Made a hardware test.

applications/lofar2/designs/lofar2_unb2c_ddrctrl/src/vhdl/lofar2_unb2c_ddrctrl.vhd

@@ -45,13 +45,12 @@ ENTITY lofar2_unb2c_ddrctrl IS
     g_stamp_date        : NATURAL := 0;  -- Date (YYYYMMDD) -- set by QSF
     g_stamp_time        : NATURAL := 0;  -- Time (HHMMSS)   -- set by QSF
     g_revision_id       : STRING  := "";  -- revision id    -- set by QSF
-    g_factory_image     : BOOLEAN := TRUE;
+    g_factory_image     : BOOLEAN := FALSE;
     g_protect_addr_range: BOOLEAN := FALSE
   );
   PORT (
     -- GENERAL
     CLK          : IN    STD_LOGIC; -- System Clock
-    tb_clk       : IN    STD_LOGIC;
     PPS          : IN    STD_LOGIC; -- System Sync
     WDI          : OUT   STD_LOGIC; -- Watchdog Clear
     INTA         : INOUT STD_LOGIC; -- FPGA interconnect line
@@ -123,7 +122,6 @@ ARCHITECTURE str OF lofar2_unb2c_ddrctrl IS
   SIGNAL xo_ethclk                  : STD_LOGIC;
   SIGNAL xo_rst                     : STD_LOGIC;
   SIGNAL xo_rst_n                   : STD_LOGIC;
-  SIGNAL not_mm_clk                 : STD_LOGIC;
   SIGNAL mm_clk                     : STD_LOGIC;
   SIGNAL mm_rst                     : STD_LOGIC := '0';
   SIGNAL st_pps                     : STD_LOGIC;
@@ -248,8 +246,6 @@ ARCHITECTURE str OF lofar2_unb2c_ddrctrl IS
 
 BEGIN
 
-  mm_clk <= tb_clk;
-
   out_siso.ready        <= vector_and(NOT out_wr_data_done_arr) AND vector_and(NOT out_wr_bsn_done_arr);
 
 
@@ -504,7 +500,7 @@ BEGIN
     xo_rst                   => xo_rst,
     xo_rst_n                 => xo_rst_n,
 
-    mm_clk                   => not_mm_clk,
+    mm_clk                   => mm_clk,
     mm_rst                   => mm_rst,
 
     dp_rst                   => st_rst,

applications/lofar2/designs/lofar2_unb2c_ddrctrl/tb/vhdl/tb_lofar2_unb2c_ddrctrl.vhd

@@ -191,7 +191,6 @@ BEGIN
     PORT MAP (
       -- GENERAL
       CLK         => st_clk,
-      tb_clk      => tb_clk,
       PPS         => pps,
       WDI         => WDI,
       INTA        => INTA,
@@ -270,6 +269,7 @@ BEGIN
     mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 0, c_bsn_start_wg, tb_clk);  -- first write low then high part
     mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 1,              0, tb_clk);  -- assume v_bsn < 2**31-1
 
+-----------------------------------------------------------------------------------------------------------------------------
 
     WAIT FOR c_mm_clk_period*24000;
     mmf_mm_bus_wr(c_mm_file_reg_stop_in, 0, 1, tb_clk);
@@ -278,7 +278,6 @@ BEGIN
     WAIT FOR c_mm_clk_period*50000;
 
 
-    assert false report "1. read whole memory!" severity note;
     FOR I IN 0 TO c_bim-1 LOOP
       FOR J IN 0 TO c_nof_streams-1 LOOP
         FOR K IN c_block_size-(c_block_size/(2**c_speed)) TO c_block_size-1 LOOP
@@ -291,15 +290,15 @@ BEGIN
       WAIT FOR c_st_clk_period*c_block_size;
     END LOOP;
 
+-----------------------------------------------------------------------------------------------------------------------------
 
-    WAIT FOR c_mm_clk_period*2400;
+    WAIT FOR c_mm_clk_period*24000;
     mmf_mm_bus_wr(c_mm_file_reg_stop_in, 0, 1, tb_clk);
     WAIT FOR c_mm_clk_period*30;
     mmf_mm_bus_wr(c_mm_file_reg_stop_in, 0, 0, tb_clk);
-    WAIT FOR c_mm_clk_period*55000;
+    WAIT FOR c_mm_clk_period*50000;
 
 
-    assert false report "2. read whole memory!" severity note;
     FOR I IN 0 TO c_bim-1 LOOP
       FOR J IN 0 TO c_nof_streams-1 LOOP
         FOR K IN c_block_size-(c_block_size/(2**c_speed)) TO c_block_size-1 LOOP
@@ -312,15 +311,16 @@ BEGIN
       WAIT FOR c_st_clk_period*c_block_size;
     END LOOP;
 
+-----------------------------------------------------------------------------------------------------------------------------
 
-    WAIT FOR c_mm_clk_period*2500;
+    WAIT FOR c_mm_clk_period*24000;
     mmf_mm_bus_wr(c_mm_file_reg_stop_in, 0, 1, tb_clk);
     WAIT FOR c_mm_clk_period*300;
     mmf_mm_bus_wr(c_mm_file_reg_stop_in, 0, 0, tb_clk);
-    WAIT FOR c_mm_clk_period*52000;
+    WAIT FOR c_mm_clk_period*50000;
+
 
 
-    assert false report "3. read whole memory!" severity note;
     FOR I IN 0 TO c_bim-1 LOOP
       FOR J IN 0 TO c_nof_streams-1 LOOP
         FOR K IN c_block_size-(c_block_size/(2**c_speed)) TO c_block_size-1 LOOP
@@ -333,6 +333,71 @@ BEGIN
       WAIT FOR c_st_clk_period*c_block_size;
     END LOOP;
 
+-----------------------------------------------------------------------------------------------------------------------------
+
+    WAIT FOR c_mm_clk_period*24000;
+    mmf_mm_bus_wr(c_mm_file_reg_stop_in, 0, 1, tb_clk);
+    WAIT FOR c_mm_clk_period*30;
+    mmf_mm_bus_wr(c_mm_file_reg_stop_in, 0, 0, tb_clk);
+    WAIT FOR c_mm_clk_period*50000;
+
+
+    FOR I IN 0 TO c_bim-1 LOOP
+      FOR J IN 0 TO c_nof_streams-1 LOOP
+        FOR K IN c_block_size-(c_block_size/(2**c_speed)) TO c_block_size-1 LOOP
+          mmf_mm_bus_rd(c_mm_file_ram_data_buf, (J*c_block_size)+K      ,     sosi_out_data(c_rd_data_w-1 DOWNTO 0), tb_clk);
+          sosi_out_data_sin(c_data_w-1 DOWNTO 0) <= sosi_out_data(c_data_w-1 DOWNTO 0);
+          mmf_mm_bus_rd( c_mm_file_ram_bsn_buf, ((J*c_block_size)+k)*2  ,      sosi_out_bsn(c_rd_data_w-1 DOWNTO 0), tb_clk);
+          mmf_mm_bus_rd( c_mm_file_ram_bsn_buf, ((J*c_block_size)+k)*2+1,  sosi_out_not_bsn(c_rd_data_w-1 DOWNTO 0), tb_clk);
+        END LOOP;
+      END LOOP;
+      WAIT FOR c_st_clk_period*(c_block_size-500);
+    END LOOP;
+
+-----------------------------------------------------------------------------------------------------------------------------
+
+    WAIT FOR c_mm_clk_period*24000;
+    mmf_mm_bus_wr(c_mm_file_reg_stop_in, 0, 1, tb_clk);
+    WAIT FOR c_mm_clk_period*30000;
+    mmf_mm_bus_wr(c_mm_file_reg_stop_in, 0, 0, tb_clk);
+    WAIT FOR c_mm_clk_period*50000;
+
+
+    FOR I IN 0 TO c_bim-1 LOOP
+      FOR J IN 0 TO c_nof_streams-1 LOOP
+        FOR K IN c_block_size-(c_block_size/(2**c_speed)) TO c_block_size-1 LOOP
+          mmf_mm_bus_rd(c_mm_file_ram_data_buf, (J*c_block_size)+K      ,     sosi_out_data(c_rd_data_w-1 DOWNTO 0), tb_clk);
+          sosi_out_data_sin(c_data_w-1 DOWNTO 0) <= sosi_out_data(c_data_w-1 DOWNTO 0);
+          mmf_mm_bus_rd( c_mm_file_ram_bsn_buf, ((J*c_block_size)+k)*2  ,      sosi_out_bsn(c_rd_data_w-1 DOWNTO 0), tb_clk);
+          mmf_mm_bus_rd( c_mm_file_ram_bsn_buf, ((J*c_block_size)+k)*2+1,  sosi_out_not_bsn(c_rd_data_w-1 DOWNTO 0), tb_clk);
+        END LOOP;
+      END LOOP;
+      WAIT FOR c_st_clk_period*(c_block_size);
+    END LOOP;
+
+-----------------------------------------------------------------------------------------------------------------------------
+
+    WAIT FOR c_mm_clk_period*24000;
+    mmf_mm_bus_wr(c_mm_file_reg_stop_in, 0, 1, tb_clk);
+    WAIT FOR c_mm_clk_period*30;
+    mmf_mm_bus_wr(c_mm_file_reg_stop_in, 0, 0, tb_clk);
+    WAIT FOR c_mm_clk_period*50000;
+
+
+    FOR I IN 0 TO c_bim-1 LOOP
+      FOR J IN 0 TO c_nof_streams-1 LOOP
+        FOR K IN c_block_size-(c_block_size/(2**c_speed)) TO c_block_size-1 LOOP
+          mmf_mm_bus_rd(c_mm_file_ram_data_buf, (J*c_block_size)+K      ,     sosi_out_data(c_rd_data_w-1 DOWNTO 0), tb_clk);
+          sosi_out_data_sin(c_data_w-1 DOWNTO 0) <= sosi_out_data(c_data_w-1 DOWNTO 0);
+          mmf_mm_bus_rd( c_mm_file_ram_bsn_buf, ((J*c_block_size)+k)*2  ,      sosi_out_bsn(c_rd_data_w-1 DOWNTO 0), tb_clk);
+          mmf_mm_bus_rd( c_mm_file_ram_bsn_buf, ((J*c_block_size)+k)*2+1,  sosi_out_not_bsn(c_rd_data_w-1 DOWNTO 0), tb_clk);
+        END LOOP;
+      END LOOP;
+      WAIT FOR c_st_clk_period*(c_block_size);
+    END LOOP;
+
+-----------------------------------------------------------------------------------------------------------------------------
+
     tb_end <= '1';
     ASSERT FALSE  REPORT "Test: OK" SEVERITY FAILURE;
     WAIT;