Added regression_test_vhdl key with some tb.

boards/uniboard1/libraries/unb1_board/hdllib.cfg

@@ -62,6 +62,10 @@ test_bench_files =
     
     tb/vhdl/tb_tb_tb_unb1_board_regression.vhd
 
+regression_test_vhdl = 
+    tb/vhdl/tb_mms_unb1_board_sens.vhd
+    tb/vhdl/tb_unb1_board_mesh_reorder_bidir.vhd
+
 
 [modelsim_project_file]
 

libraries/base/ss/hdllib.cfg

@@ -19,6 +19,9 @@ test_bench_files =
     tb/vhdl/tb_ss_wide.vhd
     tb/vhdl/tb_tb_ss.vhd
 
+regression_test_vhdl = 
+    tb/vhdl/tb_tb_ss.vhd
+
 
 [modelsim_project_file]