enabled eth frame discard function; enabled I2C SENS,PMBUS

boards/uniboard2a/libraries/unb2a_board/src/vhdl/ctrl_unb2_board.vhd

@@ -226,12 +226,12 @@ ENTITY ctrl_unb2_board IS
     TESTIO                 : INOUT STD_LOGIC_VECTOR(g_aux.testio_w-1 DOWNTO 0);
     
     -- I2C Interface to Sensors
-    SENS_SC                : INOUT STD_LOGIC := 'H';
-    SENS_SD                : INOUT STD_LOGIC := 'H';
+    SENS_SC                : INOUT STD_LOGIC := 'Z';
+    SENS_SD                : INOUT STD_LOGIC := 'Z';
 
     -- pmbus
-    PMBUS_SC               : INOUT STD_LOGIC := 'H';
-    PMBUS_SD               : INOUT STD_LOGIC := 'H';
+    PMBUS_SC               : INOUT STD_LOGIC := 'Z';
+    PMBUS_SD               : INOUT STD_LOGIC := 'Z';
     PMBUS_ALERT            : IN    STD_LOGIC := '0';
     
     -- DDR reference clock domains reset creation
@@ -679,25 +679,25 @@ BEGIN
     sda       => SENS_SD
   );
 
---  u_mms_unb2_board_pmbus : ENTITY work.mms_unb2_board_sens
---  GENERIC MAP (
---    g_sim       => g_sim,
---    g_clk_freq  => 20 * 10**6 -- (to be checked) this (re)calculation lets the I2C bus run at ~300kHz
---  )
---  PORT MAP (
---    -- Clocks and reset
---    mm_rst    => i_mm_rst,
---    mm_clk    => i_mm_clk,
---    mm_start  => mm_board_sens_start,
---    
---    -- Memory-mapped clock domain
---    reg_mosi  => reg_unb_pmbus_mosi,
---    reg_miso  => reg_unb_pmbus_miso,
---    
---    -- i2c bus
---    scl       => PMBUS_SC,
---    sda       => PMBUS_SD
---  );
+  u_mms_unb2_board_pmbus : ENTITY work.mms_unb2_board_sens
+  GENERIC MAP (
+    g_sim       => g_sim,
+    g_clk_freq  => 8*10**6 -- (to be checked) this (re)calculation lets the I2C bus run at ~300kHz @ mm_clk=50MHz
+  )
+  PORT MAP (
+    -- Clocks and reset
+    mm_rst    => i_mm_rst,
+    mm_clk    => i_mm_clk,
+    mm_start  => mm_board_sens_start,
+    
+    -- Memory-mapped clock domain
+    reg_mosi  => reg_unb_pmbus_mosi,
+    reg_miso  => reg_unb_pmbus_miso,
+    
+    -- i2c bus
+    scl       => PMBUS_SC,
+    sda       => PMBUS_SD
+  );
 
   u_mms_unb2_fpga_sens : ENTITY work.mms_unb2_fpga_sens
   GENERIC MAP (
@@ -772,7 +772,8 @@ BEGIN
     GENERIC MAP (
       g_technology         => g_technology,
       g_init_ip_address    => g_base_ip & X"0000", -- Last two bytes set by board/FPGA ID.
-      g_cross_clock_domain => g_udp_offload
+      g_cross_clock_domain => g_udp_offload,
+      g_frm_discard_en     => TRUE
     )
     PORT MAP (
       -- Clocks and reset