Fixed avoiding combinatorial latches. Removed unused x,y,z debug signals.

libraries/base/common/src/vhdl/common_mem_bus.vhd

@@ -153,9 +153,6 @@ ARCHITECTURE rtl OF common_mem_bus IS
   SIGNAL slave_mosi_arr_comb : t_mem_mosi_arr(0 TO g_nof_slaves-1) := (OTHERS=>c_mem_mosi_rst);
   SIGNAL master_miso_comb    : t_mem_miso := c_mem_miso_rst;
 
-  SIGNAL x  : NATURAL;
-  SIGNAL y  : NATURAL;
-  SIGNAL z  : NATURAL;
 BEGIN
 
   gen_single : IF g_nof_slaves=1 GENERATE 
@@ -178,8 +175,6 @@ BEGIN
           EXIT;
         END IF;
       END LOOP;
-      x <= c_mm_bus_addr_w;
-      y <= v_base;
     END PROCESS;
     
     index_pipeline(1 TO c_index_latency_max) <= index_pipeline(0 TO c_index_latency_max-1) WHEN rising_edge(mm_clk);
@@ -187,11 +182,13 @@ BEGIN
     -- Master access, can be write or read
     p_mosi : PROCESS(master_mosi, index_pipeline)
     BEGIN
+      slave_mosi_arr_comb <= (OTHERS=>master_mosi);  -- default assign to all, to avoid latches
       FOR I IN 0 TO g_nof_slaves-1 LOOP
         slave_mosi_arr_comb(I).rd <= '0';
         slave_mosi_arr_comb(I).wr <= '0';
         IF I = index_pipeline(0) THEN   -- check index for read or write access
-          slave_mosi_arr_comb(I) <= master_mosi;
+          slave_mosi_arr_comb(I).rd <= master_mosi.rd;
+          slave_mosi_arr_comb(I).wr <= master_mosi.wr;
         END IF;
       END LOOP;
     END PROCESS;
@@ -207,7 +204,7 @@ BEGIN
     p_miso : PROCESS(slave_miso_arr, index_pipeline)
       VARIABLE v_rd_latency : NATURAL;
     BEGIN
-      master_miso_comb <= c_mem_miso_rst;
+      master_miso_comb <= c_mem_miso_rst;   -- default clear, to avoid latches
       FOR I IN 0 TO g_nof_slaves-1 LOOP
         v_rd_latency := c_mosi_latency + g_rd_latency_arr(I);
         IF I = index_pipeline(v_rd_latency) THEN  -- check index for read response