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RTSD
HDL
Commits
c0ebf702
Commit
c0ebf702
authored
8 years ago
by
Pepping
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Added generic g_version
parent
7a6e3130
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boards/uniboard1/libraries/unb1_board/src/vhdl/ctrl_unb1_board.vhd
+11
-8
11 additions, 8 deletions
...iboard1/libraries/unb1_board/src/vhdl/ctrl_unb1_board.vhd
with
11 additions
and
8 deletions
boards/uniboard1/libraries/unb1_board/src/vhdl/ctrl_unb1_board.vhd
+
11
−
8
View file @
c0ebf702
...
@@ -254,6 +254,8 @@ END ctrl_unb1_board;
...
@@ -254,6 +254,8 @@ END ctrl_unb1_board;
ARCHITECTURE
str
OF
ctrl_unb1_board
IS
ARCHITECTURE
str
OF
ctrl_unb1_board
IS
CONSTANT
c_ctrl_unb1_version
:
NATURAL
:
=
1
;
-- Only increment when something changes to the register map of rom_system_info.
-- g_sel=0 for clk200_pll.vhd : used when ADUH is not used so g_dp_phs_clk_vec_w = g_nof_dp_phs_clk = 0
-- g_sel=0 for clk200_pll.vhd : used when ADUH is not used so g_dp_phs_clk_vec_w = g_nof_dp_phs_clk = 0
-- g_sel=1 for clk200_pll_p6.vhd : used when ADUH is used so g_dp_phs_clk_vec_w = g_nof_dp_phs_clk > 0
-- g_sel=1 for clk200_pll_p6.vhd : used when ADUH is used so g_dp_phs_clk_vec_w = g_nof_dp_phs_clk > 0
CONSTANT
c_dp_clk_pll_sel
:
NATURAL
:
=
sel_a_b
(
g_dp_phs_clk_vec_w
=
0
,
0
,
1
);
CONSTANT
c_dp_clk_pll_sel
:
NATURAL
:
=
sel_a_b
(
g_dp_phs_clk_vec_w
=
0
,
0
,
1
);
...
@@ -431,14 +433,15 @@ BEGIN
...
@@ -431,14 +433,15 @@ BEGIN
u_mms_unb1_board_system_info
:
ENTITY
work
.
mms_unb1_board_system_info
u_mms_unb1_board_system_info
:
ENTITY
work
.
mms_unb1_board_system_info
GENERIC
MAP
(
GENERIC
MAP
(
g_sim
=>
g_sim
,
g_sim
=>
g_sim
,
g_design_name
=>
g_design_name
,
g_design_name
=>
g_design_name
,
g_use_phy
=>
g_use_phy
,
g_use_phy
=>
g_use_phy
,
g_fw_version
=>
g_fw_version
,
g_fw_version
=>
g_fw_version
,
g_stamp_date
=>
g_stamp_date
,
g_stamp_date
=>
g_stamp_date
,
g_stamp_time
=>
g_stamp_time
,
g_stamp_time
=>
g_stamp_time
,
g_stamp_svn
=>
g_stamp_svn
,
g_stamp_svn
=>
g_stamp_svn
,
g_design_note
=>
g_design_note
g_design_note
=>
g_design_note
,
g_ctrl_unb1_version
=>
c_ctrl_unb1_version
)
)
PORT
MAP
(
PORT
MAP
(
mm_clk
=>
mm_clk
,
mm_clk
=>
mm_clk
,
...
...
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