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RTSD
HDL
Commits
c0e6e66d
Commit
c0e6e66d
authored
2 years ago
by
Reinier van der Walle
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corrected compile_ip.tcl
parent
30161261
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Pipeline
#42534
passed
2 years ago
Stage: simulation
Stage: synthesis
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libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_1910/compile_ip.tcl
+4
-4
4 additions, 4 deletions
...a10_e2sg/altera_libraries/altera_emif_1910/compile_ip.tcl
with
4 additions
and
4 deletions
libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_1910/compile_ip.tcl
+
4
−
4
View file @
c0e6e66d
...
...
@@ -41,9 +41,9 @@ set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_d
# ddr4_16g_1600_72b
set IP_DIR
"
$env
(HDL_BUILD_DIR)/
$env
(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
vlog -sv
"
$
IP_DIR/../altera_emif_arch_nf_191/sim/ip_arria10_e2sg_ddr4_16g_1600_72b_altera_emif_arch_nf_191_
slbjghy
_top.sv"
-work altera_emif_arch_nf_191
vlog -sv
"
$
IP_DIR/../altera_emif_arch_nf_191/sim/ip_arria10_e2sg_ddr4_16g_1600_72b_altera_emif_arch_nf_191_
slbjghy
_io_aux.sv"
-work altera_emif_arch_nf_191
vcom
"
$
IP_DIR/../altera_emif_arch_nf_191/sim/ip_arria10_e2sg_ddr4_16g_1600_72b_altera_emif_arch_nf_191_
slbjghy
.vhd"
-work altera_emif_arch_nf_191
vlog -sv
"
$
IP_DIR/../altera_emif_arch_nf_191/sim/ip_arria10_e2sg_ddr4_16g_1600_72b_altera_emif_arch_nf_191_
mqx4bea
_top.sv"
-work altera_emif_arch_nf_191
vlog -sv
"
$
IP_DIR/../altera_emif_arch_nf_191/sim/ip_arria10_e2sg_ddr4_16g_1600_72b_altera_emif_arch_nf_191_
mqx4bea
_io_aux.sv"
-work altera_emif_arch_nf_191
vcom
"
$
IP_DIR/../altera_emif_arch_nf_191/sim/ip_arria10_e2sg_ddr4_16g_1600_72b_altera_emif_arch_nf_191_
mqx4bea
.vhd"
-work altera_emif_arch_nf_191
# ddr4_8g_1600
set IP_DIR
"
$env
(HDL_BUILD_DIR)/
$env
(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
...
...
@@ -161,5 +161,5 @@ set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_d
vcom
"
$
IP_DIR/../altera_emif_1910/sim/ip_arria10_e2sg_ddr4_16g_1600_64b_altera_emif_1910_rvperma.vhd"
-work altera_emif_1910
set IP_DIR
"
$env
(HDL_BUILD_DIR)/
$env
(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
vcom
"
$
IP_DIR/../altera_emif_1910/sim/ip_arria10_e2sg_ddr4_16g_1600_72b_altera_emif_1910_
3t6zvq
q.vhd"
-work altera_emif_1910
vcom
"
$
IP_DIR/../altera_emif_1910/sim/ip_arria10_e2sg_ddr4_16g_1600_72b_altera_emif_1910_
vq72fg
q.vhd"
-work altera_emif_1910
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Reinier van der Walle
@walle
mentioned in commit
be60ae75
·
2 years ago
mentioned in commit
be60ae75
mentioned in commit be60ae750ce2633318578298347dd2774a278808
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Reinier van der Walle
@walle
mentioned in merge request
!307 (merged)
·
2 years ago
mentioned in merge request
!307 (merged)
mentioned in merge request !307
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Reinier van der Walle
@walle
mentioned in commit
e0f33250
·
2 years ago
mentioned in commit
e0f33250
mentioned in commit e0f33250436e4ffef3a4946fbd19bd6594f0f0f1
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