Copied from ip_arria10_e2sg/ram/. Updated information header. Changed...

Copied from ip_arria10_e2sg/ram/. Updated information header. Changed technology_name to agi027_xxxx. The copied ip_arria10_e2sg_true_dual_port_ram_dual_clock.vhd is changed for agi027_xxxx to a true dual port ram single clock, because the Agilex isn't supporting that variant.

libraries/technology/ip_agi027_xxxx/ram/ip_agi027_xxxx_simple_dual_port_ram_dual_clock.vhd

+-- -----------------------------------------------------------------------------
+--
+-- Copyright 2023
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-- -----------------------------------------------------------------------------
+--
+-- Author: 
+--   D.F. Brouwer
+-- Purpose:
+--   RadioHDL wrapper
+-- Description:
+--   Quartus II VHDL Template
+--   Simple Dual-Port RAM with different read/write addresses and
+--   different read/write clock
+-- Reference:
+--   Copied from ip_arria10_e2sg/ip_arria10_e2sg_simple_dual_port_ram_dual_clock.vhd
+--   and the inferred Altera code was obtained using template insert with
+--   Quartus 14.0a10.  
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity ip_agi027_xxxx_simple_dual_port_ram_dual_clock is
+  generic
+  (
+    DATA_WIDTH : natural := 8;
+    ADDR_WIDTH : natural := 6
+  );
+  port
+  (
+    rclk  : in std_logic;
+    wclk  : in std_logic;
+    raddr : in natural range 0 to 2**ADDR_WIDTH - 1;
+    waddr : in natural range 0 to 2**ADDR_WIDTH - 1;
+    data  : in std_logic_vector((DATA_WIDTH - 1) downto 0);
+    we    : in std_logic := '1';
+    q   : out std_logic_vector((DATA_WIDTH - 1) downto 0)
+  );
+end ip_agi027_xxxx_simple_dual_port_ram_dual_clock;
+
+architecture rtl of ip_agi027_xxxx_simple_dual_port_ram_dual_clock is
+  -- Build a 2-D array type for the RAM
+  subtype word_t is std_logic_vector((DATA_WIDTH - 1) downto 0);
+  type memory_t is array(2**ADDR_WIDTH - 1 downto 0) of word_t;
+
+  -- Declare the RAM signal.
+  signal ram : memory_t;
+begin
+  process(wclk)
+  begin
+  if(rising_edge(wclk)) then
+    if(we = '1') then
+      ram(waddr) <= data;
+    end if;
+  end if;
+  end process;
+
+  process(rclk)
+  begin
+  if(rising_edge(rclk)) then
+    q <= ram(raddr);
+  end if;
+  end process;
+end rtl;

libraries/technology/ip_agi027_xxxx/ram/ip_agi027_xxxx_simple_dual_port_ram_single_clock.vhd

+-- -----------------------------------------------------------------------------
+--
+-- Copyright 2023
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-- -----------------------------------------------------------------------------
+--
+-- Author: 
+--   D.F. Brouwer
+-- Purpose:
+--   RadioHDL wrapper
+-- Description:
+--   Quartus II VHDL Template
+--   Simple Dual-Port RAM with different read/write addresses but
+--   single read/write clock
+-- Reference:
+--   Copied from ip_arria10_e2sg/ip_arria10_e2sg_simple_dual_port_ram_simple_clock.vhd
+--   and the inferred Altera code was obtained using template insert with
+--   Quartus 14.0a10.  
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity ip_agi027_xxxx_simple_dual_port_ram_single_clock is
+  generic
+  (
+    DATA_WIDTH : natural := 8;
+    ADDR_WIDTH : natural := 6
+  );
+  port
+  (
+    clk   : in std_logic;
+    raddr : in natural range 0 to 2**ADDR_WIDTH - 1;
+    waddr : in natural range 0 to 2**ADDR_WIDTH - 1;
+    data  : in std_logic_vector((DATA_WIDTH - 1) downto 0);
+    we    : in std_logic := '1';
+    q   : out std_logic_vector((DATA_WIDTH - 1) downto 0)
+  );
+end ip_agi027_xxxx_simple_dual_port_ram_single_clock;
+
+architecture rtl of ip_agi027_xxxx_simple_dual_port_ram_single_clock is
+  -- Build a 2-D array type for the RAM
+  subtype word_t is std_logic_vector((DATA_WIDTH - 1) downto 0);
+  type memory_t is array(2**ADDR_WIDTH - 1 downto 0) of word_t;
+
+  -- Declare the RAM signal.
+  signal ram : memory_t;
+begin
+  process(clk)
+  begin
+  if(rising_edge(clk)) then
+    if(we = '1') then
+      ram(waddr) <= data;
+    end if;
+
+    -- On a read during a write to the same address, the read will
+    -- return the OLD data at the address
+    q <= ram(raddr);
+  end if;
+  end process;
+end rtl;

libraries/technology/ip_agi027_xxxx/ram/ip_agi027_xxxx_true_dual_port_ram_single_clock.vhd

+-- -----------------------------------------------------------------------------
+--
+-- Copyright 2023
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-- -----------------------------------------------------------------------------
+--
+-- Author: 
+--   D.F. Brouwer
+-- Purpose:
+--   RadioHDL wrapper
+-- Description:
+--   Quartus II VHDL Template
+--   True Dual-Port RAM with single clock
+--   Read-during-write on port A or B returns newly written data
+--   Read-during-write on port A and B returns unknown data.
+-- Reference:
+--   Copied from ip_arria10_e2sg/ip_arria10_e2sg_true_dual_port_ram_dual_clock.vhd
+--   and the inferred Altera code was obtained using template insert with
+--   Quartus 14.0a10.  
+-- Remark:
+--   The orignal file is for True Dual-Port RAM with dual clock. However, that is
+--   not supported by the Agilex 7 in the way it is used before Agilex 7.
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity ip_agi027_xxxx_true_dual_port_ram_single_clock is
+  generic
+  (
+    DATA_WIDTH : natural := 8;
+    ADDR_WIDTH : natural := 6
+  );
+  port
+  (
+    clk   : in std_logic;
+    addr_a  : in natural range 0 to 2**ADDR_WIDTH - 1;
+    addr_b  : in natural range 0 to 2**ADDR_WIDTH - 1;
+    data_a  : in std_logic_vector((DATA_WIDTH - 1) downto 0);
+    data_b  : in std_logic_vector((DATA_WIDTH - 1) downto 0);
+    we_a  : in std_logic := '1';
+    we_b  : in std_logic := '1';
+    q_a   : out std_logic_vector((DATA_WIDTH - 1) downto 0);
+    q_b   : out std_logic_vector((DATA_WIDTH - 1) downto 0)
+  );
+end ip_agi027_xxxx_true_dual_port_ram_single_clock;
+
+architecture rtl of ip_agi027_xxxx_true_dual_port_ram_single_clock is
+  -- Build a 2-D array type for the RAM
+  subtype word_t is std_logic_vector((DATA_WIDTH - 1) downto 0);
+  type memory_t is array(2**ADDR_WIDTH - 1 downto 0) of word_t;
+
+  -- Declare the RAM
+  shared variable ram : memory_t;
+begin
+  process(clk)
+  begin
+  if(rising_edge(clk)) then
+    -- Port A
+    if(we_a = '1') then
+      ram(addr_a) := data_a;
+    end if;
+    q_a <= ram(addr_a);
+    -- Port B
+    if(we_b = '1') then
+      ram(addr_b) := data_b;
+    end if;
+    q_b <= ram(addr_b);
+  end if;
+  end process;
+end rtl;