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RTSD
HDL
Commits
be1a0dae
Commit
be1a0dae
authored
3 years ago
by
Reinier van der Walle
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added fill fifo to node_sdp_correlator
parent
8db4b922
No related branches found
No related tags found
1 merge request
!204
Resolve L2SDP-627
Pipeline
#25409
passed
3 years ago
Stage: simulation
Stage: synthesis
Changes
1
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1
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1 changed file
applications/lofar2/libraries/sdp/src/vhdl/node_sdp_correlator.vhd
+35
-7
35 additions, 7 deletions
...ons/lofar2/libraries/sdp/src/vhdl/node_sdp_correlator.vhd
with
35 additions
and
7 deletions
applications/lofar2/libraries/sdp/src/vhdl/node_sdp_correlator.vhd
+
35
−
7
View file @
be1a0dae
...
...
@@ -93,6 +93,7 @@ ARCHITECTURE str OF node_sdp_correlator IS
CONSTANT
c_block_size
:
NATURAL
:
=
c_sdp_N_crosslets_max
*
c_sdp_S_pn
;
CONSTANT
c_data_w
:
NATURAL
:
=
c_sdp_W_crosslet
*
c_nof_complex
;
CONSTANT
c_mux_fifo_size
:
NATURAL
:
=
2
**
ceil_log2
(
g_P_sq
*
c_block_size
);
-- Large enough to store a block for each remote packet.
CONSTANT
c_fifo_fill_size
:
NATURAL
:
=
2
**
ceil_log2
(
3
*
c_block_size
);
-- crosslet statistics offload
SIGNAL
ram_st_offload_copi
:
t_mem_copi
:
=
c_mem_copi_rst
;
...
...
@@ -111,6 +112,8 @@ ARCHITECTURE str OF node_sdp_correlator IS
SIGNAL
ring_mux_sosi
:
t_dp_sosi
:
=
c_dp_sosi_rst
;
SIGNAL
ring_mux_siso
:
t_dp_siso
:
=
c_dp_siso_rdy
;
SIGNAL
dp_fifo_fill_sosi
:
t_dp_sosi
:
=
c_dp_sosi_rst
;
SIGNAL
dp_fifo_fill_siso
:
t_dp_siso
:
=
c_dp_siso_rdy
;
SIGNAL
rx_sosi
:
t_dp_sosi
:
=
c_dp_sosi_rst
;
SIGNAL
dispatch_invert_sosi_arr
:
t_dp_sosi_arr
(
0
TO
g_P_sq
-1
)
:
=
(
OTHERS
=>
c_dp_sosi_rst
);
SIGNAL
dispatch_sosi_arr
:
t_dp_sosi_arr
(
g_P_sq
-1
DOWNTO
0
)
:
=
(
OTHERS
=>
c_dp_sosi_rst
);
...
...
@@ -230,6 +233,35 @@ BEGIN
to_ri_sosi
<=
ring_mux_sosi
;
-- fill fifo to remove gaps
u_dp_fifo_fill_eop
:
ENTITY
dp_lib
.
dp_fifo_fill_eop
GENERIC
MAP
(
g_data_w
=>
c_longword_w
,
g_bsn_w
=>
c_dp_stream_bsn_w
,
g_empty_w
=>
c_dp_stream_empty_w
,
g_channel_w
=>
c_dp_stream_channel_w
,
g_error_w
=>
c_dp_stream_error_w
,
g_use_bsn
=>
TRUE
,
g_use_empty
=>
TRUE
,
g_use_channel
=>
TRUE
,
g_use_error
=>
TRUE
,
g_use_sync
=>
TRUE
,
g_fifo_fill
=>
c_block_size
,
g_fifo_size
=>
c_fifo_fill_size
)
PORT
MAP
(
wr_rst
=>
dp_rst
,
wr_clk
=>
dp_clk
,
rd_rst
=>
dp_rst
,
rd_clk
=>
dp_clk
,
snk_out
=>
ring_mux_siso
,
snk_in
=>
ring_mux_sosi
,
src_in
=>
dp_fifo_fill_siso
,
src_out
=>
dp_fifo_fill_sosi
);
---------------------------------------------------------------
-- Repack 64b to 32b
---------------------------------------------------------------
...
...
@@ -245,8 +277,8 @@ BEGIN
rst
=>
dp_rst
,
clk
=>
dp_clk
,
snk_in
=>
ring_mux
_sosi
,
snk_out
=>
ring_mux
_siso
,
snk_in
=>
dp_fifo_fill
_sosi
,
snk_out
=>
dp_fifo_fill
_siso
,
src_out
=>
rx_sosi
);
...
...
@@ -268,11 +300,7 @@ BEGIN
src_out_arr
=>
dispatch_invert_sosi_arr
);
p_debug
:
PROCESS
(
dispatch_invert_sosi_arr
,
xsel_data_sosi
)
BEGIN
dispatch_sosi_arr
<=
func_dp_stream_arr_reverse_range
(
dispatch_invert_sosi_arr
);
dispatch_sosi_arr
(
0
)
<=
xsel_data_sosi
;
END
PROCESS
;
---------------------------------------------------------------
...
...
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