Corrected ready = NOT waitrequest.

libraries/base/mm/src/vhdl/mm_latency_adapter.vhd

@@ -56,12 +56,14 @@ END mm_latency_adapter;
 
 ARCHITECTURE str OF mm_latency_adapter IS
 
-  -- Sum of all t_mem_mosi fields widths: 32 + 72 + 1 (wr) + 1 (rd)
-  CONSTANT c_data_w  : NATURAL := c_mem_address_w +  c_mem_data_w + 2;
+  -- Sum of all t_mem_mosi fields widths (synthesis will optimize away unused address and data bits)
+  CONSTANT c_data_w  : NATURAL := c_mem_address_w +  c_mem_data_w + 2;  -- 32 + 72 + 1 (wr) + 1 (rd) = 106
 
+  SIGNAL in_waitrequest  : STD_LOGIC;
   SIGNAL in_data         : STD_LOGIC_VECTOR(c_data_w-1 DOWNTO 0);
   SIGNAL in_val          : STD_LOGIC;
-  SIGNAL in_waitrequest  : STD_LOGIC;
+  SIGNAL in_ready        : STD_LOGIC;
+  SIGNAL out_ready       : STD_LOGIC;
   SIGNAL out_data        : STD_LOGIC_VECTOR(c_data_w-1 DOWNTO 0);
   SIGNAL out_val         : STD_LOGIC;
     
@@ -73,9 +75,14 @@ BEGIN
   p_miso : PROCESS(out_miso, in_waitrequest)
   BEGIN       
     in_miso <= out_miso;
+    --in_miso.rdval <= out_miso.rdval AND NOT in_waitrequest;
     in_miso.waitrequest <= in_waitrequest;
   END PROCESS;
 
+  -- Account for opposite meaning of waitrequest and ready
+  in_waitrequest <= NOT in_ready;
+  out_ready      <= NOT out_miso.waitrequest;
+  
   u_rl : ENTITY common_lib.common_rl_decrease
   GENERIC MAP (
     g_adapt   => g_adapt,
@@ -85,11 +92,11 @@ BEGIN
     rst           => mm_rst,
     clk           => mm_clk,
     -- ST sink: RL = 1
-    snk_out_ready => in_waitrequest,
+    snk_out_ready => in_ready,
     snk_in_dat    => in_data,
     snk_in_val    => in_val,
     -- ST source: RL = 0
-    src_in_ready  => out_miso.waitrequest,
+    src_in_ready  => out_ready,
     src_out_dat   => out_data,
     src_out_val   => out_val
   );