Initial

applications/apertif/apertif_unb1_fn_beamformer/src/vhdl/mmm_apertif_unb1_fn_beamformer.vhd

+------------------------------------------------------------------------------
+--
+-- Copyright (C) 2013
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib, unb1_board_lib, mm_lib, eth_lib, technology_lib, tech_tse_lib, tech_mac_10g_lib, bf_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE common_lib.tb_common_mem_pkg.ALL;
+USE common_lib.common_network_layers_pkg.ALL;
+USE common_lib.common_network_total_header_pkg.ALL; 
+USE common_lib.common_field_pkg.ALL;
+USE unb1_board_lib.unb1_board_pkg.ALL;
+USE unb1_board_lib.unb1_board_peripherals_pkg.ALL;
+USE mm_lib.mm_file_pkg.ALL;
+USE mm_lib.mm_file_unb_pkg.ALL;
+USE eth_lib.eth_pkg.ALL; 
+USE technology_lib.technology_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
+USE tech_tse_lib.tech_tse_pkg.ALL;
+USE tech_tse_lib.tb_tech_tse_pkg.ALL;
+USE tech_mac_10g_lib.tech_mac_10g_component_pkg.ALL;
+USE bf_lib.bf_pkg.ALL;
+USE work.apertif_unb1_fn_beamformer_udp_offload_pkg.ALL;   
+
+ENTITY mmm_apertif_unb1_fn_beamformer IS
+  GENERIC (
+    -- General
+    g_sim         : BOOLEAN := FALSE; --FALSE: use SOPC; TRUE: use mm_file I/O
+    g_sim_unb_nr  : NATURAL := 0;
+    g_sim_node_nr : NATURAL := 0;
+    g_tech_select : INTEGER := c_tech_select_default;
+    g_bf          : t_c_bf  := c_bf
+  );
+  PORT (
+    xo_clk                         : IN  STD_LOGIC;
+    xo_rst_n                       : IN  STD_LOGIC;
+    xo_rst                         : IN  STD_LOGIC;
+                                   
+    mm_rst                         : IN  STD_LOGIC;
+    mm_clk                         : OUT STD_LOGIC;
+    mm_locked                      : OUT STD_LOGIC;
+    cal_clk                        : OUT STD_LOGIC;
+                                   
+    pout_wdi                       : OUT STD_LOGIC;
+    pin_pps                        : IN  STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+
+    -- Manual WDI override
+    reg_wdi_mosi                   : OUT t_mem_mosi;
+    reg_wdi_miso                   : IN  t_mem_miso;
+                                   
+    -- system_info                 
+    reg_unb_system_info_mosi       : OUT t_mem_mosi;
+    reg_unb_system_info_miso       : IN  t_mem_miso;
+    rom_unb_system_info_mosi       : OUT t_mem_mosi;
+    rom_unb_system_info_miso       : IN  t_mem_miso;
+                                   
+    -- UniBoard I2C sensors        
+    reg_unb_sens_mosi              : OUT t_mem_mosi; 
+    reg_unb_sens_miso              : IN  t_mem_miso; 
+                                   
+    -- Diagnostics                 
+    reg_diagnostics_mosi           : OUT t_mem_mosi; 
+    reg_diagnostics_miso           : IN  t_mem_miso;
+
+    -- . tr_nonbonded with diagnostics
+    reg_tr_nonbonded_mosi          : OUT t_mem_mosi := c_mem_mosi_rst;
+    reg_tr_nonbonded_miso          : IN  t_mem_miso;
+                                   
+    -- . diag_data_buffer          
+    ram_diag_data_buf_mosi         : OUT t_mem_mosi := c_mem_mosi_rst;
+    ram_diag_data_buf_miso         : IN  t_mem_miso;  
+    reg_diag_data_buf_mosi         : OUT t_mem_mosi := c_mem_mosi_rst;
+    reg_diag_data_buf_miso         : IN  t_mem_miso;  
+                                   
+    -- . bsn_monitor               
+    reg_bsn_monitor_mosi           : OUT t_mem_mosi := c_mem_mosi_rst;
+    reg_bsn_monitor_miso           : IN  t_mem_miso;
+   
+    -- . beamformer 
+    ram_st_sst_bf_mosi             : OUT t_mem_mosi := c_mem_mosi_rst;
+    ram_st_sst_bf_miso             : IN  t_mem_miso;
+    reg_st_sst_bf_mosi             : OUT t_mem_mosi := c_mem_mosi_rst;
+    reg_st_sst_bf_miso             : IN  t_mem_miso;
+                                   
+    ram_ss_ss_wide_mosi            : OUT t_mem_mosi := c_mem_mosi_rst;
+    ram_ss_ss_wide_miso            : IN  t_mem_miso;  
+    ram_bf_weights_mosi            : OUT t_mem_mosi := c_mem_mosi_rst;
+    ram_bf_weights_miso            : IN  t_mem_miso;                  
+                                   
+    reg_diag_bg_mosi               : OUT t_mem_mosi := c_mem_mosi_rst;
+    reg_diag_bg_miso               : IN  t_mem_miso;  
+    ram_diag_bg_mosi               : OUT t_mem_mosi := c_mem_mosi_rst;
+    ram_diag_bg_miso               : IN  t_mem_miso;               
+
+    -- . dp_ram_from_mm for DP offload (header insertion)
+    reg_dp_ram_from_mm_mosi        : OUT t_mem_mosi;
+    reg_dp_ram_from_mm_miso        : IN  t_mem_miso := c_mem_miso_rst;
+    ram_dp_ram_from_mm_mosi        : OUT t_mem_mosi;
+    ram_dp_ram_from_mm_miso        : IN  t_mem_miso := c_mem_miso_rst;
+    
+    -- . UDP offload                  
+    reg_dp_split_mosi              : OUT t_mem_mosi;
+    reg_dp_split_miso              : IN  t_mem_miso := c_mem_miso_rst;
+    reg_dp_pkt_merge_mosi          : OUT t_mem_mosi;
+    reg_dp_pkt_merge_miso          : IN  t_mem_miso := c_mem_miso_rst;
+    
+    -- . 10GbE offload
+    reg_dp_offload_tx_mosi         : OUT t_mem_mosi;
+    reg_dp_offload_tx_miso         : IN  t_mem_miso;
+    reg_dp_offload_tx_hdr_dat_mosi : OUT t_mem_mosi;
+    reg_dp_offload_tx_hdr_dat_miso : IN  t_mem_miso;
+    reg_dp_offload_tx_hdr_ovr_mosi : OUT t_mem_mosi;
+    reg_dp_offload_tx_hdr_ovr_miso : IN  t_mem_miso;
+    reg_tr_10GbE_mosi              : OUT t_mem_mosi;
+    reg_tr_10GbE_miso              : IN  t_mem_miso;
+
+    reg_mdio_mosi_arr              : OUT t_mem_mosi_arr(c_unb1_board_nof_mdio-1 DOWNTO 0);
+    reg_mdio_miso_arr              : IN  t_mem_miso_arr(c_unb1_board_nof_mdio-1 DOWNTO 0);
+
+    reg_tr_xaui_mosi               : OUT t_mem_mosi;
+    reg_tr_xaui_miso               : IN  t_mem_miso;
+
+      -- eth1g
+    eth1g_tse_clk                  : OUT STD_LOGIC;
+    eth1g_mm_rst                   : OUT STD_LOGIC;
+    eth1g_tse_mosi                 : OUT t_mem_mosi;  
+    eth1g_tse_miso                 : IN  t_mem_miso;  
+    eth1g_reg_mosi                 : OUT t_mem_mosi;  
+    eth1g_reg_miso                 : IN  t_mem_miso;  
+    eth1g_reg_interrupt            : IN  STD_LOGIC; 
+    eth1g_ram_mosi                 : OUT t_mem_mosi;  
+    eth1g_ram_miso                 : IN  t_mem_miso 
+  
+  );
+END mmm_apertif_unb1_fn_beamformer;
+
+
+ARCHITECTURE str OF mmm_apertif_unb1_fn_beamformer IS
+
+  -- Custom register widths  
+  CONSTANT c_bg_diag_wave_period                 : POSITIVE := 4;    
+  CONSTANT c_ram_st_sst_bf_addr_w                : NATURAL := ceil_log2(c_bf_max_nof_bf_units*g_bf.stat_data_sz*g_bf.nof_weights*c_nof_complex);     
+  CONSTANT c_reg_st_sst_bf_addr_w                : NATURAL := ceil_log2(c_bf_max_nof_bf_units)*2;     
+  CONSTANT c_ram_ss_ss_wide_addr_w               : NATURAL := ceil_log2(c_bf_max_nof_bf_units*g_bf.nof_weights*g_bf.nof_signal_paths);
+  CONSTANT c_ram_bf_weights_addr_w               : NATURAL := ceil_log2(c_bf_max_nof_bf_units*g_bf.nof_signal_paths*g_bf.nof_weights); 
+  CONSTANT c_ram_diag_bg_addr_w                  : NATURAL := ceil_log2(c_bg_diag_wave_period) + ceil_log2(g_bf.nof_subbands*g_bf.nof_signal_paths/g_bf.nof_input_streams)+ceil_log2(g_bf.nof_input_streams); 
+  CONSTANT c_dp_ram_mm_nof_words                 : NATURAL := c_network_total_header_32b_nof_words * (c_tech_tse_data_w/c_word_w);                            
+  CONSTANT c_dp_ram_mm_adr_w                     : NATURAL := ceil_log2(g_bf.nof_bf_units * pow2(ceil_log2(c_dp_ram_mm_nof_words)));
+  CONSTANT c_reg_dp_split_nof_words              : NATURAL := 1;                                                                         
+  CONSTANT c_reg_dp_split_adr_w                  : NATURAL := ceil_log2(g_bf.nof_bf_units * pow2(ceil_log2(c_reg_dp_split_nof_words)));    
+  CONSTANT c_reg_dp_pkt_merge_nof_words          : NATURAL := 1;                                                                             
+  CONSTANT c_reg_dp_pkt_merge_adr_w              : NATURAL := ceil_log2(c_eth_nof_udp_ports * pow2(ceil_log2(c_reg_dp_pkt_merge_nof_words)));
+
+  -- 10GbE offload
+  CONSTANT c_reg_dp_offload_tx_adr_w             : NATURAL := 1;
+  CONSTANT c_reg_dp_offload_tx_hdr_dat_nof_words : NATURAL := field_nof_words(c_apertif_unb1_fn_beamformer_udp_offload_hdr_field_arr, c_word_w); -- = 26 32b words
+  CONSTANT c_reg_dp_offload_tx_hdr_dat_adr_w     : NATURAL := ceil_log2(c_reg_dp_offload_tx_hdr_dat_nof_words);                     -- = 5
+  CONSTANT c_reg_dp_offload_tx_hdr_ovr_nof_words : NATURAL := c_apertif_unb1_fn_beamformer_udp_offload_hdr_field_arr'LENGTH;                     -- = 23 override bits; one for each field; each bit in its own 32b register.
+  CONSTANT c_reg_dp_offload_tx_hdr_ovr_adr_w     : NATURAL := ceil_log2(c_reg_dp_offload_tx_hdr_ovr_nof_words);                     -- = 5
+  CONSTANT c_reg_tr_10GbE_adr_w                  : NATURAL := func_tech_mac_10g_csr_addr_w(g_tech_select);
+  CONSTANT c_xaui_mosi_addr_w                    : NATURAL := 9; --2^9 = range of 512 addresses
+  CONSTANT c_max_nof_xaui_inst                   : NATURAL := 4;
+  CONSTANT c_reg_tr_xaui_addr_w                  : NATURAL := ceil_log2(c_max_nof_xaui_inst* pow2(c_xaui_mosi_addr_w)); -- 4* 512 = 2048 addresses -> 11 address bits.
+  
+  -- Simulation
+  CONSTANT c_mm_clk_period  : TIME := 100 ps;
+  CONSTANT c_tse_clk_period : TIME := 8 ns;
+                           
+  CONSTANT c_sim_node_type  : STRING(1 TO 2):= sel_a_b(g_sim_node_nr<4, "FN", "BN");
+  CONSTANT c_sim_node_nr    : NATURAL := sel_a_b(c_sim_node_type="BN", g_sim_node_nr-4, g_sim_node_nr);
+
+  SIGNAL i_mm_clk  : STD_LOGIC := '1';
+  SIGNAL i_tse_clk : STD_LOGIC := '1';
+  
+  ----------------------------------------------------------------------------
+  -- mm_file component
+  ----------------------------------------------------------------------------
+  COMPONENT mm_file
+  GENERIC(
+    g_file_prefix       : STRING;
+    g_mm_clk_period     : TIME := c_mm_clk_period;
+    g_update_on_change  : BOOLEAN := FALSE;
+    g_mm_rd_latency     : NATURAL := 1
+  );
+  PORT (
+    mm_rst        : IN  STD_LOGIC;
+    mm_clk        : IN  STD_LOGIC;
+    mm_master_out : OUT t_mem_mosi;
+    mm_master_in  : IN  t_mem_miso 
+  );
+  END COMPONENT;               
+
+  CONSTANT c_dut_src_mac           : STD_LOGIC_VECTOR(c_network_eth_mac_slv'RANGE) := X"002286080001";
+  SIGNAL eth_psc_access            : STD_LOGIC;
+                                   
+                                   
+  SIGNAL reg_ppsh_mosi             : t_mem_mosi := c_mem_mosi_rst;
+  SIGNAL reg_ppsh_miso             : t_mem_miso := c_mem_miso_rst;
+                                   
+  SIGNAL i_eth1g_reg_mosi          : t_mem_mosi;
+  SIGNAL i_eth1g_reg_miso          : t_mem_miso;
+                                   
+  SIGNAL eth1g_reg_proc_mosi       : t_mem_mosi;
+  SIGNAL eth1g_reg_proc_miso       : t_mem_miso;
+
+  CONSTANT c_sim_eth_src_mac       : STD_LOGIC_VECTOR(c_network_eth_mac_slv'RANGE) := X"00228608" & TO_UVEC(g_sim_unb_nr, c_byte_w) & TO_UVEC(g_sim_node_nr, c_byte_w);
+  CONSTANT c_sim_eth_control_rx_en : NATURAL := 2**c_eth_mm_reg_control_bi.rx_en;
+
+  SIGNAL sim_eth_mm_bus_switch     : STD_LOGIC;
+  SIGNAL sim_eth_psc_access        : STD_LOGIC;
+                                   
+  SIGNAL sim_eth1g_reg_mosi        : t_mem_mosi;
+
+BEGIN
+
+  
+  mm_clk        <= i_mm_clk;
+  eth1g_tse_clk <= i_tse_clk;
+
+  ----------------------------------------------------------------------------
+  -- MM <-> file I/O for simulation. The files are created in $UPE/sim.
+  ----------------------------------------------------------------------------
+  gen_mm_file_io : IF g_sim = TRUE GENERATE
+
+    i_mm_clk  <= NOT i_mm_clk AFTER c_mm_clk_period/2;
+    mm_locked <= '0', '1' AFTER c_mm_clk_period*5;
+
+    i_tse_clk    <= NOT i_tse_clk AFTER c_tse_clk_period/2;
+    eth1g_mm_rst <= '1', '0' AFTER c_tse_clk_period*5;
+
+    u_mm_file_reg_unb_system_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
+                                               PORT MAP(mm_rst, i_mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
+
+    u_mm_file_rom_unb_system_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
+                                               PORT MAP(mm_rst, i_mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+
+    u_mm_file_reg_wdi             : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
+                                               PORT MAP(mm_rst, i_mm_clk, reg_wdi_mosi, reg_wdi_miso );
+
+    u_mm_file_reg_unb_sens        : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
+                                               PORT MAP(mm_rst, i_mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
+
+    u_mm_file_reg_diagnostics     : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAGNOSTICS")
+                                               PORT MAP(mm_rst, i_mm_clk, reg_diagnostics_mosi, reg_diagnostics_miso );
+
+    u_mm_file_reg_tr_nonbonded    : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_NONBONDED")
+                                               PORT MAP(mm_rst, i_mm_clk, reg_tr_nonbonded_mosi, reg_tr_nonbonded_miso );
+
+    u_mm_file_ram_diag_data_buf   : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER")
+                                               PORT MAP(mm_rst, i_mm_clk, ram_diag_data_buf_mosi, ram_diag_data_buf_miso);
+                                  
+    u_mm_file_reg_diag_data_buf   : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER")
+                                               PORT MAP(mm_rst, i_mm_clk, reg_diag_data_buf_mosi, reg_diag_data_buf_miso);
+
+    u_mm_file_reg_bsn_monitor     : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR")
+                                               PORT MAP(mm_rst, i_mm_clk, reg_bsn_monitor_mosi, reg_bsn_monitor_miso );
+
+    u_mm_file_ram_st_sst_bf       : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ST_SST")
+                                               PORT MAP(mm_rst, i_mm_clk, ram_st_sst_bf_mosi, ram_st_sst_bf_miso );
+
+    u_mm_file_reg_st_sst_bf       : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ST_SST")
+                                               PORT MAP(mm_rst, i_mm_clk, reg_st_sst_bf_mosi, reg_st_sst_bf_miso );
+
+    u_mm_file_ram_ss_ss_wide      : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SS_SS_WIDE")
+                                               PORT MAP(mm_rst, i_mm_clk, ram_ss_ss_wide_mosi, ram_ss_ss_wide_miso );
+
+    u_mm_file_ram_bf_weights      : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_BF_WEIGHTS")
+                                               PORT MAP(mm_rst, i_mm_clk, ram_bf_weights_mosi, ram_bf_weights_miso );
+
+    u_mm_file_reg_diag_bg         : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG")
+                                               PORT MAP(mm_rst, i_mm_clk, reg_diag_bg_mosi, reg_diag_bg_miso );
+                                
+    u_mm_file_ram_diag_bg         : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG")
+                                               PORT MAP(mm_rst, i_mm_clk, ram_diag_bg_mosi, ram_diag_bg_miso );
+
+    u_mm_file_reg_dp_ram_from_mm  : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_RAM_FROM_MM")
+                                               PORT MAP(mm_rst, i_mm_clk, reg_dp_ram_from_mm_mosi, reg_dp_ram_from_mm_miso );
+
+    u_mm_file_ram_dp_ram_from_mm  : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DP_RAM_FROM_MM")
+                                               PORT MAP(mm_rst, i_mm_clk, ram_dp_ram_from_mm_mosi, ram_dp_ram_from_mm_miso );
+
+    u_mm_file_reg_dp_split        : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_SPLIT")
+                                               PORT MAP(mm_rst, i_mm_clk, reg_dp_split_mosi, reg_dp_split_miso );
+
+    u_mm_file_reg_dp_pkt_merge    : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_PKT_MERGE")
+                                               PORT MAP(mm_rst, i_mm_clk, reg_dp_pkt_merge_mosi, reg_dp_pkt_merge_miso );
+
+    u_mm_file_reg_eth             : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
+                                               PORT MAP(mm_rst, i_mm_clk, i_eth1g_reg_mosi, eth1g_reg_miso );
+
+    ----------------------------------------------------------------------------
+    -- 1GbE setup sequence normally performed by unb_os@NIOS
+    ----------------------------------------------------------------------------
+    p_eth_setup : PROCESS
+    BEGIN
+      sim_eth_mm_bus_switch <= '1';
+
+      eth1g_tse_mosi.wr <= '0';
+      eth1g_tse_mosi.rd <= '0';
+      WAIT FOR 400 ns;
+      WAIT UNTIL rising_edge(i_mm_clk);
+      proc_tech_tse_setup(c_tech_stratixiv, FALSE, c_tech_tse_tx_fifo_depth, c_tech_tse_rx_fifo_depth, c_tech_tse_tx_ready_latency, c_sim_eth_src_mac, sim_eth_psc_access, i_mm_clk, eth1g_tse_miso, eth1g_tse_mosi);
+
+      -- Enable RX
+      proc_mem_mm_bus_wr(c_eth_reg_control_wi+0, c_sim_eth_control_rx_en, i_mm_clk, eth1g_reg_miso, sim_eth1g_reg_mosi);  -- control rx en
+      sim_eth_mm_bus_switch <= '0';
+
+      WAIT;
+    END PROCESS;
+
+    p_switch : PROCESS(sim_eth_mm_bus_switch, sim_eth1g_reg_mosi, i_eth1g_reg_mosi)
+    BEGIN
+      IF sim_eth_mm_bus_switch = '1' THEN
+          eth1g_reg_mosi <= sim_eth1g_reg_mosi;
+        ELSE
+          eth1g_reg_mosi <= i_eth1g_reg_mosi;
+        END IF;
+    END PROCESS;
+
+    ----------------------------------------------------------------------------
+    -- Procedure that polls a sim control file that can be used to e.g. get
+    -- the simulation time in ns
+    ----------------------------------------------------------------------------
+    mmf_poll_sim_ctrl_file(c_mmf_unb_file_path & "sim.ctrl", c_mmf_unb_file_path & "sim.stat");
+
+  END GENERATE;
+
+  -----------------------------------------------------------------------------
+  -- SOPC system
+  -----------------------------------------------------------------------------
+  ----------------------------------------------------------------------------
+  -- SOPC for synthesis
+  ----------------------------------------------------------------------------
+  gen_sopc : IF g_sim = FALSE GENERATE
+    u_sopc : ENTITY work.sopc_apertif_unb1_fn_beamformer
+    PORT MAP (
+      -- 1) global signals:
+      clk_0                                                   => xo_clk,            -- PLL reference = 25 MHz from ETH_clk pin
+      reset_n                                                 => xo_rst_n,
+      mm_clk                                                  => mm_clk,            -- PLL clk[0] = 125 MHz system clock that the NIOS2 and the MM bus run on
+      cal_clk                                                 => cal_clk,           -- PLL clk[1] =  40 MHz calibration clock for the IO reconfiguration
+      tse_clk                                                 => eth1g_tse_clk,     -- PLL clk[2] = 125 MHz dedicated clock for the 1 Gbit Ethernet unit
+    
+      -- the_altpll_0
+      areset_to_the_altpll_0                                  => '0',
+      locked_from_the_altpll_0                                => mm_locked,
+      phasedone_from_the_altpll_0                             => OPEN,
+    
+      -- the_avs_eth_0
+      coe_clk_export_from_the_avs_eth_0                       => OPEN,
+      coe_reset_export_from_the_avs_eth_0                     => eth1g_mm_rst,
+      coe_tse_address_export_from_the_avs_eth_0               => eth1g_tse_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tse_adr_w-1 DOWNTO 0),
+      coe_tse_write_export_from_the_avs_eth_0                 => eth1g_tse_mosi.wr,
+      coe_tse_writedata_export_from_the_avs_eth_0             => eth1g_tse_mosi.wrdata(c_word_w-1 DOWNTO 0),
+      coe_tse_read_export_from_the_avs_eth_0                  => eth1g_tse_mosi.rd,
+      coe_tse_readdata_export_to_the_avs_eth_0                => eth1g_tse_miso.rddata(c_word_w-1 DOWNTO 0),
+      coe_tse_waitrequest_export_to_the_avs_eth_0             => eth1g_tse_miso.waitrequest,
+      coe_reg_address_export_from_the_avs_eth_0               => eth1g_reg_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_eth_adr_w-1 DOWNTO 0),
+      coe_reg_write_export_from_the_avs_eth_0                 => eth1g_reg_mosi.wr,
+      coe_reg_writedata_export_from_the_avs_eth_0             => eth1g_reg_mosi.wrdata(c_word_w-1 DOWNTO 0),
+      coe_reg_read_export_from_the_avs_eth_0                  => eth1g_reg_mosi.rd,
+      coe_reg_readdata_export_to_the_avs_eth_0                => eth1g_reg_miso.rddata(c_word_w-1 DOWNTO 0),
+      coe_irq_export_to_the_avs_eth_0                         => eth1g_reg_interrupt,
+      coe_ram_address_export_from_the_avs_eth_0               => eth1g_ram_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_eth_adr_w-1 DOWNTO 0),
+      coe_ram_write_export_from_the_avs_eth_0                 => eth1g_ram_mosi.wr,
+      coe_ram_writedata_export_from_the_avs_eth_0             => eth1g_ram_mosi.wrdata(c_word_w-1 DOWNTO 0),
+      coe_ram_read_export_from_the_avs_eth_0                  => eth1g_ram_mosi.rd,
+      coe_ram_readdata_export_to_the_avs_eth_0                => eth1g_ram_miso.rddata(c_word_w-1 DOWNTO 0),
+    
+      -- the_reg_unb_sens
+      coe_address_export_from_the_reg_unb_sens                => reg_unb_sens_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_sens_adr_w-1 DOWNTO 0),
+      coe_clk_export_from_the_reg_unb_sens                    => OPEN,
+      coe_read_export_from_the_reg_unb_sens                   => reg_unb_sens_mosi.rd,
+      coe_readdata_export_to_the_reg_unb_sens                 => reg_unb_sens_miso.rddata(c_word_w-1 DOWNTO 0),
+      coe_reset_export_from_the_reg_unb_sens                  => OPEN,
+      coe_write_export_from_the_reg_unb_sens                  => reg_unb_sens_mosi.wr,
+      coe_writedata_export_from_the_reg_unb_sens              => reg_unb_sens_mosi.wrdata(c_word_w-1 DOWNTO 0),
+    
+      -- the_reg_tr_nonbonded_mesh
+      coe_address_export_from_the_reg_tr_nonbonded_mesh       => reg_tr_nonbonded_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tr_nonbonded_adr_w-1 DOWNTO 0),
+      coe_clk_export_from_the_reg_tr_nonbonded_mesh           => OPEN,
+      coe_read_export_from_the_reg_tr_nonbonded_mesh          => reg_tr_nonbonded_mosi.rd,
+      coe_readdata_export_to_the_reg_tr_nonbonded_mesh        => reg_tr_nonbonded_miso.rddata(c_word_w-1 DOWNTO 0),
+      coe_reset_export_from_the_reg_tr_nonbonded_mesh         => OPEN,
+      coe_write_export_from_the_reg_tr_nonbonded_mesh         => reg_tr_nonbonded_mosi.wr,
+      coe_writedata_export_from_the_reg_tr_nonbonded_mesh     => reg_tr_nonbonded_mosi.wrdata(c_word_w-1 DOWNTO 0),
+    
+      -- the_reg_diagnostics_mesh
+      coe_address_export_from_the_reg_diagnostics_mesh        => reg_diagnostics_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_diagnostics_adr_w-1 DOWNTO 0),
+      coe_clk_export_from_the_reg_diagnostics_mesh            => OPEN,
+      coe_read_export_from_the_reg_diagnostics_mesh           => reg_diagnostics_mosi.rd,
+      coe_readdata_export_to_the_reg_diagnostics_mesh         => reg_diagnostics_miso.rddata(c_word_w-1 DOWNTO 0),
+      coe_reset_export_from_the_reg_diagnostics_mesh          => OPEN,
+      coe_write_export_from_the_reg_diagnostics_mesh          => reg_diagnostics_mosi.wr,
+      coe_writedata_export_from_the_reg_diagnostics_mesh      => reg_diagnostics_mosi.wrdata(c_word_w-1 DOWNTO 0),
+    
+      -- the_ram_diag_data_buffer
+      coe_address_export_from_the_ram_diag_data_buffer        => ram_diag_data_buf_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_diag_db_adr_w-1 DOWNTO 0),
+      coe_clk_export_from_the_ram_diag_data_buffer            => OPEN,
+      coe_read_export_from_the_ram_diag_data_buffer           => ram_diag_data_buf_mosi.rd,
+      coe_readdata_export_to_the_ram_diag_data_buffer         => ram_diag_data_buf_miso.rddata(c_word_w-1 DOWNTO 0),
+      coe_reset_export_from_the_ram_diag_data_buffer          => OPEN,
+      coe_write_export_from_the_ram_diag_data_buffer          => ram_diag_data_buf_mosi.wr,
+      coe_writedata_export_from_the_ram_diag_data_buffer      => ram_diag_data_buf_mosi.wrdata(c_word_w-1 DOWNTO 0),
+    
+      -- the_reg_diag_data_buffer
+      coe_address_export_from_the_reg_diag_data_buffer        => reg_diag_data_buf_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_diag_db_adr_w-1 DOWNTO 0),
+      coe_clk_export_from_the_reg_diag_data_buffer            => OPEN,
+      coe_read_export_from_the_reg_diag_data_buffer           => reg_diag_data_buf_mosi.rd,
+      coe_readdata_export_to_the_reg_diag_data_buffer         => reg_diag_data_buf_miso.rddata(c_word_w-1 DOWNTO 0),
+      coe_reset_export_from_the_reg_diag_data_buffer          => OPEN,
+      coe_write_export_from_the_reg_diag_data_buffer          => reg_diag_data_buf_mosi.wr,
+      coe_writedata_export_from_the_reg_diag_data_buffer      => reg_diag_data_buf_mosi.wrdata(c_word_w-1 DOWNTO 0),
+    
+      -- the_reg_bsn_monitor
+      coe_address_export_from_the_reg_bsn_monitor             => reg_bsn_monitor_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_bsn_monitor_adr_w-1 DOWNTO 0),
+      coe_clk_export_from_the_reg_bsn_monitor                 => OPEN,
+      coe_read_export_from_the_reg_bsn_monitor                => reg_bsn_monitor_mosi.rd,
+      coe_readdata_export_to_the_reg_bsn_monitor              => reg_bsn_monitor_miso.rddata(c_word_w-1 DOWNTO 0),
+      coe_reset_export_from_the_reg_bsn_monitor               => OPEN,
+      coe_write_export_from_the_reg_bsn_monitor               => reg_bsn_monitor_mosi.wr,
+      coe_writedata_export_from_the_reg_bsn_monitor           => reg_bsn_monitor_mosi.wrdata(c_word_w-1 DOWNTO 0),
+      
+      -- the_pio_debug_wave
+      out_port_from_the_pio_debug_wave                        => OPEN,
+    
+      -- the_pio_pps
+      in_port_to_the_pio_pps                                  => pin_pps,
+    
+      -- the_pio_system_info: actually a avs_common_mm instance
+      coe_clk_export_from_the_pio_system_info                 => OPEN,
+      coe_reset_export_from_the_pio_system_info               => OPEN,
+      coe_address_export_from_the_pio_system_info             => reg_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w-1 DOWNTO 0), 
+      coe_read_export_from_the_pio_system_info                => reg_unb_system_info_mosi.rd,
+      coe_readdata_export_to_the_pio_system_info              => reg_unb_system_info_miso.rddata(c_word_w-1 DOWNTO 0),
+      coe_write_export_from_the_pio_system_info               => reg_unb_system_info_mosi.wr,
+      coe_writedata_export_from_the_pio_system_info           => reg_unb_system_info_mosi.wrdata(c_word_w-1 DOWNTO 0),
+    
+      -- the_rom_system_info
+      coe_clk_export_from_the_rom_system_info                 => OPEN,
+      coe_reset_export_from_the_rom_system_info               => OPEN,
+      coe_address_export_from_the_rom_system_info             => rom_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w-1 DOWNTO 0), 
+      coe_read_export_from_the_rom_system_info                => rom_unb_system_info_mosi.rd,
+      coe_readdata_export_to_the_rom_system_info              => rom_unb_system_info_miso.rddata(c_word_w-1 DOWNTO 0),
+      coe_write_export_from_the_rom_system_info               => rom_unb_system_info_mosi.wr,
+      coe_writedata_export_from_the_rom_system_info           => rom_unb_system_info_mosi.wrdata(c_word_w-1 DOWNTO 0),
+    
+      -- the_pio_wdi
+      out_port_from_the_pio_wdi                               => pout_wdi,
+    
+      -- the_reg_wdi: Manual WDI override; causes FPGA reconfiguration if WDI is enabled (g_use_phy).
+      coe_clk_export_from_the_reg_wdi                         => OPEN,
+      coe_reset_export_from_the_reg_wdi                       => OPEN,
+      coe_address_export_from_the_reg_wdi                     => reg_wdi_mosi.address(0), 
+      coe_read_export_from_the_reg_wdi                        => reg_wdi_mosi.rd,
+      coe_readdata_export_to_the_reg_wdi                      => reg_wdi_miso.rddata(c_word_w-1 DOWNTO 0),
+      coe_write_export_from_the_reg_wdi                       => reg_wdi_mosi.wr,
+      coe_writedata_export_from_the_reg_wdi                   => reg_wdi_mosi.wrdata(c_word_w-1 DOWNTO 0),
+    
+      -- the_ram_st_sst
+      coe_address_export_from_the_ram_st_sst                  => ram_st_sst_bf_mosi.address(c_ram_st_sst_bf_addr_w-1 DOWNTO 0),
+      coe_clk_export_from_the_ram_st_sst                      => OPEN,                                           
+      coe_read_export_from_the_ram_st_sst                     => ram_st_sst_bf_mosi.rd,                                 
+      coe_readdata_export_to_the_ram_st_sst                   => ram_st_sst_bf_miso.rddata(c_word_w-1 DOWNTO 0),        
+      coe_reset_export_from_the_ram_st_sst                    => OPEN,                                           
+      coe_write_export_from_the_ram_st_sst                    => ram_st_sst_bf_mosi.wr,                                 
+      coe_writedata_export_from_the_ram_st_sst                => ram_st_sst_bf_mosi.wrdata(c_word_w-1 DOWNTO 0),        
+    
+      -- the_reg_st_sst
+      coe_address_export_from_the_reg_st_sst                  => reg_st_sst_bf_mosi.address(c_reg_st_sst_bf_addr_w-1 DOWNTO 0),
+      coe_clk_export_from_the_reg_st_sst                      => OPEN,                                           
+      coe_read_export_from_the_reg_st_sst                     => reg_st_sst_bf_mosi.rd,                                 
+      coe_readdata_export_to_the_reg_st_sst                   => reg_st_sst_bf_miso.rddata(c_word_w-1 DOWNTO 0),        
+      coe_reset_export_from_the_reg_st_sst                    => OPEN,                                           
+      coe_write_export_from_the_reg_st_sst                    => reg_st_sst_bf_mosi.wr,                                 
+      coe_writedata_export_from_the_reg_st_sst                => reg_st_sst_bf_mosi.wrdata(c_word_w-1 DOWNTO 0),        
+    
+      -- the_ram_ss_ss_wide
+      coe_address_export_from_the_ram_ss_ss_wide              => ram_ss_ss_wide_mosi.address(c_ram_ss_ss_wide_addr_w-1 DOWNTO 0), 
+      coe_clk_export_from_the_ram_ss_ss_wide                  => OPEN,                                            
+      coe_read_export_from_the_ram_ss_ss_wide                 => ram_ss_ss_wide_mosi.rd,                                  
+      coe_readdata_export_to_the_ram_ss_ss_wide               => ram_ss_ss_wide_miso.rddata(c_word_w-1 DOWNTO 0),         
+      coe_reset_export_from_the_ram_ss_ss_wide                => OPEN,                                            
+      coe_write_export_from_the_ram_ss_ss_wide                => ram_ss_ss_wide_mosi.wr,                                  
+      coe_writedata_export_from_the_ram_ss_ss_wide            => ram_ss_ss_wide_mosi.wrdata(c_word_w-1 DOWNTO 0),         
+    
+      -- the_ram_bf_weights
+      coe_address_export_from_the_ram_bf_weights              => ram_bf_weights_mosi.address(c_ram_bf_weights_addr_w-1 DOWNTO 0), 
+      coe_clk_export_from_the_ram_bf_weights                  => OPEN,                                                    
+      coe_read_export_from_the_ram_bf_weights                 => ram_bf_weights_mosi.rd,                                      
+      coe_readdata_export_to_the_ram_bf_weights               => ram_bf_weights_miso.rddata(c_word_w-1 DOWNTO 0),             
+      coe_reset_export_from_the_ram_bf_weights                => OPEN,                                                    
+      coe_write_export_from_the_ram_bf_weights                => ram_bf_weights_mosi.wr,                                      
+      coe_writedata_export_from_the_ram_bf_weights            => ram_bf_weights_mosi.wrdata(c_word_w-1 DOWNTO 0),             
+    
+      -- the_reg_bg_diag_bg
+      coe_address_export_from_the_reg_diag_bg                 => reg_diag_bg_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_diag_bg_adr_w-1 DOWNTO 0),  
+      coe_clk_export_from_the_reg_diag_bg                     => OPEN,                                                   
+      coe_read_export_from_the_reg_diag_bg                    => reg_diag_bg_mosi.rd,                                      
+      coe_readdata_export_to_the_reg_diag_bg                  => reg_diag_bg_miso.rddata(c_word_w-1 DOWNTO 0),             
+      coe_reset_export_from_the_reg_diag_bg                   => OPEN,                                                   
+      coe_write_export_from_the_reg_diag_bg                   => reg_diag_bg_mosi.wr,                                      
+      coe_writedata_export_from_the_reg_diag_bg               => reg_diag_bg_mosi.wrdata(c_word_w-1 DOWNTO 0),             
+    
+      -- the_ram_diag_bg
+      coe_address_export_from_the_ram_diag_bg                 => ram_diag_bg_mosi.address(c_ram_diag_bg_addr_w-1 DOWNTO 0),
+      coe_clk_export_from_the_ram_diag_bg                     => OPEN,                                                   
+      coe_read_export_from_the_ram_diag_bg                    => ram_diag_bg_mosi.rd,                                     
+      coe_readdata_export_to_the_ram_diag_bg                  => ram_diag_bg_miso.rddata(c_word_w-1 DOWNTO 0),            
+      coe_reset_export_from_the_ram_diag_bg                   => OPEN,                                                   
+      coe_write_export_from_the_ram_diag_bg                   => ram_diag_bg_mosi.wr,                                     
+      coe_writedata_export_from_the_ram_diag_bg               => ram_diag_bg_mosi.wrdata(c_word_w-1 DOWNTO 0),  
+    
+      -- the_reg_dp_ram_from_mm 
+      coe_clk_export_from_the_reg_dp_ram_from_mm              => OPEN,
+      coe_reset_export_from_the_reg_dp_ram_from_mm            => OPEN,
+      coe_address_export_from_the_reg_dp_ram_from_mm          => reg_dp_ram_from_mm_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_dp_ram_from_mm_adr_w-1 DOWNTO 0),
+      coe_read_export_from_the_reg_dp_ram_from_mm             => reg_dp_ram_from_mm_mosi.rd,
+      coe_readdata_export_to_the_reg_dp_ram_from_mm           => reg_dp_ram_from_mm_miso.rddata(c_word_w-1 DOWNTO 0),
+      coe_write_export_from_the_reg_dp_ram_from_mm            => reg_dp_ram_from_mm_mosi.wr,
+      coe_writedata_export_from_the_reg_dp_ram_from_mm        => reg_dp_ram_from_mm_mosi.wrdata(c_word_w-1 DOWNTO 0), 
+    
+      -- the_ram_dp_ram_from_mm 
+      coe_clk_export_from_the_ram_dp_ram_from_mm              => OPEN,
+      coe_reset_export_from_the_ram_dp_ram_from_mm            => OPEN,
+      coe_address_export_from_the_ram_dp_ram_from_mm          => ram_dp_ram_from_mm_mosi.address(c_dp_ram_mm_adr_w-1 DOWNTO 0),
+      coe_read_export_from_the_ram_dp_ram_from_mm             => ram_dp_ram_from_mm_mosi.rd,
+      coe_readdata_export_to_the_ram_dp_ram_from_mm           => ram_dp_ram_from_mm_miso.rddata(c_word_w-1 DOWNTO 0),
+      coe_write_export_from_the_ram_dp_ram_from_mm            => ram_dp_ram_from_mm_mosi.wr,
+      coe_writedata_export_from_the_ram_dp_ram_from_mm        => ram_dp_ram_from_mm_mosi.wrdata(c_word_w-1 DOWNTO 0),
+    
+      -- the_reg_dp_split
+      coe_clk_export_from_the_reg_dp_split                    => OPEN,
+      coe_reset_export_from_the_reg_dp_split                  => OPEN,
+      coe_address_export_from_the_reg_dp_split                => reg_dp_split_mosi.address(c_reg_dp_split_adr_w-1 DOWNTO 0),
+      coe_read_export_from_the_reg_dp_split                   => reg_dp_split_mosi.rd,
+      coe_readdata_export_to_the_reg_dp_split                 => reg_dp_split_miso.rddata(c_word_w-1 DOWNTO 0),
+      coe_write_export_from_the_reg_dp_split                  => reg_dp_split_mosi.wr,
+      coe_writedata_export_from_the_reg_dp_split              => reg_dp_split_mosi.wrdata(c_word_w-1 DOWNTO 0),
+    
+      -- the_reg_dp_pkt_merge
+      coe_clk_export_from_the_reg_dp_pkt_merge                => OPEN,
+      coe_reset_export_from_the_reg_dp_pkt_merge              => OPEN,
+      coe_address_export_from_the_reg_dp_pkt_merge            => reg_dp_pkt_merge_mosi.address(c_reg_dp_pkt_merge_adr_w-1 DOWNTO 0),
+      coe_read_export_from_the_reg_dp_pkt_merge               => reg_dp_pkt_merge_mosi.rd,
+      coe_readdata_export_to_the_reg_dp_pkt_merge             => reg_dp_pkt_merge_miso.rddata(c_word_w-1 DOWNTO 0),
+      coe_write_export_from_the_reg_dp_pkt_merge              => reg_dp_pkt_merge_mosi.wr,
+      coe_writedata_export_from_the_reg_dp_pkt_merge          => reg_dp_pkt_merge_mosi.wrdata(c_word_w-1 DOWNTO 0),
+    
+      -- the_reg_dp_offload_tx
+      coe_address_export_from_the_reg_dp_offload_tx           => reg_dp_offload_tx_mosi.address(0),
+      coe_clk_export_from_the_reg_dp_offload_tx               => OPEN,
+      coe_read_export_from_the_reg_dp_offload_tx              => reg_dp_offload_tx_mosi.rd,
+      coe_readdata_export_to_the_reg_dp_offload_tx            => reg_dp_offload_tx_miso.rddata(c_word_w-1 DOWNTO 0),
+      coe_reset_export_from_the_reg_dp_offload_tx             => OPEN,
+      coe_write_export_from_the_reg_dp_offload_tx             => reg_dp_offload_tx_mosi.wr,
+      coe_writedata_export_from_the_reg_dp_offload_tx         => reg_dp_offload_tx_mosi.wrdata(c_word_w-1 DOWNTO 0),
+    
+      -- the_reg_dp_offload_tx_hdr_dat
+      coe_address_export_from_the_reg_dp_offload_tx_hdr_dat   => reg_dp_offload_tx_hdr_dat_mosi.address(c_reg_dp_offload_tx_hdr_dat_adr_w-1 DOWNTO 0),
+      coe_clk_export_from_the_reg_dp_offload_tx_hdr_dat       => OPEN,
+      coe_read_export_from_the_reg_dp_offload_tx_hdr_dat      => reg_dp_offload_tx_hdr_dat_mosi.rd,
+      coe_readdata_export_to_the_reg_dp_offload_tx_hdr_dat    => reg_dp_offload_tx_hdr_dat_miso.rddata(c_word_w-1 DOWNTO 0),
+      coe_reset_export_from_the_reg_dp_offload_tx_hdr_dat     => OPEN,
+      coe_write_export_from_the_reg_dp_offload_tx_hdr_dat     => reg_dp_offload_tx_hdr_dat_mosi.wr,
+      coe_writedata_export_from_the_reg_dp_offload_tx_hdr_dat => reg_dp_offload_tx_hdr_dat_mosi.wrdata(c_word_w-1 DOWNTO 0),
+    
+      -- the_reg_dp_offload_tx_hdr_ovr
+      coe_address_export_from_the_reg_dp_offload_tx_hdr_ovr   => reg_dp_offload_tx_hdr_ovr_mosi.address(c_reg_dp_offload_tx_hdr_ovr_adr_w-1 DOWNTO 0),
+      coe_clk_export_from_the_reg_dp_offload_tx_hdr_ovr       => OPEN,
+      coe_read_export_from_the_reg_dp_offload_tx_hdr_ovr      => reg_dp_offload_tx_hdr_ovr_mosi.rd,
+      coe_readdata_export_to_the_reg_dp_offload_tx_hdr_ovr    => reg_dp_offload_tx_hdr_ovr_miso.rddata(c_word_w-1 DOWNTO 0),
+      coe_reset_export_from_the_reg_dp_offload_tx_hdr_ovr     => OPEN,
+      coe_write_export_from_the_reg_dp_offload_tx_hdr_ovr     => reg_dp_offload_tx_hdr_ovr_mosi.wr,
+      coe_writedata_export_from_the_reg_dp_offload_tx_hdr_ovr => reg_dp_offload_tx_hdr_ovr_mosi.wrdata(c_word_w-1 DOWNTO 0),
+    
+      -- the_reg_tr_10GbE 
+      coe_clk_export_from_the_reg_tr_10GbE                    => OPEN,
+      coe_reset_export_from_the_reg_tr_10GbE                  => OPEN,
+      coe_address_export_from_the_reg_tr_10GbE                => reg_tr_10GbE_mosi.address(c_reg_tr_10GbE_adr_w-1 DOWNTO 0),
+      coe_read_export_from_the_reg_tr_10GbE                   => reg_tr_10GbE_mosi.rd,
+      coe_readdata_export_to_the_reg_tr_10GbE                 => reg_tr_10GbE_miso.rddata(c_word_w-1 DOWNTO 0),
+      coe_waitrequest_export_to_the_reg_tr_10GbE              => reg_tr_10GbE_miso.waitrequest,
+      coe_write_export_from_the_reg_tr_10GbE                  => reg_tr_10GbE_mosi.wr,
+      coe_writedata_export_from_the_reg_tr_10GbE              => reg_tr_10GbE_mosi.wrdata(c_word_w-1 DOWNTO 0),
+    
+      -- the_reg_mdio_0
+      coe_clk_export_from_the_reg_mdio_0                      => OPEN,
+      coe_reset_export_from_the_reg_mdio_0                    => OPEN,
+      coe_address_export_from_the_reg_mdio_0                  => reg_mdio_mosi_arr(0).address(c_unb1_board_peripherals_mm_reg_default.reg_mdio_adr_w-1 DOWNTO 0),
+      coe_read_export_from_the_reg_mdio_0                     => reg_mdio_mosi_arr(0).rd,
+      coe_readdata_export_to_the_reg_mdio_0                   => reg_mdio_miso_arr(0).rddata(c_word_w-1 DOWNTO 0),
+      coe_write_export_from_the_reg_mdio_0                    => reg_mdio_mosi_arr(0).wr,
+      coe_writedata_export_from_the_reg_mdio_0                => reg_mdio_mosi_arr(0).wrdata(c_word_w-1 DOWNTO 0),
+    
+      -- the_reg_mdio_1
+      coe_clk_export_from_the_reg_mdio_1                      => OPEN,
+      coe_reset_export_from_the_reg_mdio_1                    => OPEN,
+      coe_address_export_from_the_reg_mdio_1                  => reg_mdio_mosi_arr(1).address(c_unb1_board_peripherals_mm_reg_default.reg_mdio_adr_w-1 DOWNTO 0),
+      coe_read_export_from_the_reg_mdio_1                     => reg_mdio_mosi_arr(1).rd,
+      coe_readdata_export_to_the_reg_mdio_1                   => reg_mdio_miso_arr(1).rddata(c_word_w-1 DOWNTO 0),
+      coe_write_export_from_the_reg_mdio_1                    => reg_mdio_mosi_arr(1).wr,
+      coe_writedata_export_from_the_reg_mdio_1                => reg_mdio_mosi_arr(1).wrdata(c_word_w-1 DOWNTO 0),
+    
+      -- the_reg_mdio_2
+      coe_clk_export_from_the_reg_mdio_2                      => OPEN,
+      coe_reset_export_from_the_reg_mdio_2                    => OPEN,
+      coe_address_export_from_the_reg_mdio_2                  => reg_mdio_mosi_arr(2).address(c_unb1_board_peripherals_mm_reg_default.reg_mdio_adr_w-1 DOWNTO 0),
+      coe_read_export_from_the_reg_mdio_2                     => reg_mdio_mosi_arr(2).rd,
+      coe_readdata_export_to_the_reg_mdio_2                   => reg_mdio_miso_arr(2).rddata(c_word_w-1 DOWNTO 0),
+      coe_write_export_from_the_reg_mdio_2                    => reg_mdio_mosi_arr(2).wr,
+      coe_writedata_export_from_the_reg_mdio_2                => reg_mdio_mosi_arr(2).wrdata(c_word_w-1 DOWNTO 0),
+    
+      -- the_reg_tr_xaui 
+      coe_clk_export_from_the_reg_tr_xaui                     => OPEN,
+      coe_reset_export_from_the_reg_tr_xaui                   => OPEN,
+      coe_address_export_from_the_reg_tr_xaui                 => reg_tr_xaui_mosi.address(c_reg_tr_xaui_addr_w-1 DOWNTO 0),
+      coe_read_export_from_the_reg_tr_xaui                    => reg_tr_xaui_mosi.rd,
+      coe_readdata_export_to_the_reg_tr_xaui                  => reg_tr_xaui_miso.rddata(c_word_w-1 DOWNTO 0),
+      coe_waitrequest_export_to_the_reg_tr_xaui               => reg_tr_xaui_miso.waitrequest,
+      coe_write_export_from_the_reg_tr_xaui                   => reg_tr_xaui_mosi.wr,
+      coe_writedata_export_from_the_reg_tr_xaui               => reg_tr_xaui_mosi.wrdata(c_word_w-1 DOWNTO 0)
+    );
+  END GENERATE;
+  
+END;
+
+
+
+
+
+
+
+
+
+
+
+