Skip to content
Snippets Groups Projects
Commit bdc2bd37 authored by Daniel van der Schuur's avatar Daniel van der Schuur
Browse files

-Fixed hdllib.cfg files so they copy required HEX/MIF files; 

-Stripped irrelevant items from the test bench.
parent 3ff235c1
No related branches found
No related tags found
No related merge requests found
Show whitespace changes
Inline Side-by-side
applications/apertif/systems/apertif_bf_xc/hdllib.cfg
+ 1
− 1
View file @ bdc2bd37
hdl_lib_name = apertif_bf_xc
hdl_library_clause_name = apertif_bf_xc_lib
hdl_lib_uses_synth =
hdl_lib_uses_sim = apertif_unb1_correlator apertif_fn_beamformer
hdl_lib_uses_sim = apertif_unb1_correlator apertif_unb1_fn_beamformer
hdl_lib_technology = ip_stratixiv
modelsim_copy_files =
......
applications/apertif/systems/apertif_bg_xc/hdllib.cfg
+ 3
− 1
View file @ bdc2bd37
hdl_lib_name = apertif_bg_xc
hdl_library_clause_name = apertif_bg_xc_lib
hdl_lib_uses_synth =
hdl_lib_uses_sim = apertif_unb1_correlator apertif_fn_bf_emu
hdl_lib_uses_sim = apertif_unb1_correlator apertif_unb1_fn_bf_emu
hdl_lib_technology = ip_stratixiv
modelsim_copy_files =
../../designs/apertif_unb1_fn_bf_emu/src/hex/ hex/
$UNB/Firmware/dsp/filter/build/data/ mif
synth_files =
......
applications/apertif/systems/apertif_bg_xc/tb/vhdl/tb_apertif_bg_xc.vhd
+ 56
− 98
View file @ bdc2bd37
-------------------------------------------------------------------------------
--
-- Copyright (C) 2014
-- Copyright (C) 2015
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
......@@ -28,150 +28,108 @@
-- . 2) Instantiate 3x fn_beamformer
-- Usage:
LIBRARY ip_stratixiv_ddr3_mem_model_lib;
LIBRARY IEEE, common_lib, unb1_board_lib, i2c_lib, tech_ddr_lib;
LIBRARY IEEE, common_lib, unb1_board_lib, apertif_unb1_fn_bf_emu_lib, apertif_unb1_correlator_lib;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE common_lib.common_pkg.ALL;
USE unb1_board_lib.unb1_board_pkg.ALL;
USE common_lib.tb_common_pkg.ALL;
USE tech_ddr_lib.tech_ddr_pkg.ALL;
ENTITY tb_apertif_bf_xc IS
END tb_apertif_bf_xc;
ENTITY tb_apertif_bg_xc IS
END tb_apertif_bg_xc;
ARCHITECTURE tb OF tb_apertif_bf_xc IS
ARCHITECTURE tb OF tb_apertif_bg_xc IS
CONSTANT c_sim : BOOLEAN := TRUE;
CONSTANT c_unb_nr : NATURAL := 0; -- UniBoard 0
CONSTANT c_node_nr : NATURAL := 7; -- Back node 3
CONSTANT c_id : STD_LOGIC_VECTOR(7 DOWNTO 0) := TO_UVEC(c_unb_nr, c_unb1_board_nof_uniboard_w) & TO_UVEC(c_node_nr, c_unb1_board_nof_chip_w);
CONSTANT c_unb_nr : NATURAL := 0;
CONSTANT c_node_nr : NATURAL := 0;
CONSTANT c_id : STD_LOGIC_VECTOR(7 DOWNTO 0) := TO_UVEC(c_unb_nr, 5) & TO_UVEC(c_node_nr, 3);
CONSTANT c_version : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
CONSTANT c_fw_version : t_unb1_board_fw_version := (1, 0);
CONSTANT c_cable_delay : TIME := 12 ns;
CONSTANT c_eth_clk_period : TIME := 40 ns; -- 25 MHz XO on UniBoard
CONSTANT c_sa_clk_period : TIME := 6.4 ns;
CONSTANT c_tr_clk_period : TIME := 6.4 ns;
CONSTANT c_clk_period : TIME := 5 ns;
CONSTANT c_pps_period : NATURAL := 1000;
CONSTANT c_ddr : t_c_tech_ddr := c_tech_ddr3_4g_800m_master;
-- DUT
SIGNAL clk : STD_LOGIC := '0';
SIGNAL pps : STD_LOGIC := '0';
SIGNAL pps_rst : STD_LOGIC := '0';
SIGNAL sa_clk : STD_LOGIC := '1';
SIGNAL sb_clk : STD_LOGIC := '1';
SIGNAL WDI : STD_LOGIC;
SIGNAL INTA : STD_LOGIC;
SIGNAL INTB : STD_LOGIC;
SIGNAL tr_clk : STD_LOGIC := '1';
SIGNAL eth_clk : STD_LOGIC := '0';
SIGNAL eth_txp : STD_LOGIC;
SIGNAL eth_rxp : STD_LOGIC;
SIGNAL VERSION : STD_LOGIC_VECTOR(c_unb1_board_aux.version_w-1 DOWNTO 0) := c_version;
SIGNAL ID : STD_LOGIC_VECTOR(c_unb1_board_aux.id_w-1 DOWNTO 0) := c_id;
SIGNAL TESTIO : STD_LOGIC_VECTOR(c_unb1_board_aux.testio_w-1 DOWNTO 0);
SIGNAL sens_scl : STD_LOGIC;
SIGNAL sens_sda : STD_LOGIC;
SIGNAL si_fn_0_tx : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL fn_bn_0_tx : STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0) := (OTHERS => '0');
-- Signals to interface with the DDR3 memory model.
SIGNAL phy_in : t_tech_ddr3_phy_in;
SIGNAL phy_io : t_tech_ddr3_phy_io;
SIGNAL phy_ou : t_tech_ddr3_phy_ou;
BEGIN
----------------------------------------------------------------------------
-- System setup
-- Clocks and PPS
----------------------------------------------------------------------------
clk <= NOT clk AFTER c_clk_period/2; -- External clock (200 MHz)
eth_clk <= NOT eth_clk AFTER c_eth_clk_period/2; -- Ethernet ref clock (25 MHz)
sa_clk <= NOT sa_clk AFTER c_sa_clk_period/2;
sb_clk <= NOT sb_clk AFTER c_sa_clk_period/2;
INTA <= 'H'; -- pull up
INTB <= 'H'; -- pull up
sens_scl <= 'H'; -- pull up
sens_sda <= 'H'; -- pull up
------------------------------------------------------------------------------
-- External PPS
------------------------------------------------------------------------------
clk <= NOT clk AFTER c_clk_period/2;
eth_clk <= NOT eth_clk AFTER c_eth_clk_period/2;
tr_clk <= NOT tr_clk AFTER c_tr_clk_period/2;
proc_common_gen_pulse(1, c_pps_period, '1', pps_rst, clk, pps);
------------------------------------------------------------------------------
-- DUT
-- 3x apertif_unb1_fn_bf_emu
------------------------------------------------------------------------------
u_apertif_unb1_fn_beamformer : ENTITY work.apertif_unb1_fn_beamformer_tp_bg
u_apertif_unb1_fn_bf_emu : ENTITY apertif_unb1_fn_bf_emu_lib.apertif_unb1_fn_bf_emu
GENERIC MAP (
g_sim => c_sim,
g_sim_unb_nr => c_unb_nr,
g_sim_node_nr => c_node_nr
)
PORT MAP (
-- GENERAL
CLK => clk,
PPS => pps,
WDI => WDI,
INTA => INTA,
INTB => INTB,
sens_sc => sens_scl,
sens_sd => sens_sda,
-- Others
VERSION => VERSION,
VERSION => "00",
ID => ID,
TESTIO => TESTIO,
-- 1GbE Control Interface
ETH_clk => eth_clk,
ETH_SGIN => eth_rxp,
ETH_SGOUT => eth_txp,
-- Transceiver clocks
SA_CLK => sa_clk, -- : IN STD_LOGIC; -- SerDes Clock BN-BI / SI_FN
SB_CLK => sb_clk,
-- Mesh Serial I/O
FN_BN_0_RX => fn_bn_0_tx, -- : IN STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
FN_BN_1_RX => fn_bn_0_tx, -- : IN STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
FN_BN_2_RX => fn_bn_0_tx, -- : IN STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
FN_BN_3_RX => fn_bn_0_tx, -- : IN STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
-- Serial I/O
SI_FN_0_RX => si_fn_0_tx, -- : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
SI_FN_1_RX => si_fn_0_tx, -- : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
SI_FN_2_RX => si_fn_0_tx, -- : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
SI_FN_3_RX => si_fn_0_tx, -- : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
MB_I_in => phy_in,
MB_I_io => phy_io,
MB_I_ou => phy_ou
ETH_SGIN => '0',
SA_CLK => tr_clk,
SI_FN_0_RX => (OTHERS=>'0'),
SI_FN_1_RX => (OTHERS=>'0'),
SI_FN_2_RX => (OTHERS=>'0'),
SI_FN_3_RX => (OTHERS=>'0'),
SI_FN_0_TX => si_fn_0_tx
);
------------------------------------------------------------------------------
-- DDR3 memory model
-- apertif_unb1_correlator
------------------------------------------------------------------------------
u_tech_ddr_memory_model : ENTITY tech_ddr_lib.tech_ddr_memory_model
u_apertif_unb1_correlator : ENTITY apertif_unb1_correlator_lib.apertif_unb1_correlator
GENERIC MAP (
g_tech_ddr => c_ddr
g_sim => c_sim,
g_sim_unb_nr => c_unb_nr,
g_sim_node_nr => c_node_nr,
g_use_bg => FALSE
)
PORT MAP (
mem3_in => phy_ou,
mem3_io => phy_io,
mem3_ou => phy_in
);
CLK => clk,
PPS => pps,
VERSION => "00",
ID => ID,
ETH_clk => eth_clk,
ETH_SGIN => '0',
SA_CLK => tr_clk,
SB_CLK => tr_clk,
SI_FN_0_RX => si_fn_0_tx,
SI_FN_1_RX => si_fn_0_tx,
SI_FN_2_RX => si_fn_0_tx,
SI_FN_3_RX => (OTHERS=>'0'),
FN_BN_0_RX => (OTHERS=>'0'),
FN_BN_1_RX => (OTHERS=>'0'),
FN_BN_2_RX => (OTHERS=>'0'),
FN_BN_3_RX => (OTHERS=>'0')
);
END tb;
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Please register or to comment