add testing of sync_offset

libraries/base/dp/tb/vhdl/tb_dp_bsn_source_v2.vhd

@@ -36,6 +36,7 @@ USE dp_lib.tb_dp_pkg.ALL;
 
 ENTITY tb_dp_bsn_source_v2 IS
   GENERIC (
+    g_sync_offset  : NATURAL := 0;  -- must be < c_sync_period for proc_dp_verify_sync
     g_clk_per_sync : NATURAL := 240
   );
 END tb_dp_bsn_source_v2;
@@ -47,7 +48,6 @@ ARCHITECTURE tb OF tb_dp_bsn_source_v2 IS
   CONSTANT c_block_size   : NATURAL := 32; -- 31;
   CONSTANT c_bsn_w        : NATURAL := 31; -- 16;
   CONSTANT c_sync_period  : NATURAL := 8;
-  CONSTANT c_sync_offset  : NATURAL := 0; -- 3;  -- must be < c_sync_period for proc_dp_verify_sync
 
   -- The state name tells what kind of test is being done
   TYPE t_state_enum IS (
@@ -93,7 +93,7 @@ BEGIN
 
     dp_on   <= '0';
     dp_on_pps  <= '0';
-    init_bsn <= TO_UVEC(c_sync_offset, c_bsn_w);
+    init_bsn <= TO_UVEC(g_sync_offset, c_bsn_w);
 
     -- Get synchronous to clk
     proc_common_wait_until_low(clk, rst);
@@ -137,7 +137,7 @@ BEGIN
     proc_common_wait_some_cycles(clk, 1000);
 
     -- Now start on next PPS and continue forever
-    init_bsn <= TO_UVEC(c_sync_offset, c_bsn_w);
+    init_bsn <= TO_UVEC(g_sync_offset, c_bsn_w);
     tb_state <= s_pps_start;
     dp_on_pps <= '1';
     dp_on     <= '1';
@@ -157,7 +157,7 @@ BEGIN
   -- Verification
   -----------------------------------------------------------------------------
   proc_dp_verify_sop_and_eop(clk, bs_sosi.valid, bs_sosi.sop, bs_sosi.eop, hold_bs_sop);                        -- Verify that sop and eop come in pairs
-  proc_dp_verify_sync_v2(c_sync_period, c_sync_offset, clk, verify_sync, bs_sosi.sync, bs_sosi.sop, bs_sosi.bsn, tb_bsn_cnt);  -- Verify sync at sop and at expected BSN
+  proc_dp_verify_sync_v2(c_sync_period, g_sync_offset, clk, verify_sync, bs_sosi.sync, bs_sosi.sop, bs_sosi.bsn, tb_bsn_cnt);  -- Verify sync at sop and at expected BSN
 
   -----------------------------------------------------------------------------
   -- DUT: dp_bsn_source_v2

libraries/base/dp/tb/vhdl/tb_dp_pkg.vhd

@@ -2277,7 +2277,7 @@ PACKAGE BODY tb_dp_pkg IS
         END IF;
 
         -- if bsn = 0 (when in dp_off state) set tb_bsn_cnt also to 0
-        IF TO_UINT(bsn(c_bsn_w-1 DOWNTO 0)) = 0 THEN
+        IF TO_UINT(bsn(c_bsn_w-1 DOWNTO 0)) = c_sync_offset THEN
           v_tb_bsn_cnt := 0;
         END IF;
 

libraries/base/dp/tb/vhdl/tb_tb_dp_bsn_source_v2.vhd

@@ -36,10 +36,16 @@ ARCHITECTURE tb OF tb_tb_dp_bsn_source_v2 IS
   SIGNAL tb_end : STD_LOGIC := '0';  -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
 BEGIN
 
-  --                                                   (clk_per_sync)
-  u0_230 : ENTITY work.tb_dp_bsn_source_v2 GENERIC MAP (230);
-  u0_240 : ENTITY work.tb_dp_bsn_source_v2 GENERIC MAP (240);
-  u0_248 : ENTITY work.tb_dp_bsn_source_v2 GENERIC MAP (248);
+  --                                         (sync_offset, clk_per_sync)
+  -- test different clk_per_sync
+  u0_230 : ENTITY work.tb_dp_bsn_source_v2 GENERIC MAP (0, 230);
+  u0_240 : ENTITY work.tb_dp_bsn_source_v2 GENERIC MAP (0, 240);
+  u0_248 : ENTITY work.tb_dp_bsn_source_v2 GENERIC MAP (0, 248);
+
+  -- test different sync_offsets
+  u1_1 : ENTITY work.tb_dp_bsn_source_v2 GENERIC MAP (1, 248);
+  u1_3 : ENTITY work.tb_dp_bsn_source_v2 GENERIC MAP (3, 248);
+  u1_4 : ENTITY work.tb_dp_bsn_source_v2 GENERIC MAP (4, 248);
   
 END tb;
   
\ No newline at end of file