Use mm_sosi or out_sosi_arr(0) from BSN aligner for output BSN monitor,...

Use mm_sosi or out_sosi_arr(0) from BSN aligner for output BSN monitor, dependent on g_use_mm_output.

libraries/base/dp/src/vhdl/mmp_dp_bsn_align_v2.vhd

@@ -52,7 +52,8 @@ ENTITY mmp_dp_bsn_align_v2 IS
     g_data_w                     : NATURAL;           -- number of bits in sosi data
     g_data_replacement_value     : INTEGER := 0;      -- output sosi data value for missing input blocks
     g_use_mm_output              : BOOLEAN := FALSE;  -- output via MM or via streaming DP
-    g_pipeline_input             : NATURAL := 1;      -- >= 0, choose 0 for wires, choose 1 to ease timing closure
+    g_pipeline_input             : NATURAL := 1;      -- >= 0, choose 0 for wires, choose 1 to ease timing closure of in_sosi_arr
+    g_pipeline_output            : NATURAL := 1;      -- >= 0, choose 0 for wires, choose 1 to ease timing closure of out_sosi_arr
     g_rd_latency                 : NATURAL := 2;      -- 1 or 2, choose 2 to ease timing closure
     -- for mms_dp_bsn_monitor_v2
     g_nof_clk_per_sync           : NATURAL := 200*10**6;
@@ -103,15 +104,19 @@ ARCHITECTURE str OF mmp_dp_bsn_align_v2 IS
   --   dat_w     : NATURAL;
   --   nof_dat   : NATURAL;    -- optional, nof dat words <= 2**adr_w
   --   init_sl   : STD_LOGIC;  -- optional, init all dat words to std_logic '0', '1' or 'X'
-  CONSTANT c_mm_reg     : t_c_mem := (1, ceil_log2(g_nof_streams), 1, g_nof_streams, '0');
+  CONSTANT c_mm_reg       : t_c_mem := (1, ceil_log2(g_nof_streams), 1, g_nof_streams, '0');
 
-  SIGNAL reg_wr         : STD_LOGIC_VECTOR(c_mm_reg.nof_dat*c_mm_reg.dat_w-1 DOWNTO 0);
-  SIGNAL stream_en_arr  : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
+  SIGNAL reg_wr           : STD_LOGIC_VECTOR(c_mm_reg.nof_dat*c_mm_reg.dat_w-1 DOWNTO 0);
+  SIGNAL stream_en_arr    : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
 
-  SIGNAL mm_sosi_arr    : t_dp_sosi_arr(0 DOWNTO 0);
+  SIGNAL ref_sync         : STD_LOGIC;
+  SIGNAL mon_out_sosi_arr : t_dp_sosi_arr(0 DOWNTO 0);
+  SIGNAL i_out_sosi_arr   : t_dp_sosi_arr(g_nof_streams-1  DOWNTO 0);
+  SIGNAL i_mm_sosi        : t_dp_sosi;
 
 BEGIN
 
+  -- MM control of BSN aligner
   u_reg : ENTITY common_lib.common_reg_r_w_dc
   GENERIC MAP (
     g_cross_clock_domain   => TRUE,
@@ -138,6 +143,9 @@ BEGIN
 
   stream_en_arr <= reg_wr;
 
+  -- Use local sync as reference sync input for the BSN monitors
+  ref_sync <= in_sosi_arr(0).sync;
+
   -- Use input BSN monitors for the first g_nof_input_bsn_monitors input
   -- streams, e.g. to support:
   -- . only one input stream (g_nof_input_bsn_monitors = 1), or
@@ -164,9 +172,8 @@ BEGIN
       -- Streaming clock domain
       dp_rst         => dp_rst,
       dp_clk         => dp_clk,
-      ref_sync       => in_sosi_arr(0).sync,  -- local reference sync input
+      ref_sync       => ref_sync,
 
-      in_siso_arr    => (OTHERS=>c_dp_siso_rdy),
       in_sosi_arr    => in_sosi_arr(g_nof_input_bsn_monitors-1 DOWNTO 0)
     );
   END GENERATE;
@@ -193,13 +200,19 @@ BEGIN
       -- Streaming clock domain
       dp_rst         => dp_rst,
       dp_clk         => dp_clk,
-      ref_sync       => in_sosi_arr(0).sync,  -- local reference sync input
+      ref_sync       => ref_sync,
 
-      in_siso_arr    => (OTHERS=>c_dp_siso_rdy),
-      in_sosi_arr    => mm_sosi_arr
+      in_sosi_arr    => mon_out_sosi_arr
     );
   END GENERATE;
 
+  -- Use mm_sosi or out_sosi_arr(0) from BSN aligner for output BSN monitor
+  mon_out_sosi_arr(0) <= i_mm_sosi WHEN g_use_mm_output = TRUE ELSE i_out_sosi_arr(0);
+
+  -- wire to output
+  mm_sosi <= i_mm_sosi;
+  out_sosi_arr <= i_out_sosi_arr;
+
   u_bsn_align : ENTITY work.dp_bsn_align_v2
   GENERIC MAP (
     g_nof_streams                => g_nof_streams,
@@ -211,6 +224,7 @@ BEGIN
     g_data_replacement_value     => g_data_replacement_value,
     g_use_mm_output              => g_use_mm_output,
     g_pipeline_input             => g_pipeline_input,
+    g_pipeline_output            => g_pipeline_output,
     g_rd_latency                 => g_rd_latency
   )
   PORT MAP (
@@ -222,14 +236,12 @@ BEGIN
     -- Streaming input
     in_sosi_arr    => in_sosi_arr,
     -- Output via local MM in dp_clk domain
-    mm_sosi        => mm_sosi,
+    mm_sosi        => i_mm_sosi,
     mm_copi        => mm_copi,
     mm_cipo_arr    => mm_cipo_arr,
     -- Output via streaming DP interface, when g_use_mm_output = TRUE.
-    out_sosi_arr   => out_sosi_arr
+    out_sosi_arr   => i_out_sosi_arr
   );
 
-  mm_sosi <= mm_sosi_arr(0);
-
 END str;