Changed assignment for ETH_CLK from GLOBAL_CLOCK to OFF to enable

compilation with quartus version > 18.0

applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/flat.qsf

@@ -55,14 +55,12 @@ set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS OFF
 #set_instance_assignment -name GLOBAL_SIGNAL GLOBAL_CLOCK -to board_inst|config_clk~pad
 #set_instance_assignment -name GLOBAL_SIGNAL GLOBAL_CLOCK -to board_inst|clk_clk~pad
 #set_instance_assignment -name GLOBAL_SIGNAL GLOBAL_CLOCK -to board_inst|pll_ref_clk~pad
-set_instance_assignment -name GLOBAL_SIGNAL GLOBAL_CLOCK -to board_inst|kernel_clk_gen|board_kernel_clk_gen|kernel_pll|altera_iopll_i|twentynm_pll|outclk[0]
-set_instance_assignment -name GLOBAL_SIGNAL GLOBAL_CLOCK -to board_inst|kernel_clk_gen|board_kernel_clk_gen|kernel_pll|altera_iopll_i|twentynm_pll|outclk[1]
+set_instance_assignment -name GLOBAL_SIGNAL GLOBAL_CLOCK -to board_inst|kernel_clk_gen|board_kernel_clk_gen|kernel_pll|altera_iopll_i|twentynm_pll|*
 set_instance_assignment -name GLOBAL_SIGNAL GLOBAL_CLOCK -to *ALTERA_INSERTED_OSCILLATOR_FOR_IOPLL*
 
-set_instance_assignment -name GLOBAL_SIGNAL GLOBAL_CLOCK -to u_ctrl_unb2_board|\gen_eth:u_eth|u_tech_tse|\gen_ip_arria10_e1sg:u0|\u_LVDS_tse:u_tse|eth_tse_0|i_lvdsio_rx_0|core|arch_inst|internal_pll.pll_inst|outclock[2] 
-set_instance_assignment -name GLOBAL_SIGNAL GLOBAL_CLOCK -to u_ctrl_unb2_board|\gen_mm_clk_hardware:u_unb2_board_clk125_pll|\gen_fractional_pll:u_pll|\gen_ip_arria10_e1sg:u0|xcvr_fpll_a10_0|outclk0 
-set_instance_assignment -name GLOBAL_SIGNAL GLOBAL_CLOCK -to u_ctrl_unb2_board|\gen_mm_clk_hardware:u_unb2_board_clk125_pll|\gen_fractional_pll:u_pll|\gen_ip_arria10_e1sg:u0|xcvr_fpll_a10_0|outclk1 
-set_instance_assignment -name GLOBAL_SIGNAL GLOBAL_CLOCK -to u_ctrl_unb2_board|\gen_pll:u_unb2_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10_e1sg:u0|xcvr_fpll_a10_0|outclk0 
+#set_instance_assignment -name GLOBAL_SIGNAL GLOBAL_CLOCK -to u_ctrl_unb2b_board|\gen_eth:u_eth|u_tech_tse|\gen_ip_arria10_e1sg:u0|\u_LVDS_tse:u_tse|eth_tse_0|i_lvdsio_rx_0|core|arch_inst|internal_pll.pll_inst|outclock[2] 
+set_instance_assignment -name GLOBAL_SIGNAL GLOBAL_CLOCK -to u_ctrl_unb2b_board|\gen_mm_clk_hardware:u_unb2_board_clk125_pll|\gen_fractional_pll:u_pll|\gen_ip_arria10_e1sg:u0|xcvr_fpll_a10_0|* 
+set_instance_assignment -name GLOBAL_SIGNAL GLOBAL_CLOCK -to u_ctrl_unb2b_board|\gen_pll:u_unb2_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10_e1sg:u0|xcvr_fpll_a10_0|* 
 
 
 # Resets
@@ -138,7 +136,7 @@ set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to PPS
 
 # IO Standard Assignments from Gijs (excluding memory)
 set_instance_assignment -name IO_STANDARD "1.8 V" -to ETH_CLK
-set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to ETH_CLK
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to ETH_CLK
 set_instance_assignment -name IO_STANDARD LVDS -to ETH_SGIN[0]
 set_instance_assignment -name IO_STANDARD LVDS -to "ETH_SGIN[0](n)"
 set_instance_assignment -name IO_STANDARD LVDS -to ETH_SGIN[1]