update

boards/uniboard2a/designs/unb2a_test/doc/README.txt

@@ -94,11 +94,40 @@ LCU computer. See the README file in the ../revisions/* directories for examples
 
 
 6.
+(a)
 Programming the EPCS flash.
 when the EPCS module works an RBF file can be generated to program the flash,
 then the .sof file file can be converted to .rbf with the 'run_rbf' script.
+For generating a User image .RBF file:
+
+    run_rbf unb2a unb2a_test_[revision]
+
+For generating a Factory image .RBF file:
+
+    run_rbf unb2a --unb2_factory unb2a_test_[revision]
+
+The .RBF file is now in $RADIOHDL/build/unb2a/quartus/unb2a_test_[revision]
+Now copy the .RBF file to the LCU host with 'scp'
+
+(b)
+Then to program the FPGA(s) via the LCU host, use the python script.
+
+Program User image:
+    python util_epcs.py --unb 1 --fn 0 -n 7 -s unb2a_test_[revision].rbf
+Program Factory image:
+    python util_epcs.py --unb 1 --fn 0 -n 3 -s unb2a_test_[revision].rbf
+
+-> For extra info on RBF files on Uniboard2, see: $RADIOHDL/libraries/io/epcs/doc/README.txt
+
+To start the User image:
+    python util_remu.py --unb 1 --fn 0 -n 6  # ignore timeout error
+To start the Factory image:
+    python util_remu.py --unb 1 --fn 0 -n 5  # ignore timeout error
+
+
+
+An alternative method to write the flash is via a .JIC file and JTAG:
 
-But for now the only way to program the EPCS flash is via JTAG.
 Firstly a JIC file has to be generated from the SOF file.
 In Quartus GUI; open current project; File -> Convert Programming Files.
 Then setup:
@@ -115,9 +144,26 @@ Then program the .JIC file (output_file.jic) to EPCS flash:
 - open tools->programmer
 - make sure the 4 fpga icons have the device 10AX115U4F45ES
 - right-click each fpga icon and attach flash device EPCQL1024
-- right-click each fpga and change file from <none> to sfl_enhanced_01_02e360dd.sof
-  (in $RADIOHDL/boards/uniboard2/libraries/unb2_board/quartus)
+- optional see (*1)
 - right-click each EPCQL1024 and change file from <none> to output_file.jic
 - select click each Program/Configure radiobutton
 - click start and wait for 'Successful'
 
+(*1) When error select correct SFL (serial flash loader) from Altera service request for each FPGA:
+     right-click each fpga and change file from <none> to sfl_enhanced_01_02e360dd.sof
+     (in $RADIOHDL/boards/uniboard2/libraries/unb2a_board/quartus)
+
+
+7.
+Optionally you can readout the messages the NIOS application "unb_osy" prints over the JTAG interface.
+First make sure that the JTAG cable is set to a correct speed. Use the command:
+
+  jtagconfig --setparam "USB-BlasterII [USB-1]" JtagClock 8M
+
+Then use this command to read from the JTAG terminal:
+
+  cd /home/software/Altera/15.1/quartus
+  ./bin/nios2-terminal --cable 1 --device=1
+
+Where device is 1..4, selecting 1 of the 4 FPGAs
+