Added g_technology for tech_xaui.

libraries/io/tr_xaui/src/vhdl/tr_xaui.vhd

@@ -20,7 +20,7 @@
 --
 --------------------------------------------------------------------------------
 
-LIBRARY IEEE, common_lib, dp_lib, mdio_lib;
+LIBRARY IEEE, common_lib, dp_lib, mdio_lib, technology_lib, tech_xaui_lib;
 USE IEEE.STD_LOGIC_1164.ALL;
 USE common_lib.common_pkg.ALL;
 USE common_lib.common_mem_pkg.ALL;
@@ -28,9 +28,11 @@ USE common_lib.common_interface_layers_pkg.ALL;
 USE dp_lib.dp_stream_pkg.ALL;
 USE mdio_lib.mdio_pkg.ALL;
 USE mdio_lib.mdio_vitesse_vsc8486_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
 
 ENTITY tr_xaui IS
   GENERIC (
+    g_technology            : NATURAL := c_tech_select_default;
     g_sim                   : BOOLEAN := FALSE;
     g_sim_level             : NATURAL := 0;     -- 0 = use IP; 1 = use fast serdes model
     g_use_xgmii             : BOOLEAN := FALSE; -- Don't use streaming I/O but XGMII (e.g. conenct to 10GbE MAC)
@@ -152,9 +154,10 @@ BEGIN
   -----------------------------------------------------------------------------
   gen_phy: IF g_sim = FALSE OR g_sim_level = 0 GENERATE
     -- Altera's IP
-    u_phy_xaui : ENTITY work.phy_xaui
+    u_tech_xaui : ENTITY tech_xaui_lib.tech_xaui
     GENERIC MAP (
-      g_nof_xaui => g_nof_xaui 
+      g_technology => g_technology,
+      g_nof_xaui   => g_nof_xaui 
     )
     PORT MAP (
       tr_clk               => tr_clk,