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Commit bcac0e39 authored by Daniel van der Schuur's avatar Daniel van der Schuur
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-Instantiated beamlet_lookup and added corresponding dp_pipeline and logic.

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applications/apertif/designs/apertif_unb1_correlator/src/vhdl/apertif_unb1_correlator_vis_offload.vhd
+ 80
− 43
View file @ bcac0e39
......@@ -58,7 +58,7 @@ ENTITY apertif_unb1_correlator_vis_offload IS
END apertif_unb1_correlator_vis_offload;
ARCHITECTURE wrap OF apertif_unb1_correlator_vis_offload IS
ARCHITECTURE str OF apertif_unb1_correlator_vis_offload IS
-- Word align + Eth + IP + UDP + ID + Flags
CONSTANT c_nof_hdr_fields : NATURAL := 1 + 3 + 12 + 4 + 6 + 8 ; -- 34 fields
......@@ -118,23 +118,45 @@ ARCHITECTURE wrap OF apertif_unb1_correlator_vis_offload IS
SIGNAL id_backplane : STD_LOGIC_VECTOR(c_byte_w-1 DOWNTO 0);
SIGNAL id_chip : STD_LOGIC_VECTOR(c_byte_w-1 DOWNTO 0);
SIGNAL dp_pipeline_src_out : t_dp_sosi;
SIGNAL dp_pipeline_src_in : t_dp_siso;
SIGNAL beamlet_index : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL reordered_beamlet_index : STD_LOGIC_VECTOR( 9 DOWNTO 0);
SIGNAL channel_index : STD_LOGIC_VECTOR(15 DOWNTO 0);
BEGIN
---------------------------------------------------------------------------------------
-- Register snk_in, needed to align data with beamlet_reorder output
---------------------------------------------------------------------------------------
u_dp_pipeline : ENTITY dp_lib.dp_pipeline
PORT MAP (
clk => dp_clk,
rst => dp_rst,
snk_in => snk_in,
snk_out => snk_out,
src_out => dp_pipeline_src_out,
src_in => dp_pipeline_src_in
);
---------------------------------------------------------------------------------------
-- Swap the bytes in the 32b words to make them little-endian to fit the Intel format of the Data Writer
---------------------------------------------------------------------------------------
p_connect : PROCESS(snk_in)
p_connect : PROCESS(dp_pipeline_src_out)
BEGIN
-- Control
dp_offload_tx_snk_in_arr(0) <= snk_in;
dp_offload_tx_snk_in_arr(0) <= dp_pipeline_src_out;
-- Data: re&im concatenated so real part is put on the line first: re,im,re,im, ..
dp_offload_tx_snk_in_arr(0).data <= ntoh(snk_in.data, c_word_sz); -- perform endian byte swap on lowest c_word_sz = 4 bytes in snk_in.data
dp_offload_tx_snk_in_arr(0).data <= ntoh(dp_pipeline_src_out.data, c_word_sz); -- perform endian byte swap on lowest c_word_sz = 4 bytes in dp_pipeline_src_out.data
END PROCESS;
---------------------------------------------------------------------------------------
-- dp_offload_tx
---------------------------------------------------------------------------------------
snk_out <= dp_offload_tx_snk_out_arr(0);
dp_pipeline_src_in <= dp_offload_tx_snk_out_arr(0);
u_dp_concat_field_blk : ENTITY dp_lib.dp_concat_field_blk
GENERIC MAP (
......@@ -173,42 +195,57 @@ BEGIN
id_chip <= RESIZE_UVEC(ID(2 DOWNTO 0), c_byte_w);
---------------------------------------------------------------------------------------
-- Assign DP record fields and ID to header fields
-- Create Beamlet and Channel indices
---------------------------------------------------------------------------------------
-- Beamlet index: The processing node outputs indices ranging from 0..127. Here, we convert this to a 'global' beamlet index 0..16383.
-- . Backplane ID at MS portion achieves a 1024 beamlet increment per board;
-- . Chip ID[0] at bit 0 achieves the odd,even beamlets between nodes.
-- . Chip ID[2..1] at bits 9..8 achieves the +256 beamlet every two nodes.
-- . The beamlet count 0..127 (carried in the channel field) at bits 7..1 achieves the 128 beamlet index range with s step size of 2.
-- unb 0, FN 0 : 0,2,4,6,8
-- unb 0, FN 1 : 1,3,5,7,9
-- unb 0, FN 2 : 256,258,260
-- unb 0, FN 3 : 257,259,261
-- unb 0, BN 0 : 512,514,516
-- unb 0, BN 1 : 513,515,517
-- unb 0, BN 2 : 768,770,772
-- unb 0, BN 3 : 769,771,773
-- ..
-- unb 1, FN0 : 1024,1026,1028
-- ..
-- unb 15, FN 0 : 16384,16386,16388
-- unb 15, BN 3 : 17153,17155,17157
beamlet_index <= "00" & id_backplane(3 DOWNTO 0) & id_chip(2 DOWNTO 1) & snk_in.channel(12 DOWNTO 6) & id_chip(0);
-- channel index: We're connecting the CHANNEL FIELD IN REVERSE (using flip())to compensate for the FFT not reordering its output channels.
-- . snk_in.channel indices: [0,1,2,3,4, ..63]
-- . FFT output channels = reversed snk_in.channel indices: [ 0, 32, 16, 48, 8, 40, 24, 56, 4, .. ]
-- In addition to flipping the channel indices, we're inverting the MSbit (5) to achieve the required FFT shift.
-- . FFT output channels = reversed snk_in.channel indices: [32, 0, 48, 16, 40, 8, 56, 24, 36, .. ]
channel_index <= "0000000000" & NOT(flip(dp_pipeline_src_out.channel(5 DOWNTO 0))(5)) & flip(dp_pipeline_src_out.channel(5 DOWNTO 0))(4 DOWNTO 0); -- Use the registered snk_in to align with beamlet_lookup output.
---------------------------------------------------------------------------------------
-- Reorder the beamlet index from ARTS -> Imaging
-- . We're reordering only the 10 LS bits of beamlet_index.
-- . The MS 6 bits don't need to be reordered and are static so we'll re-attach them
-- later below.
---------------------------------------------------------------------------------------
u_beamlet_lookup : ENTITY work.beamlet_lookup
PORT MAP (
clk => dp_clk,
beamlet_in => beamlet_index(9 DOWNTO 0),
beamlet_out => reordered_beamlet_index
);
---------------------------------------------------------------------------------------
-- Assign DP record fields and IDs to header fields
---------------------------------------------------------------------------------------
gen_slv_hard_fields : FOR i IN 0 TO c_nof_offload_streams-1 GENERATE
hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "eth_src_mac" ) DOWNTO field_lo(c_hdr_field_arr, "eth_src_mac" )) <= x"00228608" & id_backplane & id_chip;
hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "udp_src_port" ) DOWNTO field_lo(c_hdr_field_arr, "udp_src_port" )) <= x"D0" & ID;
hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "udp_dst_port" ) DOWNTO field_lo(c_hdr_field_arr, "udp_dst_port" )) <= x"D0" & ID;
hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "ip_src_addr" ) DOWNTO field_lo(c_hdr_field_arr, "ip_src_addr" )) <= x"0A63" & id_backplane & INCR_UVEC(id_chip, 1);
-- Beamlet index: The processing node outputs indices ranging from 0..127. Here, we convert this to a 'global' beamlet index 0..16383.
-- . Backplane ID at MS portion achieves a 1024 beamlet increment per board;
-- . Chip ID[0] at bit 0 achieves the odd,even beamlets between nodes.
-- . Chip ID[2..1] at bits 9..8 achieves the +256 beamlet every two nodes.
-- . The beamlet count 0..127 (carried in the channel field) at bits 7..1 achieves the 128 beamlet index range with s step size of 2.
-- unb 0, FN 0 : 0,2,4,6,8
-- unb 0, FN 1 : 1,3,5,7,9
-- unb 0, FN 2 : 256,258,260
-- unb 0, FN 3 : 257,259,261
-- unb 0, BN 0 : 512,514,516
-- unb 0, BN 1 : 513,515,517
-- unb 0, BN 2 : 768,770,772
-- unb 0, BN 3 : 769,771,773
-- ..
-- unb 1, FN0 : 1024,1026,1028
-- ..
-- unb 15, FN 0 : 16384,16386,16388
-- unb 15, BN 3 : 17153,17155,17157
hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "id_beamlet_index" ) DOWNTO field_lo(c_hdr_field_arr, "id_beamlet_index" )) <= "00" & id_backplane(3 DOWNTO 0) & id_chip(2 DOWNTO 1) & snk_in.channel(12 DOWNTO 6) & id_chip(0);
-- channel index: We're connecting the CHANNEL FIELD IN REVERSE (using flip())to compensate for the FFT not reordering its output channels.
-- . snk_in.channel indices: [0,1,2,3,4, ..63]
-- . FFT output channels = reversed snk_in.channel indices: [ 0, 32, 16, 48, 8, 40, 24, 56, 4, .. ]
-- In addition to flipping the channel indices, we're inverting the MSbit (5) to achieve the required FFT shift.
-- . FFT output channels = reversed snk_in.channel indices: [32, 0, 48, 16, 40, 8, 56, 24, 36, .. ]
hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "id_channel_index" ) DOWNTO field_lo(c_hdr_field_arr, "id_channel_index" )) <= "0000000000" & NOT(flip(snk_in.channel(5 DOWNTO 0))(5)) & flip(snk_in.channel(5 DOWNTO 0))(4 DOWNTO 0);
hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "id_timestamp" ) DOWNTO field_lo(c_hdr_field_arr, "id_timestamp" )) <= snk_in.bsn;
END GENERATE;
END wrap;
hdr_fields_in_arr(0)(field_hi(c_hdr_field_arr, "eth_src_mac" ) DOWNTO field_lo(c_hdr_field_arr, "eth_src_mac" )) <= x"00228608" & id_backplane & id_chip;
hdr_fields_in_arr(0)(field_hi(c_hdr_field_arr, "udp_src_port" ) DOWNTO field_lo(c_hdr_field_arr, "udp_src_port" )) <= x"D0" & ID;
hdr_fields_in_arr(0)(field_hi(c_hdr_field_arr, "udp_dst_port" ) DOWNTO field_lo(c_hdr_field_arr, "udp_dst_port" )) <= x"D0" & ID;
hdr_fields_in_arr(0)(field_hi(c_hdr_field_arr, "ip_src_addr" ) DOWNTO field_lo(c_hdr_field_arr, "ip_src_addr" )) <= x"0A63" & id_backplane & INCR_UVEC(id_chip, 1);
hdr_fields_in_arr(0)(field_hi(c_hdr_field_arr, "id_beamlet_index" ) DOWNTO field_lo(c_hdr_field_arr, "id_beamlet_index" )) <= beamlet_index(15 DOWNTO 10) & reordered_beamlet_index;
hdr_fields_in_arr(0)(field_hi(c_hdr_field_arr, "id_channel_index" ) DOWNTO field_lo(c_hdr_field_arr, "id_channel_index" )) <= channel_index;
hdr_fields_in_arr(0)(field_hi(c_hdr_field_arr, "id_timestamp" ) DOWNTO field_lo(c_hdr_field_arr, "id_timestamp" )) <= dp_pipeline_src_out.bsn; -- Use the registered snk_in to align with beamlet_lookup output.
END str;
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