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Commit bc1f2e13 authored by Eric Kooistra's avatar Eric Kooistra
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Added tse_sgmii_lvds with Qsys 14.0a10 with same settings as for in IP used in... 

Added tse_sgmii_lvds with Qsys 14.0a10 with same settings as for in IP used in /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk for UniBoard1 with Megawizard in Quartus v9.1.
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libraries/technology/ip_arria10/tse_sgmii_lvds/ip_arria10_tse_sgmii_lvds.qsys 0 → 100644
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<?xml version="1.0" encoding="UTF-8"?>
<system name="$${FILENAME}">
<component
name="$${FILENAME}"
displayName="$${FILENAME}"
version="1.0"
description=""
tags="INTERNAL_COMPONENT=true"
categories="" />
<parameter name="bonusData"><![CDATA[bonusData
{
element $${FILENAME}
{
}
element eth_tse_0
{
datum _sortIndex
{
value = "0";
type = "int";
}
}
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
<parameter name="device" value="Unknown" />
<parameter name="deviceFamily" value="Arria 10" />
<parameter name="deviceSpeedGrade" value="Unknown" />
<parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" />
<parameter name="globalResetBus" value="false" />
<parameter name="hdlLanguage" value="VERILOG" />
<parameter name="hideFromIPCatalog" value="true" />
<parameter name="maxAdditionalLatency" value="1" />
<parameter name="projectName" value="" />
<parameter name="sopcBorderPoints" value="false" />
<parameter name="systemHash" value="0" />
<parameter name="testBenchDutName" value="" />
<parameter name="timeStamp" value="0" />
<parameter name="useTestBenchNamingPattern" value="false" />
<instanceScript></instanceScript>
<interface
name="control_port_clock_connection"
internal="eth_tse_0.control_port_clock_connection"
type="clock"
dir="end">
<port name="clk" internal="clk" />
</interface>
<interface
name="reset_connection"
internal="eth_tse_0.reset_connection"
type="reset"
dir="end">
<port name="reset" internal="reset" />
</interface>
<interface
name="control_port"
internal="eth_tse_0.control_port"
type="avalon"
dir="end">
<port name="reg_data_out" internal="reg_data_out" />
<port name="reg_rd" internal="reg_rd" />
<port name="reg_data_in" internal="reg_data_in" />
<port name="reg_wr" internal="reg_wr" />
<port name="reg_busy" internal="reg_busy" />
<port name="reg_addr" internal="reg_addr" />
</interface>
<interface
name="pcs_mac_tx_clock_connection"
internal="eth_tse_0.pcs_mac_tx_clock_connection" />
<interface
name="pcs_mac_rx_clock_connection"
internal="eth_tse_0.pcs_mac_rx_clock_connection" />
<interface
name="mac_status_connection"
internal="eth_tse_0.mac_status_connection" />
<interface name="mac_gmii_connection" internal="eth_tse_0.mac_gmii_connection" />
<interface name="mac_mii_connection" internal="eth_tse_0.mac_mii_connection" />
<interface
name="receive_clock_connection"
internal="eth_tse_0.receive_clock_connection"
type="clock"
dir="end">
<port name="ff_rx_clk" internal="ff_rx_clk" />
</interface>
<interface
name="transmit_clock_connection"
internal="eth_tse_0.transmit_clock_connection"
type="clock"
dir="end">
<port name="ff_tx_clk" internal="ff_tx_clk" />
</interface>
<interface
name="receive"
internal="eth_tse_0.receive"
type="avalon_streaming"
dir="start">
<port name="ff_rx_data" internal="ff_rx_data" />
<port name="ff_rx_eop" internal="ff_rx_eop" />
<port name="rx_err" internal="rx_err" />
<port name="ff_rx_mod" internal="ff_rx_mod" />
<port name="ff_rx_rdy" internal="ff_rx_rdy" />
<port name="ff_rx_sop" internal="ff_rx_sop" />
<port name="ff_rx_dval" internal="ff_rx_dval" />
</interface>
<interface
name="transmit"
internal="eth_tse_0.transmit"
type="avalon_streaming"
dir="end">
<port name="ff_tx_data" internal="ff_tx_data" />
<port name="ff_tx_eop" internal="ff_tx_eop" />
<port name="ff_tx_err" internal="ff_tx_err" />
<port name="ff_tx_mod" internal="ff_tx_mod" />
<port name="ff_tx_rdy" internal="ff_tx_rdy" />
<port name="ff_tx_sop" internal="ff_tx_sop" />
<port name="ff_tx_wren" internal="ff_tx_wren" />
</interface>
<interface
name="mac_misc_connection"
internal="eth_tse_0.mac_misc_connection"
type="conduit"
dir="end">
<port name="ff_tx_crc_fwd" internal="ff_tx_crc_fwd" />
<port name="ff_tx_septy" internal="ff_tx_septy" />
<port name="tx_ff_uflow" internal="tx_ff_uflow" />
<port name="ff_tx_a_full" internal="ff_tx_a_full" />
<port name="ff_tx_a_empty" internal="ff_tx_a_empty" />
<port name="rx_err_stat" internal="rx_err_stat" />
<port name="rx_frm_type" internal="rx_frm_type" />
<port name="ff_rx_dsav" internal="ff_rx_dsav" />
<port name="ff_rx_a_full" internal="ff_rx_a_full" />
<port name="ff_rx_a_empty" internal="ff_rx_a_empty" />
</interface>
<interface
name="status_led_connection"
internal="eth_tse_0.status_led_connection"
type="conduit"
dir="end">
<port name="led_crs" internal="led_crs" />
<port name="led_link" internal="led_link" />
<port name="led_col" internal="led_col" />
<port name="led_an" internal="led_an" />
<port name="led_char_err" internal="led_char_err" />
<port name="led_disp_err" internal="led_disp_err" />
</interface>
<interface
name="serdes_control_connection"
internal="eth_tse_0.serdes_control_connection"
type="conduit"
dir="end">
<port name="sd_loopback" internal="sd_loopback" />
<port name="powerdown" internal="powerdown" />
</interface>
<interface
name="tbi_connection"
internal="eth_tse_0.tbi_connection"
type="conduit"
dir="end">
<port name="tbi_rx_clk" internal="tbi_rx_clk" />
<port name="tbi_tx_clk" internal="tbi_tx_clk" />
<port name="tbi_rx_d" internal="tbi_rx_d" />
<port name="tbi_tx_d" internal="tbi_tx_d" />
</interface>
<module
kind="altera_eth_tse"
version="14.0"
enabled="1"
name="eth_tse_0"
autoexport="1">
<parameter name="deviceFamilyName" value="Arria 10" />
<parameter name="core_variation" value="MAC_PCS" />
<parameter name="ifGMII" value="MII_GMII" />
<parameter name="enable_use_internal_fifo" value="true" />
<parameter name="enable_ecc" value="false" />
<parameter name="max_channels" value="1" />
<parameter name="use_misc_ports" value="true" />
<parameter name="transceiver_type" value="NONE" />
<parameter name="enable_hd_logic" value="false" />
<parameter name="enable_gmii_loopback" value="true" />
<parameter name="enable_sup_addr" value="false" />
<parameter name="stat_cnt_ena" value="false" />
<parameter name="ext_stat_cnt_ena" value="false" />
<parameter name="ena_hash" value="false" />
<parameter name="enable_shift16" value="true" />
<parameter name="enable_mac_flow_ctrl" value="false" />
<parameter name="enable_mac_vlan" value="false" />
<parameter name="enable_magic_detect" value="false" />
<parameter name="useMDIO" value="false" />
<parameter name="mdio_clk_div" value="40" />
<parameter name="enable_ena" value="32" />
<parameter name="eg_addr" value="8" />
<parameter name="ing_addr" value="8" />
<parameter name="phy_identifier" value="0" />
<parameter name="enable_sgmii" value="false" />
<parameter name="export_pwrdn" value="false" />
<parameter name="enable_alt_reconfig" value="false" />
<parameter name="starting_channel_number" value="0" />
<parameter name="phyip_pll_type" value="CMU" />
<parameter name="phyip_pll_base_data_rate" value="1250 Mbps" />
<parameter name="phyip_en_synce_support" value="false" />
<parameter name="phyip_pma_bonding_mode" value="x1" />
<parameter name="nf_phyip_rcfg_enable" value="false" />
<parameter name="enable_timestamping" value="false" />
<parameter name="enable_ptp_1step" value="false" />
<parameter name="tstamp_fp_width" value="4" />
<parameter name="AUTO_DEVICE" value="Unknown" />
</module>
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
<interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
</system>
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