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Commit bb3449b7 authored by Eric Kooistra's avatar Eric Kooistra
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Correct tb indices.

parent 06681bc4
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1 merge request!288Resolve L2SDP-836
Pipeline #38461 passed
Stage: simulation
Stage: synthesis
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libraries/io/eth/tb/vhdl/tb_tb_eth_tester.vhd
+ 66
− 29
View file @ bb3449b7
......@@ -40,22 +40,24 @@ END tb_tb_eth_tester;
ARCHITECTURE tb OF tb_tb_eth_tester IS
-- Multi tb
CONSTANT c_tb_w : NATURAL := 50; -- sufficiently long to fit all tb instances
CONSTANT c_tb_w : NATURAL := 60; -- sufficiently long to fit all tb instances
CONSTANT c_tb_end_vec : STD_LOGIC_VECTOR(c_tb_w-1 DOWNTO 0) := (OTHERS=>'1');
SIGNAL tb_end_vec : STD_LOGIC_VECTOR(c_tb_w-1 DOWNTO 0) := c_tb_end_vec;
SIGNAL tb_end_vec : STD_LOGIC_VECTOR(c_tb_w-1 DOWNTO 0) := c_tb_end_vec; -- best view as hex in Wave Window
SIGNAL tb_end : STD_LOGIC := '0';
-- Tb
CONSTANT c_eth_clk_MHz : NATURAL := 125;
CONSTANT c_st_clk_MHz : NATURAL := 200;
CONSTANT c_nof_sync : NATURAL := 3;
CONSTANT c_nof_sync_many : NATURAL := 100;
CONSTANT c_nof_sync_many : NATURAL := 50; -- sufficient to achieve Tx FIFO fill level
CONSTANT c_nof_streams : NATURAL := 3;
-- Tx packet size and gap size in octets
CONSTANT c_block_len : NATURAL := 50; -- BG block length of first stream [0]
CONSTANT c_link_len : NATURAL := func_eth_tester_eth_packet_on_link_length(c_block_len);
CONSTANT c_block_len : NATURAL := 50; -- BG block length of first stream [0]
CONSTANT c_block_len_odd : NATURAL := 51;
CONSTANT c_block_len_jumbo : NATURAL := 9000;
CONSTANT c_link_len : NATURAL := func_eth_tester_eth_packet_on_link_length(c_block_len);
-- For near maximum 1Gbps link rate the c_block_len + c_gap_len_min time
-- in the st_clk domain equals c_link_len time in eth_clk domain.
......@@ -69,23 +71,23 @@ ARCHITECTURE tb OF tb_tb_eth_tester IS
-- Choose c_others_len > c_block_len, so same c_gap_len is suitable to
-- keep Ethernet link rate < 1 Gbps
CONSTANT c_other_len : NATURAL := 65; -- BG block length of other streams [c_nof_streams-1 : 1]
CONSTANT c_others_len : NATURAL := 65; -- BG block length of other streams [c_nof_streams-1 : 1]
-- BG ctrl
CONSTANT c_high : NATURAL := c_diag_bg_mem_max_adr; -- = 2**24
CONSTANT c_bg_ctrl_rst : t_diag_block_gen_integer := ('0', '0', 1, 8, c_gap_len, 0, c_high, 0); -- place holder for unused stream
CONSTANT c_bg_ctrl_one : t_diag_block_gen_integer := ('1', '1', c_block_len, 8, c_gap_len, 0, c_high, 0); -- for first stream
CONSTANT c_bg_ctrl_others : t_diag_block_gen_integer := ('1', '1', c_other_len, 8, c_gap_len, 0, c_high, 0); -- for other streams
CONSTANT c_bg_ctrl_one : t_diag_block_gen_integer := ('1', '1', c_block_len, 8, c_gap_len, 0, c_high, 0); -- for first stream
CONSTANT c_bg_ctrl_others : t_diag_block_gen_integer := ('1', '1', c_others_len, 8, c_gap_len, 0, c_high, 0); -- for other streams
CONSTANT c_bg_ctrl_len_0 : t_diag_block_gen_integer := ('1', '1', c_block_len+0, 8, c_gap_len, 0, c_high, 0); -- nof octets
CONSTANT c_bg_ctrl_len_1 : t_diag_block_gen_integer := ('1', '1', c_block_len+1, 8, c_gap_len, 0, c_high, 0); -- nof octets
CONSTANT c_bg_ctrl_len_2 : t_diag_block_gen_integer := ('1', '1', c_block_len+2, 8, c_gap_len, 0, c_high, 0); -- nof octets
CONSTANT c_bg_ctrl_len_3 : t_diag_block_gen_integer := ('1', '1', c_block_len+3, 8, c_gap_len, 0, c_high, 0); -- nof octets
CONSTANT c_bg_ctrl_multiple_first : t_diag_block_gen_integer := ('1', '1', c_block_len, 8, c_nof_streams * c_gap_len, 0, c_high, 0); -- for first stream
CONSTANT c_bg_ctrl_multiple_others : t_diag_block_gen_integer := ('1', '1', c_other_len, 8, c_nof_streams * c_gap_len, 0, c_high, 0); -- for other streams
CONSTANT c_bg_ctrl_multiple_first : t_diag_block_gen_integer := ('1', '1', c_block_len, 8, c_nof_streams * c_gap_len, 0, c_high, 0); -- for first stream
CONSTANT c_bg_ctrl_multiple_others : t_diag_block_gen_integer := ('1', '1', c_others_len, 8, c_nof_streams * c_gap_len, 0, c_high, 0); -- for other streams
BEGIN
......@@ -120,33 +122,68 @@ BEGIN
u_sim_tse : ENTITY work.tb_eth_tester GENERIC MAP (1, c_nof_sync, 1, TRUE, 1, c_bg_ctrl_one, c_bg_ctrl_rst) PORT MAP (tb_end_vec(1));
u_tech_tse : ENTITY work.tb_eth_tester GENERIC MAP (2, c_nof_sync, 1, TRUE, 0, c_bg_ctrl_one, c_bg_ctrl_rst) PORT MAP (tb_end_vec(2));
-- Try nof blocks_per_sync = 1
u_st_jumbo1 : ENTITY work.tb_eth_tester GENERIC MAP (10, c_nof_sync, 1, FALSE, 1,
('1', '1', c_block_len_jumbo, 1, c_zero_gap, 0, c_high, 0),
c_bg_ctrl_rst)
PORT MAP (tb_end_vec(10));
-- Try large block size
u_st_jumbo2 : ENTITY work.tb_eth_tester GENERIC MAP (11, c_nof_sync, 1, FALSE, 1,
('1', '1', c_block_len_jumbo, 2, c_zero_gap, 0, c_high, 0),
c_bg_ctrl_rst)
PORT MAP (tb_end_vec(11));
u_sim_tse_jumbo : ENTITY work.tb_eth_tester GENERIC MAP (12, c_nof_sync, 1, TRUE, 1,
('1', '1', c_block_len_jumbo, 2, c_zero_gap, 0, c_high, 0),
c_bg_ctrl_rst)
PORT MAP (tb_end_vec(12));
-- Try different BG block lengths to verify sosi.empty nof octets in last word
u_st_bg_len_0 : ENTITY work.tb_eth_tester GENERIC MAP (10, c_nof_sync, 1, FALSE, 1, c_bg_ctrl_len_0, c_bg_ctrl_rst) PORT MAP (tb_end_vec(10));
u_st_bg_len_1 : ENTITY work.tb_eth_tester GENERIC MAP (11, c_nof_sync, 1, FALSE, 1, c_bg_ctrl_len_1, c_bg_ctrl_rst) PORT MAP (tb_end_vec(11));
u_st_bg_len_2 : ENTITY work.tb_eth_tester GENERIC MAP (12, c_nof_sync, 1, FALSE, 1, c_bg_ctrl_len_2, c_bg_ctrl_rst) PORT MAP (tb_end_vec(12));
u_st_bg_len_3 : ENTITY work.tb_eth_tester GENERIC MAP (13, c_nof_sync, 1, FALSE, 1, c_bg_ctrl_len_3, c_bg_ctrl_rst) PORT MAP (tb_end_vec(13));
-- Try BG xon/xoff block flow control by using smaller gapsize that would exceed 1 Gbps
u_st_bg_flow_control : ENTITY work.tb_eth_tester
GENERIC MAP (20, c_nof_sync, 1, FALSE, 1,
('1', '1', c_block_len, 8, c_zero_gap, 0, c_high, 0),
c_bg_ctrl_rst)
PORT MAP (tb_end_vec(20));
u_st_bg_len_0 : ENTITY work.tb_eth_tester GENERIC MAP (30, c_nof_sync, 1, FALSE, 1, c_bg_ctrl_len_0, c_bg_ctrl_rst) PORT MAP (tb_end_vec(30));
u_st_bg_len_1 : ENTITY work.tb_eth_tester GENERIC MAP (31, c_nof_sync, 1, FALSE, 1, c_bg_ctrl_len_1, c_bg_ctrl_rst) PORT MAP (tb_end_vec(31));
u_st_bg_len_2 : ENTITY work.tb_eth_tester GENERIC MAP (32, c_nof_sync, 1, FALSE, 1, c_bg_ctrl_len_2, c_bg_ctrl_rst) PORT MAP (tb_end_vec(32));
u_st_bg_len_3 : ENTITY work.tb_eth_tester GENERIC MAP (33, c_nof_sync, 1, FALSE, 1, c_bg_ctrl_len_3, c_bg_ctrl_rst) PORT MAP (tb_end_vec(33));
-- Try BG xon/xoff block flow control by using smaller gapsize that would
-- exceed 1 Gbps. Use c_nof_sync_many to fill Tx FIFO. Use tse because
-- tse is limited to 1 Gbps, the st interface can achieve > 1 Gbps.
-- Try BG ready clock flow control by using c_block_len_odd to have BG
-- sosi.empy /= 0 and use zero gapsize to have BG blocks directly after
-- each other.
u_sim_tse_bg_flow_control : ENTITY work.tb_eth_tester
GENERIC MAP (40, c_nof_sync_many, 1, TRUE, 1,
('1', '1', c_block_len_odd, 8, c_zero_gap, 0, c_high, 0),
c_bg_ctrl_rst)
PORT MAP (tb_end_vec(40));
u_tech_tse_bg_flow_control : ENTITY work.tb_eth_tester
GENERIC MAP (41, c_nof_sync_many, 1, TRUE, 0,
('1', '1', c_block_len_odd, 8, c_zero_gap, 0, c_high, 0),
c_bg_ctrl_rst)
PORT MAP (tb_end_vec(41));
-----------------------------------------------------------------------------
-- Multiple streams
-----------------------------------------------------------------------------
u_st_multiple_streams : ENTITY work.tb_eth_tester
GENERIC MAP (30, c_nof_sync, c_nof_streams, FALSE, 1,
GENERIC MAP (50, c_nof_sync, c_nof_streams, FALSE, 1,
c_bg_ctrl_multiple_first,
c_bg_ctrl_multiple_others)
PORT MAP (tb_end_vec(30));
u_st_multiple_bg_flow_control : ENTITY work.tb_eth_tester
GENERIC MAP (31, c_nof_sync_many, c_nof_streams, FALSE, 1,
('1', '1', c_block_len, 8, c_short_gap, 0, c_high, 0),
('1', '1', c_other_len, 8, c_short_gap, 0, c_high, 0))
PORT MAP (tb_end_vec(31));
PORT MAP (tb_end_vec(50));
-- Use tse to verify dp_mux and dp_demux in ETH module [1]
u_sim_tse_multiple_streams : ENTITY work.tb_eth_tester
GENERIC MAP (51, c_nof_sync, c_nof_streams, TRUE, 1,
c_bg_ctrl_multiple_first,
c_bg_ctrl_multiple_others)
PORT MAP (tb_end_vec(51));
u_sim_tse_multiple_bg_flow_control : ENTITY work.tb_eth_tester
GENERIC MAP (52, c_nof_sync_many, c_nof_streams, TRUE, 1,
('1', '1', c_block_len, 8, c_short_gap, 0, c_high, 0),
('1', '1', c_others_len, 8, c_short_gap, 0, c_high, 0))
PORT MAP (tb_end_vec(52));
tb_end <= '1' WHEN tb_end_vec = c_tb_end_vec ELSE '0';
......
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