Skip to content
GitLab
Explore
Sign in
Register
Primary navigation
Search or go to…
Project
H
HDL
Manage
Activity
Members
Labels
Plan
Issues
Issue boards
Milestones
Iterations
Wiki
Requirements
Jira
Code
Merge requests
Repository
Branches
Commits
Tags
Repository graph
Compare revisions
Snippets
Locked files
Build
Pipelines
Jobs
Pipeline schedules
Test cases
Artifacts
Deploy
Releases
Container registry
Model registry
Operate
Environments
Monitor
Incidents
Analyze
Value stream analytics
Contributor analytics
CI/CD analytics
Repository analytics
Code review analytics
Issue analytics
Insights
Model experiments
Help
Help
Support
GitLab documentation
Compare GitLab plans
GitLab community forum
Contribute to GitLab
Provide feedback
Keyboard shortcuts
?
Snippets
Groups
Projects
Show more breadcrumbs
RTSD
HDL
Commits
ba698abe
Commit
ba698abe
authored
Nov 13, 2015
by
Daniel van der Schuur
Browse files
Options
Downloads
Patches
Plain Diff
-Commented out print statements.
parent
9523d0df
No related branches found
No related tags found
No related merge requests found
Changes
1
Show whitespace changes
Inline
Side-by-side
Showing
1 changed file
tools/oneclick/components/component.py
+11
-11
11 additions, 11 deletions
tools/oneclick/components/component.py
with
11 additions
and
11 deletions
tools/oneclick/components/component.py
+
11
−
11
View file @
ba698abe
...
@@ -270,7 +270,7 @@ class Component(mp.Process):
...
@@ -270,7 +270,7 @@ class Component(mp.Process):
# Get a list of the subcomponent's __init__ argument names
# Get a list of the subcomponent's __init__ argument names
args_init_names
=
cm
.
method_arg_names
(
subcomponent
.
__init__
)[
1
:]
args_init_names
=
cm
.
method_arg_names
(
subcomponent
.
__init__
)[
1
:]
print
'
args init
'
,
args_init_names
#
print 'args init', args_init_names
# Get a of the subcomponent's __init__ argument as they were passed LITERALLY.
# Get a of the subcomponent's __init__ argument as they were passed LITERALLY.
...
@@ -278,10 +278,10 @@ class Component(mp.Process):
...
@@ -278,10 +278,10 @@ class Component(mp.Process):
last_call
=
stack
[
0
][
3
]
last_call
=
stack
[
0
][
3
]
args_str
=
last_call
[
last_call
.
index
(
"
(
"
)
+
1
:
last_call
.
rindex
(
"
)
"
)]
args_str
=
last_call
[
last_call
.
index
(
"
(
"
)
+
1
:
last_call
.
rindex
(
"
)
"
)]
args_passed_literal
=
args_str
.
split
(
'
,
'
)
args_passed_literal
=
args_str
.
split
(
'
,
'
)
print
'
passed args (literal):
'
,
args_passed_literal
#
print 'passed args (literal):', args_passed_literal
# Go through the subcomponent's attributes (set by __init__)
# Go through the subcomponent's attributes (set by __init__)
print
'
passed args (value):
'
#
print 'passed args (value):'
self
.
vhdl_constants
=
vhdl_constants
#NOTE set self.vhdl_constants here, we'll overwrite portions of it as we go along.
self
.
vhdl_constants
=
vhdl_constants
#NOTE set self.vhdl_constants here, we'll overwrite portions of it as we go along.
# Zip: Get the corresponding literal string that was passed to our component in the top level Python file.
# Zip: Get the corresponding literal string that was passed to our component in the top level Python file.
...
@@ -292,7 +292,7 @@ class Component(mp.Process):
...
@@ -292,7 +292,7 @@ class Component(mp.Process):
attr_value
=
getattr
(
subcomponent
,
arg_init_name
)
attr_value
=
getattr
(
subcomponent
,
arg_init_name
)
is_constant
=
True
#FIXME - We also need to cover composite arguments such as '2*NOF_TELESCOPES'.
is_constant
=
True
#FIXME - We also need to cover composite arguments such as '2*NOF_TELESCOPES'.
print
arg_passed_literal
#
print arg_passed_literal
if
arg_passed_literal
==
None
:
if
arg_passed_literal
==
None
:
is_constant
=
False
is_constant
=
False
# If arg_passed_literal contains quotes, it was not passed as a constant (constant names do not have extra quotes)
# If arg_passed_literal contains quotes, it was not passed as a constant (constant names do not have extra quotes)
...
@@ -307,7 +307,7 @@ class Component(mp.Process):
...
@@ -307,7 +307,7 @@ class Component(mp.Process):
except
:
except
:
pass
pass
print
arg_init_name
,
attr_value
,
arg_passed_literal
,
is_constant
#
print arg_init_name, attr_value, arg_passed_literal, is_constant
# So now we know if we need to paste the value- or constant name string in the VHDL strings.
# So now we know if we need to paste the value- or constant name string in the VHDL strings.
if
is_constant
==
True
:
if
is_constant
==
True
:
...
@@ -320,10 +320,10 @@ class Component(mp.Process):
...
@@ -320,10 +320,10 @@ class Component(mp.Process):
if
arg_passed_literal
in
line
:
if
arg_passed_literal
in
line
:
# We can find the VHDL type between the ':' and the ':='
# We can find the VHDL type between the ':' and the ':='
arg_vhdl_type
=
line
.
split
(
'
:=
'
)[
-
2
].
split
(
'
:
'
)[
-
1
]
arg_vhdl_type
=
line
.
split
(
'
:=
'
)[
-
2
].
split
(
'
:
'
)[
-
1
]
print
'
debug2
'
,
arg_vhdl_type
#
print 'debug2', arg_vhdl_type
self
.
vhdl_parent_constants
.
append
(
'
CONSTANT %s : %s := %s;
\n
'
%
(
arg_passed_literal
,
arg_vhdl_type
,
attr_value
))
self
.
vhdl_parent_constants
.
append
(
'
CONSTANT %s : %s := %s;
\n
'
%
(
arg_passed_literal
,
arg_vhdl_type
,
attr_value
))
print
self
.
vhdl_parent_constants
#
print self.vhdl_parent_constants
else
:
else
:
# Put the actual value there (e.g. '12')
# Put the actual value there (e.g. '12')
self
.
vhdl_constants
=
self
.
vhdl_constants
.
replace
(
'
$
'
+
arg_init_name
,
str
(
attr_value
))
self
.
vhdl_constants
=
self
.
vhdl_constants
.
replace
(
'
$
'
+
arg_init_name
,
str
(
attr_value
))
...
@@ -371,10 +371,10 @@ class Component(mp.Process):
...
@@ -371,10 +371,10 @@ class Component(mp.Process):
for
component
in
self
.
components
:
for
component
in
self
.
components
:
target_vhdl_file
.
write
(
component
.
vhdl_lib
)
target_vhdl_file
.
write
(
component
.
vhdl_lib
)
print
component
.
vhdl_lib
#
print component.vhdl_lib
vhdl_lib_str_words
=
component
.
vhdl_lib
.
replace
(
'
;
'
,
''
).
split
(
'
'
)
vhdl_lib_str_words
=
component
.
vhdl_lib
.
replace
(
'
;
'
,
''
).
split
(
'
'
)
for
word
in
vhdl_lib_str_words
:
for
word
in
vhdl_lib_str_words
:
print
word
#
print word
if
'
_lib
'
in
word
and
not
'
USE
'
in
word
and
not
'
.
'
in
word
and
word
not
in
self
.
hdllib_used_libs
:
if
'
_lib
'
in
word
and
not
'
USE
'
in
word
and
not
'
.
'
in
word
and
word
not
in
self
.
hdllib_used_libs
:
self
.
hdllib_used_libs
+=
word
.
replace
(
'
_lib
'
,
''
).
replace
(
'
\n
'
,
''
)
+
'
'
self
.
hdllib_used_libs
+=
word
.
replace
(
'
_lib
'
,
''
).
replace
(
'
\n
'
,
''
)
+
'
'
# target_vhdl_file.write(STANDARD_LIBS)
# target_vhdl_file.write(STANDARD_LIBS)
...
@@ -405,9 +405,9 @@ class Component(mp.Process):
...
@@ -405,9 +405,9 @@ class Component(mp.Process):
for
component
in
self
.
components
:
for
component
in
self
.
components
:
# Paste the parent constants
# Paste the parent constants
print
component
.
vhdl_parent_constants
#
print component.vhdl_parent_constants
for
vhdl_parent_constant
in
component
.
vhdl_parent_constants
:
for
vhdl_parent_constant
in
component
.
vhdl_parent_constants
:
print
'
debug
'
,
vhdl_parent_constant
#
print 'debug', vhdl_parent_constant
target_vhdl_file
.
write
(
vhdl_parent_constant
)
target_vhdl_file
.
write
(
vhdl_parent_constant
)
target_vhdl_file
.
write
(
component
.
vhdl_name_comment_block
)
target_vhdl_file
.
write
(
component
.
vhdl_name_comment_block
)
...
...
This diff is collapsed.
Click to expand it.
Preview
0%
Loading
Try again
or
attach a new file
.
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Save comment
Cancel
Please
register
or
sign in
to comment