Merge branch 'HPR-85' into 'master'

Resolve HPR-85

Closes HPR-85

See merge request desp/hdl!331

libraries/io/eth/hdllib.cfg

@@ -28,7 +28,7 @@ synth_files =
     src/vhdl/eth_tester_tx.vhd
     src/vhdl/eth_tester_rx.vhd
     src/vhdl/eth_tester.vhd
-    src/vhdl/eth_tester_axi4_wrapper.vhd
+    src/vhdl/eth_tester_vivado_ip_wrapper.vhd
 
 test_bench_files = 
     src/vhdl/eth_statistics.vhd

libraries/io/eth/src/vhdl/eth_tester_vivado_ip_wrapper.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright 2023
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+--     http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+-- Author: R. van der Walle
+-- Purpose: Provide AXI-4-stream interfaces + standard avalon MM interfaces for 
+--          eth_tester.vhd such that it can be used to create a Vivado IP block.
+-- Description: 
+-- . The eth_tester_vivado_ip_wrapper uses axi4_stream_dp_bridge to convert the dp
+--   sosi/siso interfaces of the eth_tester into AXI4-Stream interfaces.
+-- . In order for this component to be suitable as a Vivado IP, the ports are
+--   exclusively STD_LOGIC(_VECTOR) where the widths are hard-coded as demanded
+--   by the Vivado IP creator (only supports VHDL-93).
+-- Remark
+-- . Avalon is used for all MM interfaces, which can be bridged to AXI4-Lite in 
+--   vivado using the AXI AMM Bridge IP.
+
+LIBRARY IEEE, common_lib, dp_lib, diag_lib, axi4_lib;
+USE IEEE.std_logic_1164.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE common_lib.common_network_layers_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE dp_lib.dp_components_pkg.ALL;
+USE diag_lib.diag_pkg.ALL;
+USE axi4_lib.axi4_stream_pkg.ALL;
+USE work.eth_pkg.ALL;
+USE work.eth_tester_pkg.ALL;
+
+ENTITY eth_tester_vivado_ip_wrapper IS  
+  PORT (
+    -- Clocks and reset
+    mm_clk             : IN  STD_LOGIC;
+    st_clk             : IN  STD_LOGIC;
+    st_pps             : IN  STD_LOGIC;
+    aresetn            : IN  STD_LOGIC;
+    -- UDP transmit interface
+    eth_src_mac        : IN  STD_LOGIC_VECTOR(6*8-1 DOWNTO 0);
+    ip_src_addr        : IN  STD_LOGIC_VECTOR(4*8-1 DOWNTO 0);
+    udp_src_port       : IN  STD_LOGIC_VECTOR(2*8-1 DOWNTO 0);
+
+    tx_fifo_rd_emp_arr : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+
+    -- tx_udp
+    -- Source In and Sink Out
+    tx_udp_tready    : IN STD_LOGIC;
+
+    -- Source Out and Sink In
+    tx_udp_tvalid    : OUT STD_LOGIC;
+    tx_udp_tdata     : OUT STD_LOGIC_VECTOR(512-1 DOWNTO 0);
+    tx_udp_tstrb     : OUT STD_LOGIC_VECTOR(512/8-1 DOWNTO 0);
+    tx_udp_tkeep     : OUT STD_LOGIC_VECTOR(512/8-1 DOWNTO 0);
+    tx_udp_tlast     : OUT STD_LOGIC;
+    tx_udp_tid       : OUT STD_LOGIC_VECTOR(4-1 DOWNTO 0);
+    tx_udp_tdest     : OUT STD_LOGIC_VECTOR(32-1 DOWNTO 0);
+    tx_udp_tuser     : OUT STD_LOGIC_VECTOR(70-1 DOWNTO 0);
+
+    -- rx_udp
+    -- Source In and Sink Out
+    rx_udp_tready    : OUT STD_LOGIC;
+
+    -- Source Out and Sink In
+    rx_udp_tvalid    : IN STD_LOGIC;
+    rx_udp_tdata     : IN STD_LOGIC_VECTOR(512-1 DOWNTO 0);
+    rx_udp_tstrb     : IN STD_LOGIC_VECTOR(512/8-1 DOWNTO 0);
+    rx_udp_tkeep     : IN STD_LOGIC_VECTOR(512/8-1 DOWNTO 0);
+    rx_udp_tlast     : IN STD_LOGIC;
+    rx_udp_tid       : IN STD_LOGIC_VECTOR(4-1 DOWNTO 0);
+    rx_udp_tdest     : IN STD_LOGIC_VECTOR(32-1 DOWNTO 0);
+    rx_udp_tuser     : IN STD_LOGIC_VECTOR(70-1 DOWNTO 0);
+
+    -- reg_bg_ctrl
+    reg_bg_ctrl_avm_address                     : IN  STD_LOGIC_VECTOR(32-1 downto 0);
+    reg_bg_ctrl_avm_read                        : IN  STD_LOGIC;
+    reg_bg_ctrl_avm_readdata                    : OUT STD_LOGIC_VECTOR(32-1 downto 0);
+    reg_bg_ctrl_avm_readdatavalid               : OUT STD_LOGIC; 
+    reg_bg_ctrl_avm_waitrequest                 : OUT STD_LOGIC; 
+    reg_bg_ctrl_avm_write                       : IN  STD_LOGIC;
+    reg_bg_ctrl_avm_writedata                   : IN  STD_LOGIC_VECTOR(32-1 downto 0);
+
+    -- reg_hdr_dat
+    reg_hdr_dat_avm_address                     : IN  STD_LOGIC_VECTOR(32-1 downto 0);
+    reg_hdr_dat_avm_read                        : IN  STD_LOGIC;
+    reg_hdr_dat_avm_readdata                    : OUT STD_LOGIC_VECTOR(32-1 downto 0);
+    reg_hdr_dat_avm_readdatavalid               : OUT STD_LOGIC; 
+    reg_hdr_dat_avm_waitrequest                 : OUT STD_LOGIC; 
+    reg_hdr_dat_avm_write                       : IN  STD_LOGIC;
+    reg_hdr_dat_avm_writedata                   : IN  STD_LOGIC_VECTOR(32-1 downto 0);
+
+    -- reg_bsn_monitor_v2_tx
+    reg_bsn_monitor_v2_tx_avm_address           : IN  STD_LOGIC_VECTOR(32-1 downto 0);
+    reg_bsn_monitor_v2_tx_avm_read              : IN  STD_LOGIC;
+    reg_bsn_monitor_v2_tx_avm_readdata          : OUT STD_LOGIC_VECTOR(32-1 downto 0);
+    reg_bsn_monitor_v2_tx_avm_readdatavalid     : OUT STD_LOGIC; 
+    reg_bsn_monitor_v2_tx_avm_waitrequest       : OUT STD_LOGIC; 
+    reg_bsn_monitor_v2_tx_avm_write             : IN  STD_LOGIC;
+    reg_bsn_monitor_v2_tx_avm_writedata         : IN  STD_LOGIC_VECTOR(32-1 downto 0);
+
+    -- reg_strobe_total_count_tx
+    reg_strobe_total_count_tx_avm_address       : IN  STD_LOGIC_VECTOR(32-1 downto 0);
+    reg_strobe_total_count_tx_avm_read          : IN  STD_LOGIC;
+    reg_strobe_total_count_tx_avm_readdata      : OUT STD_LOGIC_VECTOR(32-1 downto 0);
+    reg_strobe_total_count_tx_avm_readdatavalid : OUT STD_LOGIC; 
+    reg_strobe_total_count_tx_avm_waitrequest   : OUT STD_LOGIC; 
+    reg_strobe_total_count_tx_avm_write         : IN  STD_LOGIC;
+    reg_strobe_total_count_tx_avm_writedata     : IN  STD_LOGIC_VECTOR(32-1 downto 0);
+
+    -- reg_bsn_monitor_v2_rx
+    reg_bsn_monitor_v2_rx_avm_address           : IN  STD_LOGIC_VECTOR(32-1 downto 0);
+    reg_bsn_monitor_v2_rx_avm_read              : IN  STD_LOGIC;
+    reg_bsn_monitor_v2_rx_avm_readdata          : OUT STD_LOGIC_VECTOR(32-1 downto 0);
+    reg_bsn_monitor_v2_rx_avm_readdatavalid     : OUT STD_LOGIC; 
+    reg_bsn_monitor_v2_rx_avm_waitrequest       : OUT STD_LOGIC; 
+    reg_bsn_monitor_v2_rx_avm_write             : IN  STD_LOGIC;
+    reg_bsn_monitor_v2_rx_avm_writedata         : IN  STD_LOGIC_VECTOR(32-1 downto 0);
+
+    -- reg_strobe_total_count_rx
+    reg_strobe_total_count_rx_avm_address       : IN  STD_LOGIC_VECTOR(32-1 downto 0);
+    reg_strobe_total_count_rx_avm_read          : IN  STD_LOGIC;
+    reg_strobe_total_count_rx_avm_readdata      : OUT STD_LOGIC_VECTOR(32-1 downto 0);
+    reg_strobe_total_count_rx_avm_readdatavalid : OUT STD_LOGIC; 
+    reg_strobe_total_count_rx_avm_waitrequest   : OUT STD_LOGIC; 
+    reg_strobe_total_count_rx_avm_write         : IN  STD_LOGIC;
+    reg_strobe_total_count_rx_avm_writedata     : IN  STD_LOGIC_VECTOR(32-1 downto 0)
+
+   );
+END eth_tester_vivado_ip_wrapper;
+
+
+ARCHITECTURE str OF eth_tester_vivado_ip_wrapper IS
+  SIGNAL rx_udp_sosi_arr                : t_dp_sosi_arr(0 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+  SIGNAL rx_udp_siso_arr                : t_dp_siso_arr(0 DOWNTO 0) := (OTHERS => c_dp_siso_rdy);
+  SIGNAL tx_udp_sosi_arr                : t_dp_sosi_arr(0 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+  SIGNAL tx_udp_siso_arr                : t_dp_siso_arr(0 DOWNTO 0) := (OTHERS => c_dp_siso_rdy);
+
+  SIGNAL rx_udp_axi4_sosi               : t_axi4_sosi := c_axi4_sosi_rst;
+  SIGNAL rx_udp_axi4_siso               : t_axi4_siso := c_axi4_siso_rst;
+  SIGNAL tx_udp_axi4_sosi               : t_axi4_sosi := c_axi4_sosi_rst;
+  SIGNAL tx_udp_axi4_siso               : t_axi4_siso := c_axi4_siso_rst;
+
+  SIGNAL reg_bg_ctrl_copi               : t_mem_copi := c_mem_copi_rst;
+  SIGNAL reg_bg_ctrl_cipo               : t_mem_cipo;
+  SIGNAL reg_hdr_dat_copi               : t_mem_copi := c_mem_copi_rst;
+  SIGNAL reg_hdr_dat_cipo               : t_mem_cipo;
+  SIGNAL reg_bsn_monitor_v2_tx_copi     : t_mem_copi := c_mem_copi_rst;
+  SIGNAL reg_bsn_monitor_v2_tx_cipo     : t_mem_cipo;
+  SIGNAL reg_strobe_total_count_tx_copi : t_mem_copi := c_mem_copi_rst;
+  SIGNAL reg_strobe_total_count_tx_cipo : t_mem_cipo;
+
+  SIGNAL reg_bsn_monitor_v2_rx_copi     : t_mem_copi := c_mem_copi_rst;
+  SIGNAL reg_bsn_monitor_v2_rx_cipo     : t_mem_cipo;
+  SIGNAL reg_strobe_total_count_rx_copi : t_mem_copi := c_mem_copi_rst;
+  SIGNAL reg_strobe_total_count_rx_cipo : t_mem_cipo;
+
+  SIGNAL mm_rst : STD_LOGIC := '0';
+  SIGNAL st_rst : STD_LOGIC := '0';
+
+BEGIN
+
+  u_eth_tester : ENTITY work.eth_tester
+  GENERIC MAP (
+    g_remove_crc => FALSE
+  )
+  PORT MAP (
+    -- Clocks and reset
+    mm_rst             => mm_rst,
+    mm_clk             => mm_clk,
+    st_rst             => st_rst,
+    st_clk             => st_clk,
+    st_pps             => st_pps,
+
+    -- UDP transmit interface
+    eth_src_mac        => eth_src_mac,
+    ip_src_addr        => ip_src_addr,
+    udp_src_port       => udp_src_port,
+
+    tx_fifo_rd_emp_arr => tx_fifo_rd_emp_arr,
+
+    tx_udp_sosi_arr    => tx_udp_sosi_arr,
+    tx_udp_siso_arr    => tx_udp_siso_arr,
+
+    -- UDP receive interface
+    rx_udp_sosi_arr    => rx_udp_sosi_arr,
+
+    -- Memory Mapped Slaves (one per stream)
+    reg_bg_ctrl_copi               => reg_bg_ctrl_copi,
+    reg_bg_ctrl_cipo               => reg_bg_ctrl_cipo,
+    reg_hdr_dat_copi               => reg_hdr_dat_copi,
+    reg_hdr_dat_cipo               => reg_hdr_dat_cipo,
+    reg_bsn_monitor_v2_tx_copi     => reg_bsn_monitor_v2_tx_copi,
+    reg_bsn_monitor_v2_tx_cipo     => reg_bsn_monitor_v2_tx_cipo,
+    reg_strobe_total_count_tx_copi => reg_strobe_total_count_tx_copi,
+    reg_strobe_total_count_tx_cipo => reg_strobe_total_count_tx_cipo,
+
+    reg_bsn_monitor_v2_rx_copi     => reg_bsn_monitor_v2_rx_copi,
+    reg_bsn_monitor_v2_rx_cipo     => reg_bsn_monitor_v2_rx_cipo,
+    reg_strobe_total_count_rx_copi => reg_strobe_total_count_rx_copi,
+    reg_strobe_total_count_rx_cipo => reg_strobe_total_count_rx_cipo
+  );
+
+  -- DP to AXI4
+  u_axi4_tx_udp : ENTITY axi4_lib.axi4_stream_dp_bridge
+  GENERIC MAP (
+    g_axi4_rl => 0,
+    g_dp_rl   => 1,
+    g_active_low_rst => TRUE
+  )
+  PORT MAP (
+    in_clk => st_clk,
+    in_rst => aresetn,
+
+    dp_rst => st_rst,
+
+    dp_in_sosi => tx_udp_sosi_arr(0),
+    dp_in_siso => tx_udp_siso_arr(0),
+
+    axi4_out_sosi => tx_udp_axi4_sosi,
+    axi4_out_siso => tx_udp_axi4_siso
+  );
+
+  u_axi4_rx_udp : ENTITY axi4_lib.axi4_stream_dp_bridge
+  GENERIC MAP (
+    g_axi4_rl => 0,
+    g_dp_rl   => 1,
+    g_active_low_rst => TRUE
+  )
+  PORT MAP (
+    in_clk => st_clk,
+    in_rst => aresetn,
+
+    axi4_in_sosi => rx_udp_axi4_sosi,
+    axi4_in_siso => rx_udp_axi4_siso,
+
+    dp_out_sosi => rx_udp_sosi_arr(0),
+    dp_out_siso => rx_udp_siso_arr(0)
+  );
+
+
+  -- Wire Records to IN/OUT ports.
+  -- tx_udp
+  tx_udp_axi4_siso.tready <= tx_udp_tready;
+
+  tx_udp_tvalid <= tx_udp_axi4_sosi.tvalid;
+  tx_udp_tdata  <= tx_udp_axi4_sosi.tdata;
+  tx_udp_tstrb  <= tx_udp_axi4_sosi.tstrb;
+  tx_udp_tkeep  <= tx_udp_axi4_sosi.tkeep;
+  tx_udp_tlast  <= tx_udp_axi4_sosi.tlast;
+  tx_udp_tid    <= tx_udp_axi4_sosi.tid;
+  tx_udp_tdest  <= tx_udp_axi4_sosi.tdest;
+  tx_udp_tuser  <= tx_udp_axi4_sosi.tuser;
+
+  -- rx_udp
+  rx_udp_tready <= rx_udp_axi4_siso.tready;
+
+  rx_udp_axi4_sosi.tvalid <= rx_udp_tvalid;
+  rx_udp_axi4_sosi.tdata  <= rx_udp_tdata;
+  rx_udp_axi4_sosi.tstrb  <= rx_udp_tstrb;
+  rx_udp_axi4_sosi.tkeep  <= rx_udp_tkeep;
+  rx_udp_axi4_sosi.tlast  <= rx_udp_tlast;
+  rx_udp_axi4_sosi.tid    <= rx_udp_tid;
+  rx_udp_axi4_sosi.tdest  <= rx_udp_tdest;
+  rx_udp_axi4_sosi.tuser  <= rx_udp_tuser;
+
+  -- reg_bg_ctrl
+  -- copi
+  reg_bg_ctrl_copi.address      <= reg_bg_ctrl_avm_address;
+  reg_bg_ctrl_copi.wrdata       <= RESIZE_UVEC(reg_bg_ctrl_avm_writedata, c_mem_data_w);
+  reg_bg_ctrl_copi.wr           <= reg_bg_ctrl_avm_write;
+  reg_bg_ctrl_copi.rd           <= reg_bg_ctrl_avm_read;
+  -- cipo
+  reg_bg_ctrl_avm_readdata      <= RESIZE_UVEC_32(reg_bg_ctrl_cipo.rddata);  
+  reg_bg_ctrl_avm_readdatavalid <= reg_bg_ctrl_cipo.rdval; 
+  reg_bg_ctrl_avm_waitrequest   <= reg_bg_ctrl_cipo.waitrequest;
+
+  -- reg_hdr_dat
+  -- copi
+  reg_hdr_dat_copi.address      <= reg_hdr_dat_avm_address;
+  reg_hdr_dat_copi.wrdata       <= RESIZE_UVEC(reg_hdr_dat_avm_writedata, c_mem_data_w);
+  reg_hdr_dat_copi.wr           <= reg_hdr_dat_avm_write;
+  reg_hdr_dat_copi.rd           <= reg_hdr_dat_avm_read;
+  -- cipo
+  reg_hdr_dat_avm_readdata      <= RESIZE_UVEC_32(reg_hdr_dat_cipo.rddata);  
+  reg_hdr_dat_avm_readdatavalid <= reg_hdr_dat_cipo.rdval; 
+  reg_hdr_dat_avm_waitrequest   <= reg_hdr_dat_cipo.waitrequest;
+
+  -- reg_bsn_monitor_v2_tx
+  -- copi
+  reg_bsn_monitor_v2_tx_copi.address      <= reg_bsn_monitor_v2_tx_avm_address;
+  reg_bsn_monitor_v2_tx_copi.wrdata       <= RESIZE_UVEC(reg_bsn_monitor_v2_tx_avm_writedata, c_mem_data_w);
+  reg_bsn_monitor_v2_tx_copi.wr           <= reg_bsn_monitor_v2_tx_avm_write;
+  reg_bsn_monitor_v2_tx_copi.rd           <= reg_bsn_monitor_v2_tx_avm_read;
+  -- cipo
+  reg_bsn_monitor_v2_tx_avm_readdata      <= RESIZE_UVEC_32(reg_bsn_monitor_v2_tx_cipo.rddata);  
+  reg_bsn_monitor_v2_tx_avm_readdatavalid <= reg_bsn_monitor_v2_tx_cipo.rdval; 
+  reg_bsn_monitor_v2_tx_avm_waitrequest   <= reg_bsn_monitor_v2_tx_cipo.waitrequest;
+
+  -- reg_strobe_total_count_tx
+  -- copi
+  reg_strobe_total_count_tx_copi.address      <= reg_strobe_total_count_tx_avm_address;
+  reg_strobe_total_count_tx_copi.wrdata       <= RESIZE_UVEC(reg_strobe_total_count_tx_avm_writedata, c_mem_data_w);
+  reg_strobe_total_count_tx_copi.wr           <= reg_strobe_total_count_tx_avm_write;
+  reg_strobe_total_count_tx_copi.rd           <= reg_strobe_total_count_tx_avm_read;
+  -- cipo
+  reg_strobe_total_count_tx_avm_readdata      <= RESIZE_UVEC_32(reg_strobe_total_count_tx_cipo.rddata);  
+  reg_strobe_total_count_tx_avm_readdatavalid <= reg_strobe_total_count_tx_cipo.rdval; 
+  reg_strobe_total_count_tx_avm_waitrequest   <= reg_strobe_total_count_tx_cipo.waitrequest;
+
+  -- reg_bsn_monitor_v2_rx
+  -- copi
+  reg_bsn_monitor_v2_rx_copi.address      <= reg_bsn_monitor_v2_rx_avm_address;
+  reg_bsn_monitor_v2_rx_copi.wrdata       <= RESIZE_UVEC(reg_bsn_monitor_v2_rx_avm_writedata, c_mem_data_w);
+  reg_bsn_monitor_v2_rx_copi.wr           <= reg_bsn_monitor_v2_rx_avm_write;
+  reg_bsn_monitor_v2_rx_copi.rd           <= reg_bsn_monitor_v2_rx_avm_read;
+  -- cipo
+  reg_bsn_monitor_v2_rx_avm_readdata      <= RESIZE_UVEC_32(reg_bsn_monitor_v2_rx_cipo.rddata);  
+  reg_bsn_monitor_v2_rx_avm_readdatavalid <= reg_bsn_monitor_v2_rx_cipo.rdval; 
+  reg_bsn_monitor_v2_rx_avm_waitrequest   <= reg_bsn_monitor_v2_rx_cipo.waitrequest;
+
+  -- reg_strobe_total_count_rx
+  -- copi
+  reg_strobe_total_count_rx_copi.address      <= reg_strobe_total_count_rx_avm_address;
+  reg_strobe_total_count_rx_copi.wrdata       <= RESIZE_UVEC(reg_strobe_total_count_rx_avm_writedata, c_mem_data_w);
+  reg_strobe_total_count_rx_copi.wr           <= reg_strobe_total_count_rx_avm_write;
+  reg_strobe_total_count_rx_copi.rd           <= reg_strobe_total_count_rx_avm_read;
+  -- cipo
+  reg_strobe_total_count_rx_avm_readdata      <= RESIZE_UVEC_32(reg_strobe_total_count_rx_cipo.rddata);  
+  reg_strobe_total_count_rx_avm_readdatavalid <= reg_strobe_total_count_rx_cipo.rdval; 
+  reg_strobe_total_count_rx_avm_waitrequest   <= reg_strobe_total_count_rx_cipo.waitrequest;
+
+END str;