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Commit ba49caa0 authored by Eric Kooistra's avatar Eric Kooistra
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Revert to master version. Keep ctrl as it is already refelcting the current WG state.

parent 4b783135
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1 merge request!210MM readback the currently active crosslets info, instead of the initial MM...
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libraries/base/diag/tb/vhdl/tb_diag_wg.vhd
+ 30
− 32
View file @ ba49caa0
......@@ -19,7 +19,7 @@
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--------------------------------------------------------------------------------
LIBRARY IEEE, common_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
......@@ -49,7 +49,7 @@ ARCHITECTURE tb OF tb_diag_wg IS
CONSTANT c_clk_freq : NATURAL := 200*10**6; -- Hz
CONSTANT c_clk_period : TIME := (10**9 / c_clk_freq) * 1 ns;
-- Default settings
CONSTANT c_buf : t_c_mem := (latency => 1,
adr_w => g_buf_adr_w,
......@@ -59,87 +59,86 @@ ARCHITECTURE tb OF tb_diag_wg IS
CONSTANT c_buf_file : STRING := sel_a_b(c_buf.adr_w=11 AND c_buf.dat_w=18, "data/diag_sin_2048x18.hex",
sel_a_b(c_buf.adr_w=10 AND c_buf.dat_w=18, "data/diag_sin_1024x18.hex",
sel_a_b(c_buf.adr_w=10 AND c_buf.dat_w= 8, "data/diag_sin_1024x8.hex", "UNUSED")));
CONSTANT c_wg_nof_samples : NATURAL := c_buf.nof_dat; -- must be <= c_buf.nof_dat
CONSTANT c_wg_gain_w : NATURAL := 1; -- Normalized range [0 1> maps to fixed point range [0:2**c_diag_wg_ampl_w>
-- . use gain 2**0 = 1 to have fulle scale without clipping
-- . use gain 2**g_calc_gain_w > 1 to cause clipping
CONSTANT c_buf_full_scale : NATURAL := 2**(g_buf_dat_w-1)-1; -- The stored waveform range should also be [-c_buf_full_scale +c_buf_full_scale], so not including -c_buf_full_scale-1
CONSTANT c_wg_full_scale : NATURAL := 2**(g_wg_dat_w-1)-1;
CONSTANT c_ampl_norm : REAL := sel_a_b(g_wg_dat_w < g_buf_dat_w, REAL(c_wg_full_scale)/REAL(c_wg_full_scale+1), 1.0);
--CONSTANT c_ampl_norm : REAL := REAL(c_wg_full_scale)/REAL(c_wg_full_scale+1); -- Use this if g_wg_dat_w < g_buf_dat_w, to avoid clipping
--CONSTANT c_ampl_norm : REAL := 1.0; -- Use this if g_wg_dat_w = g_buf_dat_w, because the stored waveform range is already -+c_buf_full_scale
--CONSTANT c_ampl_norm : REAL := REAL(c_buf_full_scale)/REAL(c_buf_full_scale+1); -- No need to use this, because the stored waveform range is already -+c_buf_full_scale
CONSTANT c_freq_unit : REAL := c_diag_wg_freq_unit; -- ^= c_clk_freq = Fs (sample frequency), assuming one sinus waveform in the buffer
CONSTANT c_ampl_unit : REAL := c_diag_wg_ampl_unit*c_ampl_norm; -- ^= Full Scale range [-c_wg_full_scale +c_wg_full_scale] without clipping
CONSTANT c_phase_unit : REAL := c_diag_wg_phase_unit; -- ^= 1 degree
SIGNAL tb_end : STD_LOGIC;
SIGNAL rst : STD_LOGIC;
SIGNAL clk : STD_LOGIC := '1';
SIGNAL restart : STD_LOGIC;
SIGNAL buf_rddat : STD_LOGIC_VECTOR(c_buf.dat_w-1 DOWNTO 0);
SIGNAL buf_rdval : STD_LOGIC;
SIGNAL buf_addr : STD_LOGIC_VECTOR(c_buf.adr_w-1 DOWNTO 0);
SIGNAL buf_rden : STD_LOGIC;
SIGNAL wg_ctrl : t_diag_wg;
SIGNAL wg_ctrl_act : t_diag_wg;
SIGNAL wg_mode : NATURAL;
SIGNAL wg_freq : NATURAL;
SIGNAL wg_ampl : NATURAL;
SIGNAL wg_nof_samples : NATURAL;
SIGNAL wg_phase : NATURAL;
SIGNAL wg_ovr : STD_LOGIC;
SIGNAL wg_dat : STD_LOGIC_VECTOR(c_buf.dat_w-1 DOWNTO 0);
SIGNAL wg_val : STD_LOGIC;
SIGNAL wg_sync : STD_LOGIC;
BEGIN
rst <= '1', '0' AFTER c_clk_period/10;
clk <= NOT clk OR tb_end AFTER c_clk_period/2;
wg_ctrl.mode <= TO_UVEC(wg_mode, c_diag_wg_mode_w);
wg_ctrl.freq <= TO_UVEC(wg_freq, c_diag_wg_freq_w);
wg_ctrl.ampl <= TO_UVEC(wg_ampl, c_diag_wg_ampl_w);
wg_ctrl.nof_samples <= TO_UVEC(wg_nof_samples, c_diag_wg_nofsamples_w);
wg_ctrl.phase <= TO_UVEC(wg_phase, c_diag_wg_phase_w);
p_mm : PROCESS
BEGIN
tb_end <= '0';
restart <= '0';
wg_mode <= c_diag_wg_mode_off;
---------------------------------------------------------------------------
-- >>> Single, repeat mode
wg_nof_samples <= c_wg_nof_samples;
-- >>> CALC mode
-- Cosinus with frequency Fs/2 (note sinus Fs/2 yields DC = 0)
-- wg_freq <= INTEGER(0.5 * c_freq_unit);
-- wg_phase <= INTEGER(90.0 * c_phase_unit);
-- Choosing 1.0*Fs to select Fs which is equivalent to DC, hence the DC value is then determined by phase
-- this also applies to 2.0, 3.0, 4.0 etc
-- this also applies to 2.0, 3.0, 4.0 etc
-- wg_freq <= INTEGER(1.0 * c_freq_unit);
-- wg_phase <= INTEGER(45.0 * c_phase_unit);
-- Sinus Fs/16
wg_freq <= INTEGER(0.0625 * c_freq_unit);
--wg_freq <= INTEGER(511.0/512.0 * c_freq_unit);
--wg_freq <= INTEGER(1.0/512.0 * c_freq_unit);
--wg_freq <= INTEGER(1.0); -- minimum value, yields Fs/c_freq_unit Hz sinus
wg_phase <= INTEGER(0.0 * c_phase_unit);
-- Sinus Fs/17
-- wg_freq <= INTEGER(1.0/17.0 * c_freq_unit);
-- wg_phase <= INTEGER(0.0 * c_phase_unit);
......@@ -147,13 +146,13 @@ BEGIN
wg_ampl <= INTEGER(1.0 * c_ampl_unit); -- yields amplitude of c_wg_full_scale
-- wg_ampl <= INTEGER(1.0/REAL(c_wg_full_scale) * c_ampl_unit); -- yields amplitude of 1
-- wg_ampl <= INTEGER(3.0/REAL(c_wg_full_scale) * c_ampl_unit); -- yields amplitude of 3
WAIT UNTIL rising_edge(clk); -- align to rising edge
WAIT FOR c_clk_period*200;
---------------------------------------------------------------------------
-- >>> Select the different modes
-- CALC mode
wg_mode <= c_diag_wg_mode_calc;
restart <= '1';
......@@ -165,14 +164,14 @@ BEGIN
restart <= '0';
WAIT FOR c_clk_period*3000;
--WAIT FOR 1 sec;
-- OFF mode
wg_mode <= c_diag_wg_mode_off;
restart <= '1';
WAIT FOR c_clk_period*1;
restart <= '0';
WAIT FOR c_clk_period*200;
-- SINGLE mode
wg_mode <= c_diag_wg_mode_single;
FOR I IN 0 TO 1 LOOP
......@@ -182,7 +181,7 @@ BEGIN
WAIT FOR c_clk_period*c_buf.nof_dat;
WAIT FOR c_clk_period*300;
END LOOP;
-- REPEAT mode
wg_mode <= c_diag_wg_mode_repeat;
restart <= '1';
......@@ -195,19 +194,19 @@ BEGIN
restart <= '0';
WAIT FOR c_clk_period*c_buf.nof_dat*5;
WAIT FOR c_clk_period*200;
-- OFF mode
wg_mode <= c_diag_wg_mode_off;
restart <= '1';
WAIT FOR c_clk_period*1;
restart <= '0';
WAIT FOR c_clk_period*200;
WAIT FOR c_clk_period*100;
tb_end <= '1';
WAIT;
END PROCESS;
-- Waveform buffer
u_buf : ENTITY common_lib.common_ram_crw_crw
GENERIC MAP (
......@@ -232,7 +231,7 @@ BEGIN
rd_val_a => OPEN,
rd_val_b => buf_rdval
);
-- Waveform generator
u_wg : ENTITY work.diag_wg
GENERIC MAP (
......@@ -253,13 +252,12 @@ BEGIN
buf_rden => buf_rden,
ctrl => wg_ctrl,
ctrl_act => wg_ctrl_act,
out_ovr => wg_ovr,
out_dat => wg_dat,
out_val => wg_val,
out_sync => wg_sync
);
END tb;
libraries/base/diag/tb/vhdl/tb_diag_wg_wideband.vhd
+ 34
− 53
View file @ ba49caa0
......@@ -19,7 +19,7 @@
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--------------------------------------------------------------------------------
LIBRARY IEEE, common_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
......@@ -52,50 +52,49 @@ ARCHITECTURE tb OF tb_diag_wg_wideband IS
CONSTANT c_clk_freq : NATURAL := 200; -- MHz
CONSTANT c_clk_period : TIME := (10**6 / c_clk_freq) * 1 ps;
-- Default WG settings
CONSTANT c_buf_nof_dat : NATURAL := 2**g_buf_addr_w;
CONSTANT c_wg_gain_w : NATURAL := 1; -- Normalized range [0 1> maps to fixed point range [0:2**c_diag_wg_ampl_w>
-- . use gain 2**0 = 1 to have fulle scale without clipping
-- . use gain 2**g_calc_gain_w > 1 to cause clipping
CONSTANT c_buf_full_scale : NATURAL := 2**(g_buf_dat_w-1)-1; -- The stored waveform range should also be [-c_buf_full_scale +c_buf_full_scale], so not including -c_buf_full_scale-1
CONSTANT c_wg_full_scale : NATURAL := 2**(g_wg_dat_w-1)-1;
CONSTANT c_ampl_norm : REAL := sel_a_b(g_wg_dat_w < g_buf_dat_w, REAL(c_wg_full_scale)/REAL(c_wg_full_scale+1), 1.0);
--CONSTANT c_ampl_norm : REAL := REAL(c_wg_full_scale)/REAL(c_wg_full_scale+1); -- Use this if g_wg_dat_w < g_buf_dat_w, to avoid clipping
--CONSTANT c_ampl_norm : REAL := 1.0; -- Use this if g_wg_dat_w = g_buf_dat_w, because the stored waveform range is already -+c_buf_full_scale
--CONSTANT c_ampl_norm : REAL := REAL(c_buf_full_scale)/REAL(c_buf_full_scale+1); -- No need to use this, because the stored waveform range is already -+c_buf_full_scale
CONSTANT c_freq_unit : REAL := c_diag_wg_freq_unit; -- ^= c_clk_freq = Fs (sample frequency), assuming one sinus waveform in the buffer
CONSTANT c_ampl_unit : REAL := c_diag_wg_ampl_unit*c_ampl_norm; -- ^= Full Scale range [-c_wg_full_scale +c_wg_full_scale] without clipping
CONSTANT c_phase_unit : REAL := c_diag_wg_phase_unit; -- ^= 1 degree
-- Wideband WG settings
CONSTANT c_sample_period : TIME := (10**6 / (c_clk_freq*g_wideband_factor)) * 1 ps;
TYPE t_buf_dat_arr IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(g_buf_dat_w-1 DOWNTO 0);
SIGNAL tb_end : STD_LOGIC;
SIGNAL rst : STD_LOGIC;
SIGNAL clk : STD_LOGIC := '1';
SIGNAL restart : STD_LOGIC;
SIGNAL wg_ctrl : t_diag_wg;
SIGNAL wg_ctrl_act : t_diag_wg;
SIGNAL wg_mode : NATURAL;
SIGNAL wg_freq : NATURAL;
SIGNAL wg_ampl : NATURAL;
SIGNAL wg_nof_samples : NATURAL;
SIGNAL wg_phase : NATURAL;
-- Wideband WG output is big endian, so first output sample in MSBit, MSData
SIGNAL out_ovr : STD_LOGIC_VECTOR(g_wideband_factor -1 DOWNTO 0);
SIGNAL out_dat : STD_LOGIC_VECTOR(g_wideband_factor*g_buf_dat_w-1 DOWNTO 0);
SIGNAL out_val : STD_LOGIC_VECTOR(g_wideband_factor -1 DOWNTO 0);
SIGNAL out_sync : STD_LOGIC_VECTOR(g_wideband_factor -1 DOWNTO 0);
SIGNAL wg_ovr : STD_LOGIC_VECTOR(0 TO g_wideband_factor-1);
SIGNAL wg_dat : t_buf_dat_arr(0 TO g_wideband_factor-1);
SIGNAL wg_val : STD_LOGIC_VECTOR(0 TO g_wideband_factor-1);
......@@ -107,47 +106,47 @@ ARCHITECTURE tb OF tb_diag_wg_wideband IS
SIGNAL sample_dat : STD_LOGIC_VECTOR(g_buf_dat_w-1 DOWNTO 0);
SIGNAL sample_val : STD_LOGIC;
SIGNAL sample_sync : STD_LOGIC;
BEGIN
rst <= '1', '0' AFTER c_clk_period/10;
clk <= NOT clk OR tb_end AFTER c_clk_period/2;
sample_clk <= NOT sample_clk OR tb_end AFTER c_sample_period/2;
wg_ctrl.mode <= TO_UVEC(wg_mode, c_diag_wg_mode_w);
wg_ctrl.freq <= TO_UVEC(wg_freq, c_diag_wg_freq_w);
wg_ctrl.ampl <= TO_UVEC(wg_ampl, c_diag_wg_ampl_w);
wg_ctrl.nof_samples <= TO_UVEC(wg_nof_samples, c_diag_wg_nofsamples_w);
wg_ctrl.phase <= TO_UVEC(wg_phase, c_diag_wg_phase_w);
p_mm : PROCESS
BEGIN
tb_end <= '0';
restart <= '0';
wg_mode <= c_diag_wg_mode_off;
---------------------------------------------------------------------------
-- >>> Single, repeat mode
wg_nof_samples <= c_buf_nof_dat; -- must be <= c_buf_nof_dat
-- >>> CALC mode
-- Cosinus with frequency Fs/2 (note sinus Fs/2 yields DC = 0)
-- wg_freq <= INTEGER(0.5 * c_freq_unit);
-- wg_phase <= INTEGER(90.0 * c_phase_unit);
-- Choosing 1.0*Fs to select Fs which is equivalent to DC, hence the DC value is then determined by phase
-- this also applies to 2.0, 3.0, 4.0 etc
-- this also applies to 2.0, 3.0, 4.0 etc
-- wg_freq <= INTEGER(1.0 * c_freq_unit);
-- wg_phase <= INTEGER(45.0 * c_phase_unit);
-- Sinus Fs/16
wg_freq <= INTEGER(0.0625 * c_freq_unit);
--wg_freq <= INTEGER(511.0/512.0 * c_freq_unit);
wg_freq <= INTEGER(1.0/512.0 * c_freq_unit);
--wg_freq <= INTEGER(1.0); -- minimum value, yields Fs/c_freq_unit Hz sinus
wg_phase <= INTEGER(0.0 * c_phase_unit);
-- Sinus Fs/17
-- wg_freq <= INTEGER(1.0/17.0 * c_freq_unit);
-- wg_phase <= INTEGER(0.0 * c_phase_unit);
......@@ -155,30 +154,18 @@ BEGIN
wg_ampl <= INTEGER(1.0 * c_ampl_unit); -- yields amplitude of c_wg_full_scale
-- wg_ampl <= INTEGER(1.0/REAL(c_wg_full_scale) * c_ampl_unit); -- yields amplitude of 1
-- wg_ampl <= INTEGER(3.0/REAL(c_wg_full_scale) * c_ampl_unit); -- yields amplitude of 3
WAIT FOR c_clk_period*10;
WAIT UNTIL rising_edge(clk); -- align to rising edge
WAIT FOR c_clk_period*200;
---------------------------------------------------------------------------
-- >>> Select the different modes
-- CALC mode
wg_mode <= c_diag_wg_mode_calc;
-- Verify that wg_ctrl_act does not change without restart
WAIT FOR c_clk_period*3;
ASSERT TO_UINT(wg_ctrl_act.mode) = c_diag_wg_mode_off REPORT "Wrong wg_ctrl_act mode before restart" SEVERITY ERROR;
restart <= '1';
WAIT FOR c_clk_period*1;
restart <= '0';
-- Verify that wg_ctrl_act updated after restart
WAIT FOR c_clk_period*3;
ASSERT TO_UINT(wg_ctrl_act.mode) = c_diag_wg_mode_calc REPORT "Wrong wg_ctrl_act mode after restart" SEVERITY ERROR;
WAIT FOR c_clk_period*3000;
restart <= '1';
WAIT FOR c_clk_period*1;
......@@ -188,11 +175,6 @@ BEGIN
-- OFF mode
wg_mode <= c_diag_wg_mode_off;
-- Verify that wg_ctrl_act updated after WG off
WAIT FOR c_clk_period*3;
ASSERT TO_UINT(wg_ctrl_act.mode) = c_diag_wg_mode_off REPORT "Wrong wg_ctrl_act mode after WG off" SEVERITY ERROR;
restart <= '1';
WAIT FOR c_clk_period*1;
restart <= '0';
......@@ -207,7 +189,7 @@ BEGIN
WAIT FOR c_clk_period*c_buf_nof_dat;
WAIT FOR c_clk_period*300;
END LOOP;
-- REPEAT mode
wg_mode <= c_diag_wg_mode_repeat;
restart <= '1';
......@@ -220,20 +202,20 @@ BEGIN
restart <= '0';
WAIT FOR c_clk_period*c_buf_nof_dat*5;
WAIT FOR c_clk_period*200;
-- OFF mode
wg_mode <= c_diag_wg_mode_off;
restart <= '1';
WAIT FOR c_clk_period*1;
restart <= '0';
WAIT FOR c_clk_period*200;
WAIT FOR c_clk_period*100;
tb_end <= '1';
WAIT;
END PROCESS;
u_wideband_wg : ENTITY work.diag_wg_wideband
GENERIC MAP (
-- Wideband parameters
......@@ -249,7 +231,7 @@ BEGIN
-- Memory-mapped clock domain
mm_rst => '0',
mm_clk => '0',
mm_wrdata => (OTHERS=>'0'),
mm_address => (OTHERS=>'0'),
mm_wr => '0',
......@@ -261,16 +243,15 @@ BEGIN
st_rst => rst,
st_clk => clk,
st_restart => restart,
st_ctrl => wg_ctrl,
st_ctrl_act => wg_ctrl_act,
out_ovr => out_ovr,
out_dat => out_dat,
out_val => out_val,
out_sync => out_sync
);
-- Map wideband WG out_* slv to wg_* arrays to ease interpretation in wave window
gen_wires : FOR I IN 0 TO g_wideband_factor-1 GENERATE
wg_ovr(I) <= out_ovr( g_wideband_factor-I-1);
......@@ -278,8 +259,8 @@ BEGIN
wg_val(I) <= out_val( g_wideband_factor-I-1);
wg_sync(I) <= out_sync( g_wideband_factor-I-1);
END GENERATE;
-- View WG output at the sample rate
-- View WG output at the sample rate
p_sample : PROCESS(sample_clk)
BEGIN
IF rising_edge(sample_clk) THEN
......@@ -294,6 +275,6 @@ BEGIN
sample_sync <= wg_sync(sample_cnt);
END IF;
END PROCESS;
END tb;
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