Added use of tc.read and tc.rerun to improve rerunning the test. Added BSN...

Added use of tc.read and tc.rerun to improve rerunning the test. Added BSN monitor logging for DB sosi.

boards/uniboard1/designs/unb1_reorder/tb/python/tc_unb1_reorder_seq.py

@@ -27,7 +27,11 @@ Description:
                |         |
              WR DDR    RD DDR
 Usage:
-
+  > simulate tb_unb1_reorder.vhd
+  > python tc_unb1_reorder_seq.py --sim --unb 0 --bn 3 --rep 2
+  to run the test again:
+  > python tc_unb1_reorder_seq.py --sim --unb 0 --bn 3 --rep 2 --read     # continue rx seq checking
+  > python tc_unb1_reorder_seq.py --sim --unb 0 --bn 3 --rep 2 --rerun    # restart rx seq checking
 """
 
 ###############################################################################
@@ -40,6 +44,7 @@ import pi_diag_data_buffer
 import pi_diag_rx_seq
 import pi_io_ddr
 import pi_ss_ss_wide
+import pi_bsn_monitor
 import mem_init_file
 
 from tools import *
@@ -77,55 +82,87 @@ if __name__ == "__main__":
     db = pi_diag_data_buffer.PiDiagDataBuffer(tc, io, nofStreams=c_nof_streams)
     tx_seq = pi_diag_tx_seq.PiDiagTxSeq(tc, io, nof_inst=c_nof_streams)
     rx_seq = pi_diag_rx_seq.PiDiagRxSeq(tc, io, nof_inst=c_nof_streams)
+
+    # BSN monitors
+    bsn_bg = 0   # bg_sosi_arr
+    bsn_wr = 1   # to_mem_sosi
+    bsn_rd = 2   # from_mem_sosi
+    bsn_db = 3   # db_sosi_arr
+    nof_bsn = 4
+
+    bsn = pi_bsn_monitor.PiBsnMonitor(tc, io, nofStreams=nof_bsn)
     
     # Create object for DDR register map
-    ddr_status = pi_io_ddr.PiIoDdr(tc, io, nof_inst = 1)
+    ddr_status = pi_io_ddr.PiIoDdr(tc, io, nof_inst=1)
     
     # Create subandselect instance for pre-transpose.   
     ss = pi_ss_ss_wide.PiSsSsWide (tc, io, c_wr_chunksize*c_rd_chunksize, c_nof_streams) 
     
     
-    ###############################################################################
-    #
-    # Create setting for the pre-transpose (subbandselect)
-    #
-    ###############################################################################
-    if c_ena_pre_transpose:
-        ss_list = []
-        for i in range(c_wr_chunksize):
-            for j in range(c_rd_chunksize):
-               ss_list.append(i + j*c_wr_chunksize)
-        ss.write_selects(ss_list)
-    
-    
     ################################################################################
-    # Test
+    # Wait for
+    ################################################################################
     
     # Wait for power up (reset release)
     io.wait_for_time(hw_time=0.01, sim_time=(1, 'us'))
     
-    # Wait for the DDR memory to become available    
+    # Wait for DDR memory available    
     do_until_eq(ddr_status.read_init_done, ms_retry=3000, val=1, s_timeout=3600)
 
-    # Control defaults
-    nof_mon = sel_a_b(tc.sim, 1, 2)
+    if tc.run:
+        ################################################################################
+        # Write initialisations
+        ################################################################################
+    
+        # Init pre-transpose reorder
+        if c_ena_pre_transpose:
+            ss_list = []
+            for i in range(c_wr_chunksize):
+                for j in range(c_rd_chunksize):
+                   ss_list.append(i + j*c_wr_chunksize)
+            ss.write_selects(ss_list)
+    
+        # Init rx seq
+        step_0 = 1
+        step_1 = c_wr_chunksize                                               #   176
+        step_2 = to_unsigned(-c_wr_chunksize*(c_rd_interval-1)+1, c_word_w)   # -2639
     
-    # Initialization
-    step_0 =  1
-    step_1 =  c_wr_chunksize                       #   176
-    step_2 = -c_wr_chunksize*(c_rd_interval-1)+1   # -2639
-
-    rx_seq.write_step_3(StepSize=step_2, vLevel=5)
-    rx_seq.write_step_2(StepSize=step_2, vLevel=5)
-    rx_seq.write_step_1(StepSize=step_1, vLevel=5)
-    rx_seq.write_step_0(StepSize=step_0, vLevel=5)
+        rx_seq.write_step_3(StepSize=step_2, vLevel=5)
+        rx_seq.write_step_2(StepSize=step_2, vLevel=5)
+        rx_seq.write_step_1(StepSize=step_1, vLevel=5)
+        rx_seq.write_step_0(StepSize=step_0, vLevel=5)
+        
+        # Init bg
+        bg.write_block_gen_settings(samplesPerPacket=c_wr_chunksize, blocksPerSync=16, gapSize=0, BSNInit=0)
+    
+        ################################################################################
+        # Block sequence start
+        ################################################################################
+        rx_seq.write_enable_cntr(vLevel=5)
+        tx_seq.write_enable_cntr(vLevel=5)
+        bg.write_enable()
+        
+    if tc.rerun:
+        # Restart Rx verification
+        rx_seq.write_disable(vLevel=5)
+        io.wait_for_time(hw_time=0.01, sim_time=(1, 'us'))
+        rx_seq.write_enable_cntr(vLevel=5)
+
+    if tc.read:
+        # Continue Rx verification
+        pass        
     
-    bg.write_block_gen_settings(samplesPerPacket=c_wr_chunksize, blocksPerSync=16, gapSize=0, BSNInit=0)
+    ################################################################################
+    # Monitor results
+    ################################################################################
+    
+    # Control defaults
+    nof_mon = sel_a_b(tc.sim, 1, 2)
 
-    # Block sequence start
-    rx_seq.write_enable_cntr(vLevel=5)
-    tx_seq.write_enable_cntr(vLevel=5)
-    bg.write_enable()
+    # Tx sequence monitor
+    for mon in range(nof_mon):
+        io.wait_for_time(hw_time=0.01, sim_time=(1, 'us'))
+        tx_seq.read_cnt(vLevel=5)
 
     # Wait for rx data
     do_until_gt(rx_seq.read_cnt, ms_retry=3000, val=0, s_timeout=3600)
@@ -134,22 +171,20 @@ if __name__ == "__main__":
         tc.append_log(5, '')
         tc.append_log(3, '>>> Rep-%d' % rep)
         
-        # Tx sequence monitor
-        for mon in range(nof_mon):
-            io.wait_for_time(hw_time=0.01, sim_time=(1, 'us'))
-            tx_seq.read_cnt(vLevel=5)
-
-        # Rx sequence monitor
+        # Monitor
         for mon in range(nof_mon):
             io.wait_for_time(hw_time=0.01, sim_time=(1, 'us'))
             rx_seq.read_cnt(vLevel=5)
         
-        io.wait_for_time(hw_time=1, sim_time=(10, 'us'))
+        bsn.read_bsn_monitor(streamNr=bsn_db, bsnInit=0, vLevel=5)
 
+        # Rx result
         rx_seq.read_result(vLevel=5)
-
         if tc.get_result() != "PASSED":
             break
+
+        # Wait some interval        
+        io.wait_for_time(hw_time=1, sim_time=(10, 'us'))
         
     
     # End