Added trigger_en OUT port for convenience.

libraries/base/common/src/vhdl/mms_common_variable_delay.vhd

@@ -44,12 +44,13 @@ ENTITY mms_common_variable_delay IS
 
     delay           : IN  NATURAL := 0;
     trigger         : IN  STD_LOGIC := '0';
+    trigger_en      : OUT STD_LOGIC;
     trigger_dly     : OUT STD_LOGIC
   );
 END mms_common_variable_delay;
 
 
-ARCHITECTURE rtl OF mms_common_variable_delay IS
+ARCHITECTURE str OF mms_common_variable_delay IS
   
   CONSTANT c_enable_mem_reg : t_c_mem := (c_mem_reg_rd_latency, 1, 1, 1, '0');
   
@@ -58,18 +59,20 @@ ARCHITECTURE rtl OF mms_common_variable_delay IS
   SIGNAL enable : STD_LOGIC := '0';
 
 BEGIN
-  enable  <= sl(enable_reg);
+
+  trigger_en <= sl(enable_reg);  -- also provide enable as OUT
+  enable <= sl(enable_reg);
   
   -- device under test
-  u_dut : ENTITY work.common_variable_delay
+  u_common_variable_delay : ENTITY work.common_variable_delay
   PORT MAP (
-    rst     => dp_rst,
-    clk     => dp_clk,
+    rst       => dp_rst,
+    clk       => dp_clk,
 
-    delay   => delay,
-    enable  => enable,
-    in_val  => trigger,
-    out_val => trigger_dly
+    delay     => delay,
+    enable    => enable,
+    in_pulse  => trigger,
+    out_pulse => trigger_dly
   );
 
   u_mms_common_reg : ENTITY work.mms_common_reg
@@ -89,4 +92,4 @@ BEGIN
     out_reg        => enable_reg   
   );
 
-END;
+END;
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