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Commit b861763b authored by Eric Kooistra's avatar Eric Kooistra
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Corrected using c_mm_file_reg_bsn_sync_scheduler_xsub. Shortened the sim speed... 

Corrected using c_mm_file_reg_bsn_sync_scheduler_xsub. Shortened the sim speed by starting PPS after BSN source is ready for it.
parent 1a1374f8
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1 merge request!184Corrected using c_mm_file_reg_bsn_sync_scheduler_xsub. Shortened the sim speed...
Pipeline #23213 passed
Stage: simulation
Stage: synthesis
Stage: hardware
Pipeline: sdptr

#23214

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    applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/tb_lofar2_unb2b_sdp_station_xsub_one.vhd
    + 11
    − 11
    View file @ b861763b
    ......@@ -42,6 +42,7 @@
    -- > as 7 # default
    -- > as 12 # for detailed debugging
    -- > run -a
    -- Takes about 40 m
    --
    -------------------------------------------------------------------------------
    LIBRARY IEEE, common_lib, unb2b_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib, lofar2_sdp_lib, wpfb_lib, lofar2_unb2b_sdp_station_lib;
    ......@@ -77,7 +78,7 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_sdp_station_xsub_one IS
    CONSTANT c_tb_clk_period : TIME := 100 ps; -- use fast tb_clk to speed up M&C
    CONSTANT c_nof_block_per_sync : NATURAL := 32;
    CONSTANT c_nof_block_per_sync : NATURAL := 24;
    CONSTANT c_nof_clk_per_sync : NATURAL := c_nof_block_per_sync*c_sdp_N_fft;
    CONSTANT c_pps_period : NATURAL := c_nof_clk_per_sync;
    CONSTANT c_wpfb_sim : t_wpfb := func_wpfb_set_nof_block_per_sync(c_sdp_wpfb_subbands, c_nof_block_per_sync);
    ......@@ -132,7 +133,7 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_sdp_station_xsub_one IS
    SIGNAL ext_clk : STD_LOGIC := '0';
    SIGNAL pps : STD_LOGIC := '0';
    SIGNAL ext_pps : STD_LOGIC := '0';
    SIGNAL pps_rst : STD_LOGIC := '0';
    SIGNAL pps_rst : STD_LOGIC := '1';
    SIGNAL WDI : STD_LOGIC;
    SIGNAL INTA : STD_LOGIC;
    ......@@ -242,9 +243,6 @@ BEGIN
    BEGIN
    -- Wait for DUT power up after reset
    WAIT FOR 1 us;
    -- wait for pps
    proc_common_wait_until_hi_lo(ext_clk, ext_pps);
    ----------------------------------------------------------------------------
    -- Enable BSN
    ......@@ -253,7 +251,11 @@ BEGIN
    mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 2, 0, tb_clk); -- Init BSN = 0
    mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 1, c_nof_clk_per_sync, tb_clk); -- nof_block_per_sync
    mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 0, 16#00000003#, tb_clk); -- Enable BSN at PPS
    -- Release PPS pulser, to get first PPS now and to start BSN source
    WAIT FOR 1 us;
    pps_rst <= '0';
    ----------------------------------------------------------------------------
    -- Crosslets Info
    ----------------------------------------------------------------------------
    ......@@ -285,6 +287,7 @@ BEGIN
    ASSERT v_bsn <= c_bsn_start_wg REPORT "Too late to start WG: " & int_to_str(v_bsn) & " > " & int_to_str(c_bsn_start_wg) SEVERITY ERROR;
    mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 0, c_bsn_start_wg, tb_clk); -- first write low then high part
    mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 1, 0, tb_clk); -- assume v_bsn < 2**31-1
    -- bsn_scheduler_xsub
    mmf_mm_bus_wr(c_mm_file_reg_bsn_sync_scheduler_xsub, 1, c_ctrl_interval_size, tb_clk); -- Interval size
    mmf_mm_bus_wr(c_mm_file_reg_bsn_sync_scheduler_xsub, 2, c_bsn_start_wg, tb_clk); -- first write low then high part
    ......@@ -292,9 +295,8 @@ BEGIN
    mmf_mm_bus_wr(c_mm_file_reg_bsn_sync_scheduler_xsub, 0, 1, tb_clk); -- enable
    -- Wait for enough WG data and start of sync interval
    mmf_mm_wait_until_value(c_mm_file_reg_bsn_scheduler_wg, 0, -- read BSN low
    "UNSIGNED", rd_data, ">=", c_nof_block_per_sync * 3, -- this is the wait until condition
    mmf_mm_wait_until_value(c_mm_file_reg_bsn_scheduler_wg, 0, -- read BSN low
    "UNSIGNED", rd_data, ">=", c_nof_block_per_sync * 2, -- this is the wait until condition
    c_sdp_T_sub, tb_clk);
    ---------------------------------------------------------------------------
    ......@@ -313,8 +315,6 @@ BEGIN
    xsub_stats_arr(v_B)(63 DOWNTO 32) <= rd_data;
    END IF;
    END LOOP;
    proc_common_wait_some_cycles(tb_clk, 1);
    ---------------------------------------------------------------------------
    ......
    applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/tb_lofar2_unb2b_sdp_station_xsub_one_xst_offload.vhd
    + 8
    − 2
    View file @ b861763b
    ......@@ -34,7 +34,8 @@
    -- Usage:
    -- > as 7 # default
    -- > as 12 # for detailed debugging
    -- > run -a
    -- > run -a
    -- Takes about 10 m
    --
    -------------------------------------------------------------------------------
    LIBRARY IEEE, common_lib, unb2b_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib, lofar2_sdp_lib, wpfb_lib, lofar2_unb2b_sdp_station_lib, eth_lib;
    ......@@ -100,7 +101,7 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_sdp_station_xsub_one_xst_offload IS
    SIGNAL ext_clk : STD_LOGIC := '0';
    SIGNAL pps : STD_LOGIC := '0';
    SIGNAL ext_pps : STD_LOGIC := '0';
    SIGNAL pps_rst : STD_LOGIC := '0';
    SIGNAL pps_rst : STD_LOGIC := '1';
    SIGNAL WDI : STD_LOGIC;
    SIGNAL INTA : STD_LOGIC;
    ......@@ -216,6 +217,10 @@ BEGIN
    mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 1, c_nof_clk_per_sync, tb_clk); -- nof_block_per_sync
    mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 0, 16#00000001#, tb_clk); -- Enable BSN immediately
    -- Release PPS pulser, to get first PPS now and to start BSN source
    WAIT FOR 1 us;
    pps_rst <= '0';
    ----------------------------------------------------------------------------
    -- Enable xsub
    ----------------------------------------------------------------------------
    ......@@ -223,6 +228,7 @@ BEGIN
    mmf_mm_bus_wr(c_mm_file_reg_bsn_sync_scheduler_xsub, 2, c_nof_block_per_sync, tb_clk); -- first write bsn low then bsn high part
    mmf_mm_bus_wr(c_mm_file_reg_bsn_sync_scheduler_xsub, 3, 0, tb_clk); -- bsn high, assume v_bsn < 2**31-1
    mmf_mm_bus_wr(c_mm_file_reg_bsn_sync_scheduler_xsub, 0, 1, tb_clk); -- enable
    ----------------------------------------------------------------------------
    -- Offload enable
    ----------------------------------------------------------------------------
    ......
    applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/tb_lofar2_unb2c_sdp_station_xsub_one.vhd
    + 23
    − 20
    View file @ b861763b
    ......@@ -42,6 +42,7 @@
    -- > as 7 # default
    -- > as 12 # for detailed debugging
    -- > run -a
    -- Takes about 40 m
    --
    -------------------------------------------------------------------------------
    LIBRARY IEEE, common_lib, unb2c_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib, lofar2_sdp_lib, wpfb_lib, lofar2_unb2c_sdp_station_lib;
    ......@@ -77,11 +78,12 @@ ARCHITECTURE tb OF tb_lofar2_unb2c_sdp_station_xsub_one IS
    CONSTANT c_tb_clk_period : TIME := 100 ps; -- use fast tb_clk to speed up M&C
    CONSTANT c_nof_block_per_sync : NATURAL := 32;
    CONSTANT c_nof_block_per_sync : NATURAL := 24;
    CONSTANT c_nof_clk_per_sync : NATURAL := c_nof_block_per_sync*c_sdp_N_fft;
    CONSTANT c_pps_period : NATURAL := c_nof_clk_per_sync;
    CONSTANT c_wpfb_sim : t_wpfb := func_wpfb_set_nof_block_per_sync(c_sdp_wpfb_subbands, c_nof_block_per_sync);
    CONSTANT c_ctrl_interval_size : NATURAL := c_nof_clk_per_sync;
    CONSTANT c_percentage : REAL := 0.05; -- percentage that actual value may differ from expected value
    CONSTANT c_lo_factor : REAL := 1.0 - c_percentage; -- lower boundary
    CONSTANT c_hi_factor : REAL := 1.0 + c_percentage; -- higher boundary
    ......@@ -106,13 +108,13 @@ ARCHITECTURE tb OF tb_lofar2_unb2c_sdp_station_xsub_one IS
    TYPE t_real_arr IS ARRAY (INTEGER RANGE <>) OF REAL;
    -- MM
    CONSTANT c_mm_file_reg_bsn_source_v2 : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SOURCE_V2";
    CONSTANT c_mm_file_reg_bsn_scheduler_wg : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SCHEDULER";
    CONSTANT c_mm_file_reg_diag_wg : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_WG";
    CONSTANT c_mm_file_ram_st_sst : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "RAM_ST_SST";
    CONSTANT c_mm_file_reg_crosslets_info : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_CROSSLETS_INFO";
    CONSTANT c_mm_file_reg_bsn_scheduler_xsub : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SCHEDULER_XSUB";
    CONSTANT c_mm_file_ram_st_xsq : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "RAM_ST_XSQ";
    CONSTANT c_mm_file_reg_bsn_source_v2 : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SOURCE_V2";
    CONSTANT c_mm_file_reg_bsn_scheduler_wg : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SCHEDULER";
    CONSTANT c_mm_file_reg_diag_wg : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_WG";
    CONSTANT c_mm_file_ram_st_sst : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "RAM_ST_SST";
    CONSTANT c_mm_file_reg_crosslets_info : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_CROSSLETS_INFO";
    CONSTANT c_mm_file_reg_bsn_sync_scheduler_xsub : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SYNC_SCHEDULER_XSUB";
    CONSTANT c_mm_file_ram_st_xsq : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "RAM_ST_XSQ";
    -- Tb
    SIGNAL tb_end : STD_LOGIC := '0';
    ......@@ -131,7 +133,7 @@ ARCHITECTURE tb OF tb_lofar2_unb2c_sdp_station_xsub_one IS
    SIGNAL ext_clk : STD_LOGIC := '0';
    SIGNAL pps : STD_LOGIC := '0';
    SIGNAL ext_pps : STD_LOGIC := '0';
    SIGNAL pps_rst : STD_LOGIC := '0';
    SIGNAL pps_rst : STD_LOGIC := '1';
    SIGNAL WDI : STD_LOGIC;
    SIGNAL INTA : STD_LOGIC;
    ......@@ -225,9 +227,6 @@ BEGIN
    -- Wait for DUT power up after reset
    WAIT FOR 1 us;
    -- wait for pps
    proc_common_wait_until_hi_lo(ext_clk, ext_pps);
    ----------------------------------------------------------------------------
    -- Enable BSN
    ----------------------------------------------------------------------------
    ......@@ -236,6 +235,10 @@ BEGIN
    mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 1, c_nof_clk_per_sync, tb_clk); -- nof_block_per_sync
    mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 0, 16#00000003#, tb_clk); -- Enable BSN at PPS
    -- Release PPS pulser, to get first PPS now and to start BSN source
    WAIT FOR 1 us;
    pps_rst <= '0';
    ----------------------------------------------------------------------------
    -- Crosslets Info
    ----------------------------------------------------------------------------
    ......@@ -267,14 +270,16 @@ BEGIN
    ASSERT v_bsn <= c_bsn_start_wg REPORT "Too late to start WG: " & int_to_str(v_bsn) & " > " & int_to_str(c_bsn_start_wg) SEVERITY ERROR;
    mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 0, c_bsn_start_wg, tb_clk); -- first write low then high part
    mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 1, 0, tb_clk); -- assume v_bsn < 2**31-1
    -- bsn_scheduler_xsub
    mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_xsub, 0, c_bsn_start_wg, tb_clk); -- first write low then high part
    mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_xsub, 1, 0, tb_clk); -- assume v_bsn < 2**31-1
    mmf_mm_bus_wr(c_mm_file_reg_bsn_sync_scheduler_xsub, 1, c_ctrl_interval_size, tb_clk); -- Interval size
    mmf_mm_bus_wr(c_mm_file_reg_bsn_sync_scheduler_xsub, 2, c_bsn_start_wg, tb_clk); -- first write low then high part
    mmf_mm_bus_wr(c_mm_file_reg_bsn_sync_scheduler_xsub, 3, 0, tb_clk); -- assume v_bsn < 2**31-1
    mmf_mm_bus_wr(c_mm_file_reg_bsn_sync_scheduler_xsub, 0, 1, tb_clk); -- enable
    -- Wait for enough WG data and start of sync interval
    mmf_mm_wait_until_value(c_mm_file_reg_bsn_scheduler_wg, 0, -- read BSN low
    "UNSIGNED", rd_data, ">=", c_nof_block_per_sync * 3, -- this is the wait until condition
    mmf_mm_wait_until_value(c_mm_file_reg_bsn_scheduler_wg, 0, -- read BSN low
    "UNSIGNED", rd_data, ">=", c_nof_block_per_sync * 2, -- this is the wait until condition
    c_sdp_T_sub, tb_clk);
    ---------------------------------------------------------------------------
    ......@@ -293,8 +298,6 @@ BEGIN
    xsub_stats_arr(v_B)(63 DOWNTO 32) <= rd_data;
    END IF;
    END LOOP;
    proc_common_wait_some_cycles(tb_clk, 1);
    ---------------------------------------------------------------------------
    ......
    applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/tb_lofar2_unb2c_sdp_station_xsub_one_xst_offload.vhd
    + 18
    − 10
    View file @ b861763b
    ......@@ -35,6 +35,7 @@
    -- > as 7 # default
    -- > as 12 # for detailed debugging
    -- > run -a
    -- Takes about 10 m
    --
    -------------------------------------------------------------------------------
    LIBRARY IEEE, common_lib, unb2c_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib, lofar2_sdp_lib, wpfb_lib, lofar2_unb2c_sdp_station_lib, eth_lib;
    ......@@ -58,9 +59,9 @@ END tb_lofar2_unb2c_sdp_station_xsub_one_xst_offload;
    ARCHITECTURE tb OF tb_lofar2_unb2c_sdp_station_xsub_one_xst_offload IS
    CONSTANT c_sim : BOOLEAN := TRUE;
    CONSTANT c_unb_nr : NATURAL := 0; -- UniBoard 0
    CONSTANT c_node_nr : NATURAL := 0;
    CONSTANT c_id : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
    CONSTANT c_unb_nr : NATURAL := 2;
    CONSTANT c_node_nr : NATURAL := 1;
    CONSTANT c_id : STD_LOGIC_VECTOR(7 DOWNTO 0) := TO_UVEC(c_unb_nr * 4 + c_node_nr, 8); -- c_unb2c_board_nof_node = 4, c_unb2c_board_aux.id_w = 8
    CONSTANT c_version : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
    CONSTANT c_fw_version : t_unb2c_board_fw_version := (1, 0);
    ......@@ -74,11 +75,12 @@ ARCHITECTURE tb OF tb_lofar2_unb2c_sdp_station_xsub_one_xst_offload IS
    CONSTANT c_nof_clk_per_sync : NATURAL := c_nof_block_per_sync*c_sdp_N_fft;
    CONSTANT c_pps_period : NATURAL := c_nof_clk_per_sync;
    CONSTANT c_wpfb_sim : t_wpfb := func_wpfb_set_nof_block_per_sync(c_sdp_wpfb_subbands, c_nof_block_per_sync);
    CONSTANT c_ctrl_interval_size : NATURAL := c_nof_clk_per_sync;
    -- MM
    CONSTANT c_mm_file_reg_bsn_source_v2 : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SOURCE_V2";
    CONSTANT c_mm_file_reg_stat_enable_xst : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_STAT_ENABLE_XST";
    CONSTANT c_mm_file_reg_bsn_scheduler_xsub : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SCHEDULER_XSUB";
    CONSTANT c_mm_file_reg_bsn_source_v2 : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SOURCE_V2";
    CONSTANT c_mm_file_reg_stat_enable_xst : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_STAT_ENABLE_XST";
    CONSTANT c_mm_file_reg_bsn_sync_scheduler_xsub : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SYNC_SCHEDULER_XSUB";
    -- Tb
    SIGNAL tb_end : STD_LOGIC := '0';
    ......@@ -99,7 +101,7 @@ ARCHITECTURE tb OF tb_lofar2_unb2c_sdp_station_xsub_one_xst_offload IS
    SIGNAL ext_clk : STD_LOGIC := '0';
    SIGNAL pps : STD_LOGIC := '0';
    SIGNAL ext_pps : STD_LOGIC := '0';
    SIGNAL pps_rst : STD_LOGIC := '0';
    SIGNAL pps_rst : STD_LOGIC := '1';
    SIGNAL WDI : STD_LOGIC;
    SIGNAL INTA : STD_LOGIC;
    ......@@ -197,12 +199,18 @@ BEGIN
    mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 1, c_nof_clk_per_sync, tb_clk); -- nof_block_per_sync
    mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 0, 16#00000001#, tb_clk); -- Enable BSN immediately
    -- Release PPS pulser, to get first PPS now and to start BSN source
    WAIT FOR 1 us;
    pps_rst <= '0';
    ----------------------------------------------------------------------------
    -- Enable xsub
    ----------------------------------------------------------------------------
    mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_xsub, 0, 1, tb_clk); -- first write low then high part
    mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_xsub, 1, 0, tb_clk); -- assume v_bsn < 2**31-1
    mmf_mm_bus_wr(c_mm_file_reg_bsn_sync_scheduler_xsub, 1, c_ctrl_interval_size, tb_clk); -- Interval size
    mmf_mm_bus_wr(c_mm_file_reg_bsn_sync_scheduler_xsub, 2, c_nof_block_per_sync, tb_clk); -- first write bsn low then bsn high part
    mmf_mm_bus_wr(c_mm_file_reg_bsn_sync_scheduler_xsub, 3, 0, tb_clk); -- bsn high, assume v_bsn < 2**31-1
    mmf_mm_bus_wr(c_mm_file_reg_bsn_sync_scheduler_xsub, 0, 1, tb_clk); -- enable
    ----------------------------------------------------------------------------
    -- Offload enable
    ----------------------------------------------------------------------------
    ......
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