Added modules from digital receiver DSP library into RadioHDL structure

Modules included are:
library common_OA, used by other modules
fft_radix_n	Generic serial wide FFT with 100% multiplier efficiency. 
 		Currently supported radix2 and radix4, radix5 in progress
polyfilt	Overlapping wide polyphase filterbank 
test_generator	Test signal generator. Generates 2 tones, a PR Gaussian noise and a pulse comb

libraries/dig_receiver/common_OA/hdllib.cfg

+hdl_lib_name = common_OA
+hdl_library_clause_name = common_OA_lib
+hdl_lib_uses_synth = technology common
+hdl_lib_uses_sim = 
+
+hdl_lib_technology = 
+
+build_dir_sim = $HDL_BUILD_DIR
+build_dir_synth = $HDL_BUILD_DIR
+
+synth_files =
+    $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/common_OA/src/vhdl/common_delay.vhd
+    $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/common_OA/src/vhdl/common_delay_sl.vhd
+    $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/common_OA/src/vhdl/common_pulse_delay.vhd
+    $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/common_OA/src/vhdl/common_ram_wdrd.vhd
+    $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/common_OA/src/vhdl/common_ram_wsrs.vhd
+    $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/common_OA/src/vhdl/TotPowIntegrator.vhd
+
+test_bench_files = 
+

libraries/dig_receiver/fft_module_n/hdllib.cfg

+hdl_lib_name = fft_module_n
+hdl_library_clause_name = fft_module_n_lib
+hdl_lib_uses_synth = technology common common_OA
+hdl_lib_uses_sim = 
+
+hdl_lib_technology = 
+
+build_dir_sim = $HDL_BUILD_DIR
+build_dir_synth = $HDL_BUILD_DIR
+
+synth_files =
+    $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/fft/src/vhdl/fft_pkg.vhd
+    $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/fft/src/vhdl/multadd.vhd
+    $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/fft/src/vhdl/fft_bf.vhd
+    $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/fft/src/vhdl/fft_cm.vhd
+    $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/fft/src/vhdl/twiddle_rom.vhd
+    $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/fft/src/vhdl/twiddle_mem.vhd
+    $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/fft/src/vhdl/common_delay_cmplx.vhd
+    $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/fft/src/vhdl/shift_radix_n.vhd
+    $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/fft/src/vhdl/fft_stage_0.vhd
+    $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/fft/src/vhdl/fft_stage_1.vhd
+    $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/fft/src/vhdl/fft_stage_n.vhd
+    $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/fft/src/vhdl/fft_module2.vhd
+    $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/fft/src/vhdl/bitrev.vhd
+    $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/fft/src/vhdl/fft4_twiddle.vhd
+    $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/fft/src/vhdl/fft4_bf.vhd
+    $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/fft/src/vhdl/fft4_stage_0.vhd
+    $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/fft/src/vhdl/fft4_stage_n.vhd
+    $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/fft/src/vhdl/fft_module4.vhd
+    $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/fft/src/vhdl/fft8_bf.vhd
+    $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/fft/src/vhdl/c2r_chain.vhd
+    $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/fft/src/vhdl/cmplx2real.vhd
+    $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/fft/src/vhdl/real_fft_16.vhd
+    $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/fft/src/vhdl/real_fft_16_main.vhd
+    $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/fft/src/vhdl/real_fft_4.vhd
+    $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/fft/src/vhdl/real_fft_4_main.vhd
+    $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/fft/src/vhdl/real_fft_8.vhd
+    $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/fft/src/vhdl/real_fft_8_main.vhd
+    $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/fft/src/vhdl/real_fft_main.vhd
+    $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/fft/src/vhdl/reorder_radix_n.vhd
+    $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/fft/src/vhdl/bitrev_mod4.vhd
+    $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/fft/src/vhdl/winograd5_serial.vhd
+    
+test_bench_files = 
+    $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/fft/src/vhdl/sims/dds_4.vhd
+    $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/fft/src/vhdl/sims/tb_real_fft8.vhd
+    $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/fft/src/vhdl/sims/tb_fftmod4_dav.vhd
+    $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/fft/src/vhdl/sims/tb_real_fft.vhd
+    $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/fft/src/vhdl/sims/tb_winograd5.vhd
+

libraries/dig_receiver/polyfilt/hdllib.cfg

+hdl_lib_name = polyfilt
+hdl_library_clause_name = polyfilt_lib
+hdl_lib_uses_synth = technology common common_OA fft_module_n
+hdl_lib_uses_sim = 
+
+hdl_lib_technology = 
+
+build_dir_sim = $HDL_BUILD_DIR
+build_dir_synth = $HDL_BUILD_DIR
+
+synth_files =
+  $SVN/UniBoard_FP7/Digital_Receiver/trunk/Firmware/modules_HDL/polyfilt/src/vhdl/channelizer_pfb_16.vhd
+  $SVN/UniBoard_FP7/Digital_Receiver/trunk/Firmware/modules_HDL/polyfilt/src/vhdl/channelizer_pfb_4.vhd
+  $SVN/UniBoard_FP7/Digital_Receiver/trunk/Firmware/modules_HDL/polyfilt/src/vhdl/channelizer_pfb_8.vhd
+  $SVN/UniBoard_FP7/Digital_Receiver/trunk/Firmware/modules_HDL/polyfilt/src/vhdl/channelizer_pfb.vhd
+  $SVN/UniBoard_FP7/Digital_Receiver/trunk/Firmware/modules_HDL/polyfilt/src/vhdl/filt_27_1024.vhd
+  $SVN/UniBoard_FP7/Digital_Receiver/trunk/Firmware/modules_HDL/polyfilt/src/vhdl/filt_28_1024.vhd
+  $SVN/UniBoard_FP7/Digital_Receiver/trunk/Firmware/modules_HDL/polyfilt/src/vhdl/frequency_rotate.vhd
+  $SVN/UniBoard_FP7/Digital_Receiver/trunk/Firmware/modules_HDL/polyfilt/src/vhdl/poly_27_1024.vhd
+  $SVN/UniBoard_FP7/Digital_Receiver/trunk/Firmware/modules_HDL/polyfilt/src/vhdl/poly_delay.vhd
+  $SVN/UniBoard_FP7/Digital_Receiver/trunk/Firmware/modules_HDL/polyfilt/src/vhdl/poly_filter_main.vhd
+  $SVN/UniBoard_FP7/Digital_Receiver/trunk/Firmware/modules_HDL/polyfilt/src/vhdl/poly_filt_tb.vhd
+  $SVN/UniBoard_FP7/Digital_Receiver/trunk/Firmware/modules_HDL/polyfilt/src/vhdl/poly_filt.vhd
+  $SVN/UniBoard_FP7/Digital_Receiver/trunk/Firmware/modules_HDL/polyfilt/src/vhdl/poly_rom.vhd
+  $SVN/UniBoard_FP7/Digital_Receiver/trunk/Firmware/modules_HDL/polyfilt/src/vhdl/rate_change.vhd
+
+test_bench_files =
+

libraries/dig_receiver/test_generator/hdllib.cfg

+hdl_lib_name = test_generator
+hdl_library_clause_name = test_generator_lib
+hdl_lib_uses_synth = common mm dp diag axi4
+hdl_lib_uses_sim = 
+
+hdl_lib_technology = 
+
+build_dir_sim = $HDL_BUILD_DIR
+build_dir_synth = $HDL_BUILD_DIR
+
+synth_files =
+    $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/test_generator/src/vhdl/cal_pulse.vhd
+    $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/test_generator/src/vhdl/xorshift_RNG.vhd
+    $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/test_generator/src/vhdl/WNG.vhd
+    $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/test_generator/src/vhdl/samp_add.vhd
+    $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/test_generator/src/vhdl/dds_n.vhd
+    $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/test_generator/src/vhdl/test_generator_axi4_if.vhd
+    $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/test_generator/src/vhdl/test_generator_axi4.vhd
+    
+test_bench_files = 
+    $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/test_generator/src/vhdl/tb_test_generator.vhd