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Commit b75f28ed authored by Eric Kooistra's avatar Eric Kooistra
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Added nw_10GbE/nw_10GbE_unb2legacy peripheral.

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2 merge requests!100Removed text for XSub that is now written in Confluence Subband correlator...,!73Resolve L2SDP-240
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applications/lofar2/designs/lofar2_unb2b_beamformer/lofar2_unb2b_beamformer.fpga.yaml
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......@@ -259,3 +259,8 @@ peripherals:
peripheral_group: bst
slave_port_names:
- REG_STAT_HDR_INFO_BST
- peripheral_name: nw_10GbE/nw_10GbE_unb2legacy
slave_port_names:
- REG_NW_10GBE_MAC
libraries/io/nw_10GbE/nw_10GbE.peripheral.yaml 0 → 100644
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schema_name: args
schema_version: 1.0
schema_type: peripheral
hdl_library_name: nw_10GbE
hdl_library_description: "Network peripherals for 10GbE."
peripherals:
- peripheral_name: nw_10GbE_unb2legacy # pi_nw_10GbE_unb2legacy.py.py
peripheral_description: |
"M&C of Intel Low Latency (LL) 10GbE MAC, see [1]
The LL 10GbE MAC is used with the legacy address map option of the old 10GbE MAC, see [2], this implies:
. Some registers have a different address offset in [1] and [2]
. The 36 bit registers are stored at word 0 = [31:0] and word 1 = [3:0] = [35:32] in [1], but in [2]
they are stored with their 4 most significant bits first and their 32 least significant bits last, so
with word 0 = [3:0] = [35:32] and word 1 = [31:0].
Here the address map and 36 bit word order from [2] are used.
[1] LL 10GbE MAC, https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_32b_10g_ethernet_mac.pdf
[2] Legacy 10GbE MAC, https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/10gbps_mac.pdf
"
slave_ports:
# MM port for reg_mac_mosi = mac_mosi in nw_10GbE.vhd / tr_10GbE.vhd / tech_eth_10g.vhd / tech_eth_10g_arria10_e1sg.vhd
# Use nw_10GbE_word_to_byte_address.py to derive the byte addresses from the word addresses
- slave_name: REG_NW_10GBE_MAC
slave_type: REG
slave_description: "MAC registers"
fields:
- - {field_name: rx_transfer_control, width: 1, access_mode: RW, address_offset: 0x0000 } # = 0x0000
- - {field_name: rx_transfer_status, width: 1, access_mode: RO, address_offset: 0x0004 } # = 0x0001
- - {field_name: rx_padcrc_control, width: 2, access_mode: RW, address_offset: 0x0100 } # = 0x0040
- - {field_name: rx_crccheck_control, width: 2, access_mode: RW, address_offset: 0x0200 } # = 0x0080
- - {field_name: rx_pktovrflow_error, width: 32, access_mode: RO, address_offset: 0x0300, radix_width: 36 } # = 0x00C0
- - {field_name: rx_pktovrflow_etherStatsDropEvents, width: 32, access_mode: RO, address_offset: 0x0308, radix_width: 36 } # = 0x00C2
- - {field_name: rx_lane_decoder_preamble_control, width: 1, access_mode: RW, address_offset: 0x0400 } # = 0x0100
- - {field_name: rx_preamble_inserter_control, width: 1, access_mode: RW, address_offset: 0x0500 } # = 0x0140
- - {field_name: rx_frame_control, width: 20, access_mode: RW, address_offset: 0x2000 } # = 0x0800
- - {field_name: rx_frame_maxlength, width: 16, access_mode: RW, address_offset: 0x2004 } # = 0x0801
- - {field_name: rx_frame_addr0, width: 16, access_mode: RW, address_offset: 0x2008 } # = 0x0802
- - {field_name: rx_frame_addr1, width: 16, access_mode: RW, address_offset: 0x200c } # = 0x0803
- - {field_name: rx_frame_spaddr0_0, width: 16, access_mode: RW, address_offset: 0x2010 } # = 0x0804
- - {field_name: rx_frame_spaddr0_1, width: 16, access_mode: RW, address_offset: 0x2014 } # = 0x0805
- - {field_name: rx_frame_spaddr1_0, width: 16, access_mode: RW, address_offset: 0x2018 } # = 0x0806
- - {field_name: rx_frame_spaddr1_1, width: 16, access_mode: RW, address_offset: 0x201c } # = 0x0807
- - {field_name: rx_frame_spaddr2_0, width: 16, access_mode: RW, address_offset: 0x2020 } # = 0x0808
- - {field_name: rx_frame_spaddr2_1, width: 16, access_mode: RW, address_offset: 0x2024 } # = 0x0809
- - {field_name: rx_frame_spaddr3_0, width: 16, access_mode: RW, address_offset: 0x2028 } # = 0x080A
- - {field_name: rx_frame_spaddr3_1, width: 16, access_mode: RW, address_offset: 0x202c } # = 0x080B
- - {field_name: rx_pfc_control, width: 17, access_mode: RW, address_offset: 0x2060 } # = 0x0818
- - {field_name: tx_transfer_control, width: 1, access_mode: RW, address_offset: 0x4000 } # = 0x1000
- - {field_name: tx_transfer_status, width: 1, access_mode: RO, address_offset: 0x4004 } # = 0x1001
- - {field_name: tx_padins_control, width: 1, access_mode: RW, address_offset: 0x4100 } # = 0x1040
- - {field_name: tx_crcins_control, width: 2, access_mode: RW, address_offset: 0x4200 } # = 0x1080
- - {field_name: tx_pktunderflow_error, width: 32, access_mode: RO, address_offset: 0x4300, radix_width: 36 } # = 0x10C0
- - {field_name: tx_preamble_control, width: 1, access_mode: RW, address_offset: 0x4400 } # = 0x1100
- - {field_name: tx_pauseframe_control, width: 2, access_mode: RW, address_offset: 0x4500 } # = 0x1140
- - {field_name: tx_pauseframe_quanta, width: 16, access_mode: RW, address_offset: 0x4504 } # = 0x1141
- - {field_name: tx_pauseframe_enable, width: 1, access_mode: RW, address_offset: 0x4508 } # = 0x1142
# Altera is unclear about the width of the quanta registers. Assuming 32 bits, where bits 16:31 are reserved:
- - {field_name: pfc_pause_quanta_0, width: 32, access_mode: RW, address_offset: 0x4600 } # = 0x1180
- - {field_name: pfc_pause_quanta_1, width: 32, access_mode: RW, address_offset: 0x4604 } # = 0x1181
- - {field_name: pfc_pause_quanta_2, width: 32, access_mode: RW, address_offset: 0x4608 } # = 0x1182
- - {field_name: pfc_pause_quanta_3, width: 32, access_mode: RW, address_offset: 0x460c } # = 0x1183
- - {field_name: pfc_pause_quanta_4, width: 32, access_mode: RW, address_offset: 0x4610 } # = 0x1184
- - {field_name: pfc_pause_quanta_5, width: 32, access_mode: RW, address_offset: 0x4614 } # = 0x1185
- - {field_name: pfc_pause_quanta_6, width: 32, access_mode: RW, address_offset: 0x4618 } # = 0x1186
- - {field_name: pfc_pause_quanta_7, width: 32, access_mode: RW, address_offset: 0x461c } # = 0x1187
- - {field_name: pfc_holdoff_quanta_0, width: 32, access_mode: RW, address_offset: 0x4640 } # = 0x1190
- - {field_name: pfc_holdoff_quanta_1, width: 32, access_mode: RW, address_offset: 0x4644 } # = 0x1191
- - {field_name: pfc_holdoff_quanta_2, width: 32, access_mode: RW, address_offset: 0x4648 } # = 0x1192
- - {field_name: pfc_holdoff_quanta_3, width: 32, access_mode: RW, address_offset: 0x464c } # = 0x1193
- - {field_name: pfc_holdoff_quanta_4, width: 32, access_mode: RW, address_offset: 0x4650 } # = 0x1194
- - {field_name: pfc_holdoff_quanta_5, width: 32, access_mode: RW, address_offset: 0x4654 } # = 0x1195
- - {field_name: pfc_holdoff_quanta_6, width: 32, access_mode: RW, address_offset: 0x4658 } # = 0x1196
- - {field_name: pfc_holdoff_quanta_7, width: 32, access_mode: RW, address_offset: 0x465c } # = 0x1197
- - {field_name: tx_pfc_priority_enable, width: 8, access_mode: RW, address_offset: 0x4680 } # = 0x11A0
- - {field_name: tx_addrins_control, width: 1, access_mode: RW, address_offset: 0x4800 } # = 0x1200
- - {field_name: tx_addrins_macaddr0, width: 32, access_mode: RW, address_offset: 0x4804 } # = 0x1201
- - {field_name: tx_addrins_macaddr1, width: 16, access_mode: RW, address_offset: 0x4808 } # = 0x1202
- - {field_name: tx_frame_maxlength, width: 16, access_mode: RW, address_offset: 0x6004 } # = 0x1801
- - {field_name: rx_stats_clr, width: 1, access_mode: RW, address_offset: 0x3000 } # = 0x0C00
- - {field_name: tx_stats_clr, width: 1, access_mode: RW, address_offset: 0x7000 } # = 0x1C00
- - {field_name: rx_stats_framesOK, width: 32, access_mode: RO, address_offset: 0x3008, radix_width: 36 } # = 0x0C02
- - {field_name: tx_stats_framesOK, width: 32, access_mode: RO, address_offset: 0x7008, radix_width: 36 } # = 0x1C02
- - {field_name: rx_stats_framesErr, width: 32, access_mode: RO, address_offset: 0x3010, radix_width: 36 } # = 0x0C04
- - {field_name: tx_stats_framesErr, width: 32, access_mode: RO, address_offset: 0x7010, radix_width: 36 } # = 0x1C04
- - {field_name: rx_stats_framesCRCErr, width: 32, access_mode: RO, address_offset: 0x3018, radix_width: 36 } # = 0x0C06
- - {field_name: tx_stats_framesCRCErr, width: 32, access_mode: RO, address_offset: 0x7018, radix_width: 36 } # = 0x1C06
- - {field_name: rx_stats_octetsOK, width: 32, access_mode: RO, address_offset: 0x3020, radix_width: 36 } # = 0x0C08
- - {field_name: tx_stats_octetsOK, width: 32, access_mode: RO, address_offset: 0x7020, radix_width: 36 } # = 0x1C08
- - {field_name: rx_stats_pauseMACCtrl_Frames, width: 32, access_mode: RO, address_offset: 0x3028, radix_width: 36 } # = 0x0C0A
- - {field_name: tx_stats_pauseMACCtrl_Frames, width: 32, access_mode: RO, address_offset: 0x7028, radix_width: 36 } # = 0x1C0A
- - {field_name: rx_stats_ifErrors, width: 32, access_mode: RO, address_offset: 0x3030, radix_width: 36 } # = 0x0C0C
- - {field_name: tx_stats_ifErrors, width: 32, access_mode: RO, address_offset: 0x7030, radix_width: 36 } # = 0x1C0C
- - {field_name: rx_stats_unicast_FramesOK, width: 32, access_mode: RO, address_offset: 0x3038, radix_width: 36 } # = 0x0C0E
- - {field_name: tx_stats_unicast_FramesOK, width: 32, access_mode: RO, address_offset: 0x7038, radix_width: 36 } # = 0x1C0E
- - {field_name: rx_stats_unicast_FramesErr, width: 32, access_mode: RO, address_offset: 0x3040, radix_width: 36 } # = 0x0C10
- - {field_name: tx_stats_unicast_FramesErr, width: 32, access_mode: RO, address_offset: 0x7040, radix_width: 36 } # = 0x1C10
- - {field_name: rx_stats_multicastFramesOK, width: 32, access_mode: RO, address_offset: 0x3048, radix_width: 36 } # = 0x0C12
- - {field_name: tx_stats_multicastFramesOK, width: 32, access_mode: RO, address_offset: 0x7048, radix_width: 36 } # = 0x1C12
- - {field_name: rx_stats_multicast_FramesErr, width: 32, access_mode: RO, address_offset: 0x3050, radix_width: 36 } # = 0x0C14
- - {field_name: tx_stats_multicast_FramesErr, width: 32, access_mode: RO, address_offset: 0x7050, radix_width: 36 } # = 0x1C14
- - {field_name: rx_stats_broadcastFramesOK, width: 32, access_mode: RO, address_offset: 0x3058, radix_width: 36 } # = 0x0C16
- - {field_name: tx_stats_broadcastFramesOK, width: 32, access_mode: RO, address_offset: 0x7058, radix_width: 36 } # = 0x1C16
- - {field_name: rx_stats_broadcast_FramesErr, width: 32, access_mode: RO, address_offset: 0x3060, radix_width: 36 } # = 0x0C18
- - {field_name: tx_stats_broadcast_FramesErr, width: 32, access_mode: RO, address_offset: 0x7060, radix_width: 36 } # = 0x1C18
- - {field_name: rx_stats_etherStatsOctets, width: 32, access_mode: RO, address_offset: 0x3068, radix_width: 36 } # = 0x0C1A
- - {field_name: tx_stats_etherStatsOctets, width: 32, access_mode: RO, address_offset: 0x7068, radix_width: 36 } # = 0x1C1A
- - {field_name: rx_stats_etherStatsPkts, width: 32, access_mode: RO, address_offset: 0x3070, radix_width: 36 } # = 0x0C1C
- - {field_name: tx_stats_etherStatsPkts, width: 32, access_mode: RO, address_offset: 0x7070, radix_width: 36 } # = 0x1C1C
- - {field_name: rx_stats_etherStats_UndersizePkts, width: 32, access_mode: RO, address_offset: 0x3078, radix_width: 36 } # = 0x0C1E
- - {field_name: tx_stats_etherStats_UndersizePkts, width: 32, access_mode: RO, address_offset: 0x7078, radix_width: 36 } # = 0x1C1E
- - {field_name: rx_stats_etherStats_OversizePkts, width: 32, access_mode: RO, address_offset: 0x3080, radix_width: 36 } # = 0x0C20
- - {field_name: tx_stats_etherStats_OversizePkts, width: 32, access_mode: RO, address_offset: 0x7080, radix_width: 36 } # = 0x1C20
- - {field_name: rx_stats_etherStats_Pkts64Octets, width: 32, access_mode: RO, address_offset: 0x3088, radix_width: 36 } # = 0x0C22
- - {field_name: tx_stats_etherStats_Pkts64Octets, width: 32, access_mode: RO, address_offset: 0x7088, radix_width: 36 } # = 0x1C22
- - {field_name: rx_stats_etherStats_Pkts65to127Octets, width: 32, access_mode: RO, address_offset: 0x3090, radix_width: 36 } # = 0x0C24
- - {field_name: tx_stats_etherStats_Pkts65to127Octets, width: 32, access_mode: RO, address_offset: 0x7090, radix_width: 36 } # = 0x1C24
- - {field_name: rx_stats_etherStats_Pkts128to255Octets, width: 32, access_mode: RO, address_offset: 0x3098, radix_width: 36 } # = 0x0C26
- - {field_name: tx_stats_etherStats_Pkts128to255Octets, width: 32, access_mode: RO, address_offset: 0x7098, radix_width: 36 } # = 0x1C26
- - {field_name: rx_stats_etherStats_Pkts256to511Octets, width: 32, access_mode: RO, address_offset: 0x30a0, radix_width: 36 } # = 0x0C28
- - {field_name: tx_stats_etherStats_Pkts256to511Octets, width: 32, access_mode: RO, address_offset: 0x70a0, radix_width: 36 } # = 0x1C28
- - {field_name: rx_stats_etherStats_Pkts512to1023Octets, width: 32, access_mode: RO, address_offset: 0x30a8, radix_width: 36 } # = 0x0C2A
- - {field_name: tx_stats_etherStats_Pkts512to1023Octets, width: 32, access_mode: RO, address_offset: 0x70a8, radix_width: 36 } # = 0x1C2A
- - {field_name: rx_stats_etherStat_Pkts1024to1518Octets, width: 32, access_mode: RO, address_offset: 0x30b0, radix_width: 36 } # = 0x0C2C
- - {field_name: tx_stats_etherStat_Pkts1024to1518Octets, width: 32, access_mode: RO, address_offset: 0x70b0, radix_width: 36 } # = 0x1C2C
- - {field_name: rx_stats_etherStats_Pkts1519toXOctets, width: 32, access_mode: RO, address_offset: 0x30b8, radix_width: 36 } # = 0x0C2E
- - {field_name: tx_stats_etherStats_Pkts1519toXOctets, width: 32, access_mode: RO, address_offset: 0x70b8, radix_width: 36 } # = 0x1C2E
- - {field_name: rx_stats_etherStats_Fragments, width: 32, access_mode: RO, address_offset: 0x30c0, radix_width: 36 } # = 0x0C30
- - {field_name: tx_stats_etherStats_Fragments, width: 32, access_mode: RO, address_offset: 0x70c0, radix_width: 36 } # = 0x1C30
- - {field_name: rx_stats_etherStats_Jabbers, width: 32, access_mode: RO, address_offset: 0x30c8, radix_width: 36 } # = 0x0C32
- - {field_name: tx_stats_etherStats_Jabbers, width: 32, access_mode: RO, address_offset: 0x70c8, radix_width: 36 } # = 0x1C32
- - {field_name: rx_stats_etherStatsCRCErr, width: 32, access_mode: RO, address_offset: 0x30d0, radix_width: 36 } # = 0x0C34
- - {field_name: tx_stats_etherStatsCRCErr, width: 32, access_mode: RO, address_offset: 0x70d0, radix_width: 36 } # = 0x1C34
- - {field_name: rx_stats_unicastMACCtrlFrames, width: 32, access_mode: RO, address_offset: 0x30d8, radix_width: 36 } # = 0x0C36
- - {field_name: tx_stats_unicastMACCtrlFrames, width: 32, access_mode: RO, address_offset: 0x70d8, radix_width: 36 } # = 0x1C36
- - {field_name: rx_stats_multicastMAC_CtrlFrames, width: 32, access_mode: RO, address_offset: 0x30e0, radix_width: 36 } # = 0x0C38
- - {field_name: tx_stats_multicastMAC_CtrlFrames, width: 32, access_mode: RO, address_offset: 0x70e0, radix_width: 36 } # = 0x1C38
- - {field_name: rx_stats_broadcastMAC_CtrlFrames, width: 32, access_mode: RO, address_offset: 0x30e8, radix_width: 36 } # = 0x0C3A
- - {field_name: tx_stats_broadcastMAC_CtrlFrames, width: 32, access_mode: RO, address_offset: 0x70e8, radix_width: 36 } # = 0x1C3A
- - {field_name: rx_stats_PFCMACCtrlFrames, width: 32, access_mode: RO, address_offset: 0x30f0, radix_width: 36 } # = 0x0C3C
- - {field_name: tx_stats_PFCMACCtrlFrames, width: 32, access_mode: RO, address_offset: 0x70f0, radix_width: 36 } # = 0x1C3C
libraries/io/nw_10GbE/nw_10GbE_word_to_byte_address.py 0 → 100644
+ 120
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wo = [0x0000,
0x0001,
0x0040,
0x0080,
0x00C0,
0x00C2,
0x0100,
0x0140,
0x0800,
0x0801,
0x0802,
0x0803,
0x0804,
0x0805,
0x0806,
0x0807,
0x0808,
0x0809,
0x080A,
0x080B,
0x0818,
0x1000,
0x1001,
0x1040,
0x1080,
0x10C0,
0x1100,
0x1140,
0x1141,
0x1142,
0x1180,
0x1181,
0x1182,
0x1183,
0x1184,
0x1185,
0x1186,
0x1187,
0x1190,
0x1191,
0x1192,
0x1193,
0x1194,
0x1195,
0x1196,
0x1197,
0x11A0,
0x1200,
0x1201,
0x1202,
0x1801,
0x0C00,
0x1C00,
0x0C02,
0x1C02,
0x0C04,
0x1C04,
0x0C06,
0x1C06,
0x0C08,
0x1C08,
0x0C0A,
0x1C0A,
0x0C0C,
0x1C0C,
0x0C0E,
0x1C0E,
0x0C10,
0x1C10,
0x0C12,
0x1C12,
0x0C14,
0x1C14,
0x0C16,
0x1C16,
0x0C18,
0x1C18,
0x0C1A,
0x1C1A,
0x0C1C,
0x1C1C,
0x0C1E,
0x1C1E,
0x0C20,
0x1C20,
0x0C22,
0x1C22,
0x0C24,
0x1C24,
0x0C26,
0x1C26,
0x0C28,
0x1C28,
0x0C2A,
0x1C2A,
0x0C2C,
0x1C2C,
0x0C2E,
0x1C2E,
0x0C30,
0x1C30,
0x0C32,
0x1C32,
0x0C34,
0x1C34,
0x0C36,
0x1C36,
0x0C38,
0x1C38,
0x0C3A,
0x1C3A,
0x0C3C,
0x1C3C]
for a in wo:
#print '%x' % (a*4) # python v2
print('0x{:04x}'.format(a*4)) # python3
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