Renamed reg/ram_diag_data_buf to buffer

Connected the eth1_tse_clk

boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/mmm_unb1_terminal_bg_mesh_db.vhd

@@ -303,9 +303,9 @@ BEGIN
           PORT MAP(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
     u_mm_file_eth1g_tse  :  mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ETH1G_TSE")
           PORT MAP(mm_rst, mm_clk, eth1g_tse_mosi, eth1g_tse_miso );
-    u_mm_file_reg_diag_data_buf  :  mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUF")
+    u_mm_file_reg_diag_data_buf  :  mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER")
           PORT MAP(mm_rst, mm_clk, reg_diag_data_buf_mosi, reg_diag_data_buf_miso );
-    u_mm_file_ram_diag_data_buf  :  mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUF")
+    u_mm_file_ram_diag_data_buf  :  mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER")
           PORT MAP(mm_rst, mm_clk, ram_diag_data_buf_mosi, ram_diag_data_buf_miso );
     u_mm_file_reg_diag_bg  :  mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG")
           PORT MAP(mm_rst, mm_clk, reg_diag_bg_mosi, reg_diag_bg_miso );
@@ -359,7 +359,7 @@ BEGIN
       PORT MAP(
       clk_in_clk                              => mm_clk,
       eth1g_irq_export                        => eth1g_reg_interrupt,
-      eth1g_mm_clk_export                     => OPEN,
+      eth1g_mm_clk_export                     => eth1g_tse_clk,
       eth1g_mm_rst_export                     => eth1g_mm_rst,
       eth1g_ram_address_export                => eth1g_ram_mosi.address(9 DOWNTO 0),
       eth1g_ram_read_export                   => eth1g_ram_mosi.rd,