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Commit b559785d authored by Eric Kooistra's avatar Eric Kooistra
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Define t_mem_ctlr_mosi/miso in common_mem_pkg, to use that instead of the...

Define t_mem_ctlr_mosi/miso in common_mem_pkg, to use that instead of the records defined in tech_ddr_pkg. Also remove t_tech_ddr_addr record because it is not needed.
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...@@ -26,8 +26,10 @@ USE work.common_pkg.ALL; ...@@ -26,8 +26,10 @@ USE work.common_pkg.ALL;
PACKAGE common_mem_pkg IS PACKAGE common_mem_pkg IS
-- Memory access ------------------------------------------------------------------------------
-- -- Simple memory access (for MM control interface)
------------------------------------------------------------------------------
-- Assume the MM bus is for a 32 bit processor, therefore on the processor -- Assume the MM bus is for a 32 bit processor, therefore on the processor
-- side of a memory peripheral typcially use c_word_w = 32 for the address -- side of a memory peripheral typcially use c_word_w = 32 for the address
-- and data fields in the MM bus records. However the MM bus can also be used -- and data fields in the MM bus records. However the MM bus can also be used
...@@ -49,7 +51,8 @@ PACKAGE common_mem_pkg IS ...@@ -49,7 +51,8 @@ PACKAGE common_mem_pkg IS
-- Do not change these widths, because c_word_w just fits in a VHDL INTEGER -- Do not change these widths, because c_word_w just fits in a VHDL INTEGER
-- Should wider address range or data width be needed, then define a new -- Should wider address range or data width be needed, then define a new
-- record type t_mem_bus for that with sufficient widths. -- record type eg. t_mem_ddr, t_mem_ctlr or t_mem_bus for that with
-- sufficient widths.
-- Choose smallest maximum slv lengths that fit all use cases, because unconstrained record fields slv is not allowed -- Choose smallest maximum slv lengths that fit all use cases, because unconstrained record fields slv is not allowed
CONSTANT c_mem_address_w : NATURAL := 32; -- address range (suits 32-bit processor) CONSTANT c_mem_address_w : NATURAL := 32; -- address range (suits 32-bit processor)
...@@ -77,6 +80,58 @@ PACKAGE common_mem_pkg IS ...@@ -77,6 +80,58 @@ PACKAGE common_mem_pkg IS
TYPE t_mem_miso_arr IS ARRAY (INTEGER RANGE <>) OF t_mem_miso; TYPE t_mem_miso_arr IS ARRAY (INTEGER RANGE <>) OF t_mem_miso;
TYPE t_mem_mosi_arr IS ARRAY (INTEGER RANGE <>) OF t_mem_mosi; TYPE t_mem_mosi_arr IS ARRAY (INTEGER RANGE <>) OF t_mem_mosi;
-- Resize functions to fit an integer or an SLV in the corresponding t_mem_miso or t_mem_mosi field width
FUNCTION TO_MEM_ADDRESS(n : INTEGER) RETURN STD_LOGIC_VECTOR; -- unsigned, use integer to support 32 bit range
FUNCTION TO_MEM_DATA( n : INTEGER) RETURN STD_LOGIC_VECTOR; -- unsigned, alias of TO_MEM_DATA()
FUNCTION TO_MEM_UDATA( n : INTEGER) RETURN STD_LOGIC_VECTOR; -- unsigned, use integer to support 32 bit range
FUNCTION TO_MEM_SDATA( n : INTEGER) RETURN STD_LOGIC_VECTOR; -- sign extended
FUNCTION RESIZE_MEM_ADDRESS(vec : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR; -- unsigned
FUNCTION RESIZE_MEM_DATA( vec : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR; -- unsigned, alias of RESIZE_MEM_UDATA
FUNCTION RESIZE_MEM_UDATA( vec : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR; -- unsigned
FUNCTION RESIZE_MEM_SDATA( vec : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR; -- sign extended
FUNCTION RESIZE_MEM_XDATA( vec : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR; -- set unused MSBits to 'X'
------------------------------------------------------------------------------
-- Burst memory access (for DDR access interface)
------------------------------------------------------------------------------
-- Choose smallest maximum slv lengths that fit all use cases, because unconstrained record fields slv is not allowed
CONSTANT c_mem_ctlr_address_w : NATURAL := 32;
CONSTANT c_mem_ctlr_data_w : NATURAL := 576;
CONSTANT c_mem_ctlr_burstsize_w : NATURAL := c_mem_ctlr_address_w;
TYPE t_mem_ctlr_miso IS RECORD
rddata : STD_LOGIC_VECTOR(c_mem_ctlr_data_w-1 DOWNTO 0);
rdval : STD_LOGIC;
waitrequest_n : STD_LOGIC;
END RECORD;
TYPE t_mem_ctlr_mosi IS RECORD
address : STD_LOGIC_VECTOR(c_mem_ctlr_address_w-1 DOWNTO 0);
wrdata : STD_LOGIC_VECTOR(c_mem_ctlr_data_w-1 DOWNTO 0);
wr : STD_LOGIC;
rd : STD_LOGIC;
burstbegin : STD_LOGIC;
burstsize : STD_LOGIC_VECTOR(c_mem_ctlr_burstsize_w-1 DOWNTO 0);
END RECORD;
CONSTANT c_mem_ctlr_miso_rst : t_mem_ctlr_miso := ((OTHERS=>'0'), '0', '0');
CONSTANT c_mem_ctlr_mosi_rst : t_mem_ctlr_mosi := ((OTHERS=>'0'), (OTHERS=>'0'), '0', '0', '0', (OTHERS=>'0'));
-- Resize functions to fit an integer or an SLV in the corresponding t_mem_ctlr_miso or t_mem_ctlr_mosi field width
FUNCTION TO_MEM_CTLR_ADDRESS( n : INTEGER) RETURN STD_LOGIC_VECTOR; -- unsigned, use integer to support 32 bit range
FUNCTION TO_MEM_CTLR_DATA( n : INTEGER) RETURN STD_LOGIC_VECTOR; -- unsigned
FUNCTION TO_MEM_CTLR_BURSTSIZE(n : INTEGER) RETURN STD_LOGIC_VECTOR; -- unsigned
FUNCTION RESIZE_MEM_CTLR_ADDRESS( vec : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR; -- unsigned
FUNCTION RESIZE_MEM_CTLR_DATA( vec : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR; -- unsigned
FUNCTION RESIZE_MEM_CTLR_BURSTSIZE(vec : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR; -- unsigned
------------------------------------------------------------------------------
-- RAM block memory and MM register defintions
------------------------------------------------------------------------------
TYPE t_c_mem IS RECORD TYPE t_c_mem IS RECORD
latency : NATURAL; -- read latency latency : NATURAL; -- read latency
adr_w : NATURAL; adr_w : NATURAL;
...@@ -94,18 +149,6 @@ PACKAGE common_mem_pkg IS ...@@ -94,18 +149,6 @@ PACKAGE common_mem_pkg IS
CONSTANT c_mem_reg_init_w : NATURAL := 1*256*32; -- >= largest expected value of dat_w*nof_dat (256 * 32 bit = 1k byte) CONSTANT c_mem_reg_init_w : NATURAL := 1*256*32; -- >= largest expected value of dat_w*nof_dat (256 * 32 bit = 1k byte)
------------------------------------------------------------------------------
-- Resize functions to fit an integer or an SLV in the corresponding t_mem_miso or t_mem_mosi field width
------------------------------------------------------------------------------
FUNCTION TO_MEM_ADDRESS(n : INTEGER) RETURN STD_LOGIC_VECTOR; -- unsigned, use integer to support 32 bit range
FUNCTION TO_MEM_DATA( n : INTEGER) RETURN STD_LOGIC_VECTOR; -- unsigned, alias of TO_MEM_DATA()
FUNCTION TO_MEM_UDATA( n : INTEGER) RETURN STD_LOGIC_VECTOR; -- unsigned, use integer to support 32 bit range
FUNCTION TO_MEM_SDATA( n : INTEGER) RETURN STD_LOGIC_VECTOR; -- sign extended
FUNCTION RESIZE_MEM_ADDRESS(vec : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR; -- unsigned
FUNCTION RESIZE_MEM_DATA( vec : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR; -- unsigned, alias of RESIZE_MEM_UDATA
FUNCTION RESIZE_MEM_UDATA( vec : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR; -- unsigned
FUNCTION RESIZE_MEM_SDATA( vec : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR; -- sign extended
FUNCTION RESIZE_MEM_XDATA( vec : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR; -- set unused MSBits to 'X'
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- Functions to swap endianess -- Functions to swap endianess
...@@ -165,6 +208,39 @@ PACKAGE BODY common_mem_pkg IS ...@@ -165,6 +208,39 @@ PACKAGE BODY common_mem_pkg IS
RETURN v_vec; RETURN v_vec;
END RESIZE_MEM_XDATA; END RESIZE_MEM_XDATA;
-- Resize functions to fit an integer or an SLV in the corresponding t_mem_miso or t_mem_mosi field width
FUNCTION TO_MEM_CTLR_ADDRESS(n : INTEGER) RETURN STD_LOGIC_VECTOR IS
BEGIN
RETURN RESIZE_UVEC(TO_SVEC(n, 32), c_mem_ctlr_address_w);
END TO_MEM_CTLR_ADDRESS;
FUNCTION TO_MEM_CTLR_DATA(n : INTEGER) RETURN STD_LOGIC_VECTOR IS
BEGIN
RETURN RESIZE_UVEC(TO_SVEC(n, 32), c_mem_ctlr_data_w);
END TO_MEM_CTLR_DATA;
FUNCTION TO_MEM_CTLR_BURSTSIZE(n : INTEGER) RETURN STD_LOGIC_VECTOR IS
BEGIN
RETURN RESIZE_UVEC(TO_SVEC(n, 32), c_mem_ctlr_burstsize_w);
END TO_MEM_CTLR_BURSTSIZE;
FUNCTION RESIZE_MEM_CTLR_ADDRESS(vec : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
BEGIN
RETURN RESIZE_UVEC(vec, c_mem_ctlr_address_w);
END RESIZE_MEM_CTLR_ADDRESS;
FUNCTION RESIZE_MEM_CTLR_DATA(vec : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
BEGIN
RETURN RESIZE_UVEC(vec, c_mem_ctlr_data_w);
END RESIZE_MEM_CTLR_DATA;
FUNCTION RESIZE_MEM_CTLR_BURSTSIZE(vec : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
BEGIN
RETURN RESIZE_UVEC(vec, c_mem_ctlr_burstsize_w);
END RESIZE_MEM_CTLR_BURSTSIZE;
-- Functions to swap endianess -- Functions to swap endianess
FUNCTION func_mem_swap_endianess(mm : t_mem_miso; sz : NATURAL) RETURN t_mem_miso IS FUNCTION func_mem_swap_endianess(mm : t_mem_miso; sz : NATURAL) RETURN t_mem_miso IS
VARIABLE v_mm : t_mem_miso; VARIABLE v_mm : t_mem_miso;
......
...@@ -40,6 +40,21 @@ ...@@ -40,6 +40,21 @@
-- runs full in case a next write access will not happen soon enough. A next -- runs full in case a next write access will not happen soon enough. A next
-- DDR write access can start on the next valid, sop or sync dependent on -- DDR write access can start on the next valid, sop or sync dependent on
-- g_wr_flush_mode. -- g_wr_flush_mode.
--
-- Usage:
-- . The dvr interface could be connected to a MM interface. The DDR memory
-- may then be used to capture (large) blocks of streaming data that can
-- offline be read via a DP-MM interface (eg. like in bn_capture). During
-- the read access the streaming write data then is flushed.
-- . The dvr interface could be connected to signals from a DP interface. For
-- write access the dvr_en could connect to the wr_sosi.sop and the
-- dvr_nof_data then equals the nof data from sop to eop. The dvr_done can
-- be treated as wr_siso.xon. The dvr_wr_not_rd selects between the write
-- stream to DDR access or the read stream from DDR access. For a read
-- access or to a DP
-- interface
-- The dvr_en could be connected to a DP sop
-- --
-- Block diagram: -- Block diagram:
-- --
...@@ -91,6 +106,7 @@ ...@@ -91,6 +106,7 @@
LIBRARY IEEE, technology_lib, tech_ddr_lib, common_lib, dp_lib; LIBRARY IEEE, technology_lib, tech_ddr_lib, common_lib, dp_lib;
USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_1164.ALL;
USE common_lib.common_pkg.ALL; USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE technology_lib.technology_select_pkg.ALL; USE technology_lib.technology_select_pkg.ALL;
USE technology_lib.technology_pkg.ALL; USE technology_lib.technology_pkg.ALL;
USE tech_ddr_lib.tech_ddr_pkg.ALL; USE tech_ddr_lib.tech_ddr_pkg.ALL;
...@@ -178,8 +194,8 @@ ARCHITECTURE str OF io_ddr IS ...@@ -178,8 +194,8 @@ ARCHITECTURE str OF io_ddr IS
SIGNAL ctlr_init_done : STD_LOGIC; SIGNAL ctlr_init_done : STD_LOGIC;
SIGNAL ctlr_mosi : t_tech_ddr_mosi := c_tech_ddr_mosi_rst; SIGNAL ctlr_mosi : t_mem_ctlr_mosi := c_mem_ctlr_mosi_rst;
SIGNAL ctlr_miso : t_tech_ddr_miso := c_tech_ddr_miso_rst; SIGNAL ctlr_miso : t_mem_ctlr_miso := c_mem_ctlr_miso_rst;
SIGNAL ctlr_wr_flush_en : STD_LOGIC := '0'; SIGNAL ctlr_wr_flush_en : STD_LOGIC := '0';
......
...@@ -23,7 +23,7 @@ ...@@ -23,7 +23,7 @@
-- Purpose: Provide streaming interface to DDR memory -- Purpose: Provide streaming interface to DDR memory
-- Description: -- Description:
-- Write or read a block of data to or from DDR memory. The data width is set -- Write or read a block of data to or from DDR memory. The data width is set
-- by the DDR controller data width given by RESIZE_DDR_CTLR_DATA() and eg. -- by the DDR controller data width given by RESIZE_MEM_CTLR_DATA() and eg.
-- 256 bits for DDR3 with 64 bit DQ data. The block of data is located from -- 256 bits for DDR3 with 64 bit DQ data. The block of data is located from
-- dvr_start_address to dvr_nof_data. -- dvr_start_address to dvr_nof_data.
-- The io_ddr_driver takes care that the access is done in a number of bursts. -- The io_ddr_driver takes care that the access is done in a number of bursts.
...@@ -36,6 +36,7 @@ LIBRARY IEEE, tech_ddr_lib, common_lib, dp_lib; ...@@ -36,6 +36,7 @@ LIBRARY IEEE, tech_ddr_lib, common_lib, dp_lib;
USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL; USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL; USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL; USE dp_lib.dp_stream_pkg.ALL;
USE tech_ddr_lib.tech_ddr_pkg.ALL; USE tech_ddr_lib.tech_ddr_pkg.ALL;
...@@ -60,8 +61,8 @@ ENTITY io_ddr_driver IS ...@@ -60,8 +61,8 @@ ENTITY io_ddr_driver IS
rd_src_in : IN t_dp_siso; rd_src_in : IN t_dp_siso;
ctlr_init_done : IN STD_LOGIC; ctlr_init_done : IN STD_LOGIC;
ctlr_miso : IN t_tech_ddr_miso; ctlr_miso : IN t_mem_ctlr_miso;
ctlr_mosi : OUT t_tech_ddr_mosi ctlr_mosi : OUT t_mem_ctlr_mosi
); );
END io_ddr_driver; END io_ddr_driver;
...@@ -132,8 +133,8 @@ BEGIN ...@@ -132,8 +133,8 @@ BEGIN
BEGIN BEGIN
nxt_state <= state; nxt_state <= state;
ctlr_mosi.address <= RESIZE_DDR_CTLR_ADDRESS(cur_address); ctlr_mosi.address <= RESIZE_MEM_CTLR_ADDRESS(cur_address);
ctlr_mosi.wrdata <= RESIZE_DDR_CTLR_DATA(wr_snk_in.data); ctlr_mosi.wrdata <= RESIZE_MEM_CTLR_DATA(wr_snk_in.data);
ctlr_mosi.wr <= '0'; ctlr_mosi.wr <= '0';
ctlr_mosi.rd <= '0'; ctlr_mosi.rd <= '0';
ctlr_mosi.burstbegin <= '0'; ctlr_mosi.burstbegin <= '0';
...@@ -169,14 +170,14 @@ BEGIN ...@@ -169,14 +170,14 @@ BEGIN
wr_snk_out.ready <= '1'; wr_snk_out.ready <= '1';
ctlr_mosi.wr <= '1'; ctlr_mosi.wr <= '1';
ctlr_mosi.burstbegin <= '1'; -- assert burstbegin, ctlr_mosi.burstbegin <= '1'; -- assert burstbegin,
ctlr_mosi.burstsize <= TO_DDR_CTLR_BURSTSIZE(burst_size); -- burstsize >= 1 ctlr_mosi.burstsize <= TO_MEM_CTLR_BURSTSIZE(burst_size); -- burstsize >= 1
nxt_cur_address <= INCR_UVEC(cur_address, burst_size); nxt_cur_address <= INCR_UVEC(cur_address, burst_size);
nxt_address_cnt <= INCR_UVEC(address_cnt, -burst_size); nxt_address_cnt <= INCR_UVEC(address_cnt, -burst_size);
nxt_burst_wr_cnt <= TO_UVEC(burst_size-1, g_tech_ddr.maxburstsize_w);
-- Return for next wr request or perform any remaining writes in this burst -- Return for next wr request or perform any remaining writes in this burst
nxt_state <= s_wait; nxt_state <= s_wait;
IF burst_size > 1 THEN IF burst_size > 1 THEN
nxt_state <= s_wr_burst; nxt_state <= s_wr_burst; -- first burst wr cycle is done here, the rest are done in s_wr_burst
nxt_burst_wr_cnt <= TO_DDR_CTLR_BURSTSIZE(burst_size-1); -- first burst wr cycle is done here, the rest are done in s_wr_burst
END IF; END IF;
END IF; END IF;
END IF; END IF;
...@@ -190,7 +191,7 @@ BEGIN ...@@ -190,7 +191,7 @@ BEGIN
IF ctlr_miso.waitrequest_n = '1' THEN IF ctlr_miso.waitrequest_n = '1' THEN
ctlr_mosi.rd <= '1'; ctlr_mosi.rd <= '1';
ctlr_mosi.burstbegin <= '1'; -- assert burstbegin, ctlr_mosi.burstbegin <= '1'; -- assert burstbegin,
ctlr_mosi.burstsize <= TO_DDR_CTLR_BURSTSIZE(burst_size); -- burstsize >= 1 ctlr_mosi.burstsize <= TO_MEM_CTLR_BURSTSIZE(burst_size); -- burstsize >= 1
nxt_cur_address <= INCR_UVEC(cur_address, burst_size); nxt_cur_address <= INCR_UVEC(cur_address, burst_size);
nxt_address_cnt <= INCR_UVEC(address_cnt, -burst_size); nxt_address_cnt <= INCR_UVEC(address_cnt, -burst_size);
-- Return for next rd request -- Return for next rd request
......
...@@ -20,8 +20,9 @@ ...@@ -20,8 +20,9 @@
-- --
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
LIBRARY IEEE, technology_lib, tech_ddr_lib; LIBRARY IEEE, common_lib, technology_lib, tech_ddr_lib;
USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_1164.ALL;
USE common_lib.common_mem_pkg.ALL;
USE technology_lib.technology_pkg.ALL; USE technology_lib.technology_pkg.ALL;
USE technology_lib.technology_select_pkg.ALL; USE technology_lib.technology_select_pkg.ALL;
USE tech_ddr_lib.tech_ddr_pkg.ALL; USE tech_ddr_lib.tech_ddr_pkg.ALL;
...@@ -44,8 +45,8 @@ ENTITY tech_ddr IS ...@@ -44,8 +45,8 @@ ENTITY tech_ddr IS
ctlr_init_done : OUT STD_LOGIC; ctlr_init_done : OUT STD_LOGIC;
ctlr_mosi : IN t_tech_ddr_mosi; ctlr_mosi : IN t_mem_ctlr_mosi;
ctlr_miso : OUT t_tech_ddr_miso; ctlr_miso : OUT t_mem_ctlr_miso;
-- PHY interface -- PHY interface
phy_in : IN t_tech_ddr_phy_in; phy_in : IN t_tech_ddr_phy_in;
......
...@@ -106,78 +106,25 @@ PACKAGE tech_ddr_pkg IS ...@@ -106,78 +106,25 @@ PACKAGE tech_ddr_pkg IS
TYPE t_tech_ddr_phy_io_arr IS ARRAY(NATURAL RANGE <>) OF t_tech_ddr_phy_io; TYPE t_tech_ddr_phy_io_arr IS ARRAY(NATURAL RANGE <>) OF t_tech_ddr_phy_io;
TYPE t_tech_ddr_phy_ou_arr IS ARRAY(NATURAL RANGE <>) OF t_tech_ddr_phy_ou; TYPE t_tech_ddr_phy_ou_arr IS ARRAY(NATURAL RANGE <>) OF t_tech_ddr_phy_ou;
-- PHY address signal record
TYPE t_tech_ddr_addr IS RECORD
chip : STD_LOGIC_VECTOR(c_tech_ddr_max.cs_w_w -1 DOWNTO 0);
bank : STD_LOGIC_VECTOR(c_tech_ddr_max.ba_w -1 DOWNTO 0);
row : STD_LOGIC_VECTOR(c_tech_ddr_max.a_row_w-1 DOWNTO 0);
col : STD_LOGIC_VECTOR(c_tech_ddr_max.a_col_w-1 DOWNTO 0);
END RECORD;
TYPE t_tech_ddr_addr_arr IS ARRAY(NATURAL RANGE <>) OF t_tech_ddr_addr;
CONSTANT c_tech_ddr_addr_lo : t_tech_ddr_addr := ((OTHERS=>'0'),
(OTHERS=>'0'),
(OTHERS=>'0'),
(OTHERS=>'0'));
FUNCTION func_tech_ddr_dq_address( dq_address : STD_LOGIC_VECTOR; c_ddr : t_c_tech_ddr) RETURN t_tech_ddr_addr;
FUNCTION func_tech_ddr_dq_address( ddr_addr : t_tech_ddr_addr; c_ddr : t_c_tech_ddr) RETURN STD_LOGIC_VECTOR;
FUNCTION func_tech_ddr_ctlr_address(ddr_addr : t_tech_ddr_addr; c_ddr : t_c_tech_ddr) RETURN STD_LOGIC_VECTOR;
-- PHY MM access signal record
-- Choose smallest maximum slv lengths that fit all use cases, because unconstrained record fields slv is not allowed
CONSTANT c_tech_ddr_ctlr_address_w : NATURAL := 32; -- >= func_tech_ddr_ctlr_address_w(c_tech_ddr_max);
CONSTANT c_tech_ddr_ctlr_data_w : NATURAL := 576; -- >= func_tech_ddr_ctlr_data_w( c_tech_ddr_max);
CONSTANT c_tech_ddr_ctlr_burstsize_w : NATURAL := c_tech_ddr_max.maxburstsize_w;
TYPE t_tech_ddr_miso IS RECORD
rddata : STD_LOGIC_VECTOR(c_tech_ddr_ctlr_data_w-1 DOWNTO 0);
rdval : STD_LOGIC;
waitrequest_n : STD_LOGIC;
END RECORD;
TYPE t_tech_ddr_mosi IS RECORD
address : STD_LOGIC_VECTOR(c_tech_ddr_ctlr_address_w-1 DOWNTO 0);
wrdata : STD_LOGIC_VECTOR(c_tech_ddr_ctlr_data_w-1 DOWNTO 0);
wr : STD_LOGIC;
rd : STD_LOGIC;
burstbegin : STD_LOGIC;
burstsize : STD_LOGIC_VECTOR(c_tech_ddr_ctlr_burstsize_w-1 DOWNTO 0);
END RECORD;
CONSTANT c_tech_ddr_miso_rst : t_tech_ddr_miso := ((OTHERS=>'0'), '0', '0');
CONSTANT c_tech_ddr_mosi_rst : t_tech_ddr_mosi := ((OTHERS=>'0'), (OTHERS=>'0'), '0', '0', '0', (OTHERS=>'0'));
-- Resize functions to fit an integer or an SLV in the corresponding t_tech_ddr_miso or t_tech_ddr_mosi field width
FUNCTION TO_DDR_CTLR_ADDRESS( n : INTEGER) RETURN STD_LOGIC_VECTOR; -- unsigned, use integer to support 32 bit range
FUNCTION TO_DDR_CTLR_DATA( n : INTEGER) RETURN STD_LOGIC_VECTOR; -- unsigned
FUNCTION TO_DDR_CTLR_BURSTSIZE(n : INTEGER) RETURN STD_LOGIC_VECTOR; -- unsigned
FUNCTION RESIZE_DDR_CTLR_ADDRESS( vec : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR; -- unsigned
FUNCTION RESIZE_DDR_CTLR_DATA( vec : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR; -- unsigned
FUNCTION RESIZE_DDR_CTLR_BURSTSIZE(vec : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR; -- unsigned
END tech_ddr_pkg; END tech_ddr_pkg;
PACKAGE BODY tech_ddr_pkg IS PACKAGE BODY tech_ddr_pkg IS
FUNCTION func_tech_ddr_dq_address_w(c_ddr : t_c_tech_ddr) RETURN NATURAL IS FUNCTION func_tech_ddr_dq_address_w(c_ddr : t_c_tech_ddr) RETURN NATURAL IS
BEGIN BEGIN
RETURN c_ddr.cs_w_w + c_ddr.ba_w + c_ddr.a_w + c_ddr.a_col_w; RETURN c_ddr.cs_w_w + c_ddr.ba_w + c_ddr.a_w + c_ddr.a_col_w; -- PHY address
END; END;
FUNCTION func_tech_ddr_ctlr_address_w(c_ddr : t_c_tech_ddr) RETURN NATURAL IS FUNCTION func_tech_ddr_ctlr_address_w(c_ddr : t_c_tech_ddr) RETURN NATURAL IS
CONSTANT c_dq_address_w : NATURAL := func_tech_ddr_dq_address_w(c_ddr); CONSTANT c_dq_address_w : NATURAL := func_tech_ddr_dq_address_w(c_ddr);
BEGIN BEGIN
RETURN c_dq_address_w-c_ddr.rsl_w; RETURN c_dq_address_w-c_ddr.rsl_w; -- CTLR address
END; END;
FUNCTION func_tech_ddr_ctlr_data_w(c_ddr : t_c_tech_ddr) RETURN NATURAL IS FUNCTION func_tech_ddr_ctlr_data_w(c_ddr : t_c_tech_ddr) RETURN NATURAL IS
CONSTANT c_dq_address_w : NATURAL := func_tech_ddr_dq_address_w(c_ddr); CONSTANT c_dq_address_w : NATURAL := func_tech_ddr_dq_address_w(c_ddr);
BEGIN BEGIN
RETURN c_ddr.dq_w*c_ddr.rsl; RETURN c_ddr.dq_w*c_ddr.rsl; -- CTLR data
END; END;
FUNCTION func_tech_ddr_module_size(c_ddr : t_c_tech_ddr) RETURN NATURAL IS FUNCTION func_tech_ddr_module_size(c_ddr : t_c_tech_ddr) RETURN NATURAL IS
...@@ -190,62 +137,5 @@ PACKAGE BODY tech_ddr_pkg IS ...@@ -190,62 +137,5 @@ PACKAGE BODY tech_ddr_pkg IS
RETURN 2**(c_module_nof_bytes_w-c_1GB_w); RETURN 2**(c_module_nof_bytes_w-c_1GB_w);
END; END;
FUNCTION func_tech_ddr_dq_address(dq_address : STD_LOGIC_VECTOR; c_ddr : t_c_tech_ddr) RETURN t_tech_ddr_addr IS
VARIABLE v_ddr_addr : t_tech_ddr_addr := c_tech_ddr_addr_lo;
BEGIN
v_ddr_addr.chip(c_ddr.cs_w_w -1 DOWNTO 0) := dq_address(c_ddr.cs_w_w+c_ddr.ba_w+c_ddr.a_w+c_ddr.a_col_w-1 DOWNTO c_ddr.ba_w+c_ddr.a_w+c_ddr.a_col_w);
v_ddr_addr.bank(c_ddr.ba_w -1 DOWNTO 0) := dq_address( c_ddr.ba_w+c_ddr.a_w+c_ddr.a_col_w-1 DOWNTO c_ddr.a_w+c_ddr.a_col_w);
v_ddr_addr.row( c_ddr.a_w -1 DOWNTO 0) := dq_address( c_ddr.a_w+c_ddr.a_col_w-1 DOWNTO c_ddr.a_col_w);
v_ddr_addr.col( c_ddr.a_col_w-1 DOWNTO 0) := dq_address( c_ddr.a_col_w-1 DOWNTO 0);
RETURN v_ddr_addr;
END;
FUNCTION func_tech_ddr_dq_address(ddr_addr : t_tech_ddr_addr; c_ddr : t_c_tech_ddr) RETURN STD_LOGIC_VECTOR IS
CONSTANT c_dq_address_w : NATURAL := func_tech_ddr_dq_address_w(c_ddr);
BEGIN
RETURN RESIZE_UVEC(ddr_addr.chip(c_ddr.cs_w_w -1 DOWNTO 0) &
ddr_addr.bank(c_ddr.ba_w -1 DOWNTO 0) &
ddr_addr.row( c_ddr.a_row_w-1 DOWNTO 0) &
ddr_addr.col( c_ddr.a_col_w-1 DOWNTO 0), c_dq_address_w);
END;
FUNCTION func_tech_ddr_ctlr_address(ddr_addr : t_tech_ddr_addr; c_ddr : t_c_tech_ddr) RETURN STD_LOGIC_VECTOR IS
CONSTANT c_dq_address_w : NATURAL := func_tech_ddr_dq_address_w(c_ddr);
CONSTANT c_dq_address : STD_LOGIC_VECTOR(c_dq_address_w-1 DOWNTO 0) := func_tech_ddr_dq_address(ddr_addr, c_ddr);
CONSTANT c_ctlr_address_w : NATURAL := func_tech_ddr_ctlr_address_w(c_ddr);
BEGIN
RETURN RESIZE_UVEC(c_dq_address(c_dq_address_w-1 DOWNTO c_ddr.rsl_w), c_ctlr_address_w);
END;
FUNCTION TO_DDR_CTLR_ADDRESS(n : INTEGER) RETURN STD_LOGIC_VECTOR IS
BEGIN
RETURN RESIZE_UVEC(TO_SVEC(n, 32), c_tech_ddr_ctlr_address_w);
END TO_DDR_CTLR_ADDRESS;
FUNCTION TO_DDR_CTLR_DATA(n : INTEGER) RETURN STD_LOGIC_VECTOR IS
BEGIN
RETURN RESIZE_UVEC(TO_SVEC(n, 32), c_tech_ddr_ctlr_data_w);
END TO_DDR_CTLR_DATA;
FUNCTION TO_DDR_CTLR_BURSTSIZE(n : INTEGER) RETURN STD_LOGIC_VECTOR IS
BEGIN
RETURN RESIZE_UVEC(TO_SVEC(n, 32), c_tech_ddr_ctlr_burstsize_w);
END TO_DDR_CTLR_BURSTSIZE;
FUNCTION RESIZE_DDR_CTLR_ADDRESS(vec : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
BEGIN
RETURN RESIZE_UVEC(vec, c_tech_ddr_ctlr_address_w);
END RESIZE_DDR_CTLR_ADDRESS;
FUNCTION RESIZE_DDR_CTLR_DATA(vec : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
BEGIN
RETURN RESIZE_UVEC(vec, c_tech_ddr_ctlr_data_w);
END RESIZE_DDR_CTLR_DATA;
FUNCTION RESIZE_DDR_CTLR_BURSTSIZE(vec : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
BEGIN
RETURN RESIZE_UVEC(vec, c_tech_ddr_ctlr_burstsize_w);
END RESIZE_DDR_CTLR_BURSTSIZE;
END tech_ddr_pkg; END tech_ddr_pkg;
...@@ -26,6 +26,7 @@ LIBRARY ip_stratixiv_ddr3_uphy_4g_800_slave_lib; ...@@ -26,6 +26,7 @@ LIBRARY ip_stratixiv_ddr3_uphy_4g_800_slave_lib;
LIBRARY IEEE, technology_lib, common_lib; LIBRARY IEEE, technology_lib, common_lib;
USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_1164.ALL;
USE common_lib.common_mem_pkg.ALL;
USE technology_lib.technology_pkg.ALL; USE technology_lib.technology_pkg.ALL;
USE work.tech_ddr_pkg.ALL; USE work.tech_ddr_pkg.ALL;
USE work.tech_ddr_component_pkg.ALL; USE work.tech_ddr_component_pkg.ALL;
...@@ -47,8 +48,8 @@ ENTITY tech_ddr_stratixiv IS ...@@ -47,8 +48,8 @@ ENTITY tech_ddr_stratixiv IS
ctlr_init_done : OUT STD_LOGIC; ctlr_init_done : OUT STD_LOGIC;
ctlr_mosi : IN t_tech_ddr_mosi; ctlr_mosi : IN t_mem_ctlr_mosi;
ctlr_miso : OUT t_tech_ddr_miso; ctlr_miso : OUT t_mem_ctlr_miso;
-- PHY interface -- PHY interface
phy_in : IN t_tech_ddr_phy_in; phy_in : IN t_tech_ddr_phy_in;
......
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