Added new ddr versions

boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I/hdllib.cfg

+hdl_lib_name = unb1_test_ddr_MB_I
+hdl_library_clause_name = unb1_test_ddr_MB_I_lib
+hdl_lib_uses_synth = unb1_board unb1_test
+hdl_lib_uses_sim = 
+hdl_lib_excludes = ip_stratixiv_ddr3_uphy_4g_800_slave ip_stratixiv_ddr3_uphy_4g_single_rank_800_master ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave
+
+hdl_lib_technology = ip_stratixiv
+
+synth_files =
+    unb1_test_ddr_MB_I.vhd
+    
+test_bench_files = 
+    tb_unb1_test_ddr_MB_I.vhd
+
+modelsim_copy_files =
+    ../../src/hex hex
+
+synth_top_level_entity =
+
+quartus_copy_files =
+    ../../quartus/qsys_unb1_test.qsys .
+    ../../src/hex hex
+
+quartus_qsf_files =
+    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+
+quartus_sdc_files =
+    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+    
+quartus_tcl_files =
+    quartus/unb1_test_ddr_pins.tcl
+    ../../quartus/unb1_test_pins_constraints.tcl
+    
+quartus_vhdl_files = 
+
+quartus_qip_files =
+    $HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr/qsys_unb1_test/synthesis/qsys_unb1_test.qip
+    $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master.qip
+    #$RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/generated/ip_stratixiv_ddr3_uphy_4g_800_slave.qip
+
+modelsim_compile_ip_files =
+    $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
+

boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I/tb_unb1_test_ddr_MB_I.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2015
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose: Test bench for unb1_test_ddr_MB_I.
+-- Description: see tb_unb1_test
+
+
+LIBRARY IEEE, unb1_test_lib;
+USE IEEE.std_logic_1164.ALL;
+
+
+ENTITY tb_unb1_test_ddr_MB_I IS
+END tb_unb1_test_ddr_MB_I;
+
+
+ARCHITECTURE tb OF tb_unb1_test_ddr_MB_I IS
+BEGIN
+  u_tb_unb1_test : ENTITY unb1_test_lib.tb_unb1_test
+  GENERIC MAP (
+    g_design_name => "unb1_test_ddr_MB_I",
+    --g_sim_node_nr => 7 -- BN3
+    g_sim_node_nr => 0 --FN0
+  );
+END tb;