Added dp_pps to port definition

libraries/dsp/bf/src/vhdl/node_unb1_fn_bf.vhd

@@ -49,9 +49,10 @@ ENTITY node_unb1_fn_bf IS
   PORT(
     -- System
     mm_rst                  : IN  STD_LOGIC;
-    mm_clk                  : IN  STD_LOGIC;   -- 125 MHz from xo_clk PLL in SOPC system
-    dp_rst                  : IN  STD_LOGIC;
-    dp_clk                  : IN  STD_LOGIC;   -- 200 MHz from CLK system clock
+    mm_clk                  : IN  STD_LOGIC;      -- 125 MHz from xo_clk PLL in SOPC system
+    dp_rst                  : IN  STD_LOGIC;      
+    dp_clk                  : IN  STD_LOGIC;      -- 200 MHz from CLK system clock
+    dp_pps                  : IN  STD_LOGIC := '1'; -- Pulse per second 
     -- MM interface         
     -- . block generator    
     reg_diag_bg_mosi        : IN  t_mem_mosi; 
@@ -121,6 +122,7 @@ BEGIN
       mm_clk           => mm_clk, 
       dp_rst           => dp_rst, 
       dp_clk           => dp_clk,
+      en_sync          => dp_pps,
       -- MM interface
       reg_bg_ctrl_mosi => reg_diag_bg_mosi, 
       reg_bg_ctrl_miso => reg_diag_bg_miso,