add voltage sensor instantiation. Still need local trigger logic

libraries/io/fpga_sense/src/vhdl/fpga_sense.vhd

@@ -24,7 +24,7 @@
 --  
 
 
-LIBRARY IEEE, common_lib, technology_lib, tech_fpga_temp_sens_lib;
+LIBRARY IEEE, common_lib, technology_lib, tech_fpga_temp_sens_lib, tech_fpga_voltage_sens_lib;
 USE IEEE.std_logic_1164.ALL;
 USE IEEE.numeric_std.ALL;
 USE common_lib.common_pkg.ALL;
@@ -34,7 +34,7 @@ USE technology_lib.technology_pkg.ALL;
 --USE tech_temp_sense_lib.tech_temp_sense_component_pkg.ALL;
 
 
-ENTITY fpga_temp_sens IS
+ENTITY fpga_sense IS
   GENERIC (
     g_technology     : NATURAL := c_tech_select_default;
     g_sim            : BOOLEAN
@@ -46,18 +46,28 @@ ENTITY fpga_temp_sens IS
 
     start_sense : IN  STD_LOGIC;
     
-    reg_mosi    : IN  t_mem_mosi := c_mem_mosi_rst;
-    reg_miso    : OUT t_mem_miso
+    reg_temp_mosi          : IN  t_mem_mosi := c_mem_mosi_rst;
+    reg_temp_miso          : OUT t_mem_miso;
+
+    reg_voltage_store_mosi : IN  t_mem_mosi := c_mem_mosi_rst;
+    reg_voltage_store_miso : OUT t_mem_miso
   );
-END fpga_temp_sens;
+END fpga_sense;
+
 
+ARCHITECTURE str OF fpga_sense IS
 
-ARCHITECTURE str OF fpga_temp_sens IS
+  -- constants for the temperature sensor	
+  CONSTANT c_mem_reg_temp_adr_w     : NATURAL := 1;
+  CONSTANT c_mem_reg_temp_dat_w     : NATURAL := 32;
+  CONSTANT c_mem_reg_temp_nof_data  : NATURAL := 1;
+  CONSTANT c_mem_reg_temp_data : t_c_mem := (c_mem_reg_rd_latency, c_mem_reg_temp_adr_w , c_mem_reg_temp_dat_w , c_mem_reg_temp_nof_data, 'X');
 
-  CONSTANT c_mem_reg_adr_w     : NATURAL := 1;
-  CONSTANT c_mem_reg_dat_w     : NATURAL := 32;
-  CONSTANT c_mem_reg_nof_data  : NATURAL := 1;
-  CONSTANT c_mem_reg_temp_data : t_c_mem := (c_mem_reg_rd_latency, c_mem_reg_adr_w , c_mem_reg_dat_w , c_mem_reg_nof_data, 'X');
+  -- constants for the voltage sensor	
+  CONSTANT c_mem_reg_voltage_adr_w     : NATURAL := 1;
+  CONSTANT c_mem_reg_voltage_dat_w     : NATURAL := 32;
+  CONSTANT c_mem_reg_voltage_nof_data  : NATURAL := 1;
+  CONSTANT c_mem_reg_voltage_data : t_c_mem := (c_mem_reg_rd_latency, c_mem_reg_voltage_adr_w , c_mem_reg_voltage_dat_w , c_mem_reg_voltage_nof_data, 'X');
 
   SIGNAL mm_reg_temp_data : STD_LOGIC_VECTOR(c_mem_reg_dat_w-1 downto 0);
   SIGNAL temp_data        : STD_LOGIC_VECTOR(9 downto 0);
@@ -65,6 +75,8 @@ ARCHITECTURE str OF fpga_temp_sens IS
 
 BEGIN
 
+  -- temperature sensor
+
   gen_tech_fpga_temp_sens: IF g_sim=FALSE GENERATE
     u_tech_fpga_temp_sens : ENTITY tech_fpga_temp_sens_lib.tech_fpga_temp_sens
     GENERIC MAP (
@@ -88,19 +100,15 @@ BEGIN
 
   END GENERATE;
 
+  gen_no_tech_fpga_temp_sens: IF g_sim=TRUE GENERATE
                                                                                 
+    -- temp = (708 * adc)/1024 - 273 => adc = (temp + 273)*1024/708
                                                              
-  gen_no_tech_fpga_temp_sens: IF g_sim=TRUE GENERATE
-    temp_data <= RESIZE_UVEC(x"45",10);
+    temp_data <= TO_UVEC(460, temp_data'LENGTH);   -- choose temp = 45 degrees so adc temp_data = 460
+    --temp_data <= RESIZE_UVEC(x"45",10);
     mm_reg_temp_data <= RESIZE_UVEC(temp_data,c_mem_reg_dat_w);
   END GENERATE;
 
-
-
-
-
-
-
   u_reg_map : ENTITY common_lib.common_reg_r_w_dc
   GENERIC MAP (
     g_cross_clock_domain => FALSE,
@@ -117,8 +125,8 @@ BEGIN
     st_clk      => mm_clk,
 
     -- Memory Mapped Slave in mm_clk domain
-    sla_in      => reg_mosi,
-    sla_out     => reg_miso,
+    sla_in      => reg_temp_mosi,
+    sla_out     => reg_temp_miso,
 
     -- MM registers in st_clk domain
     reg_wr_arr  => OPEN,
@@ -127,4 +135,42 @@ BEGIN
     in_reg      => mm_reg_temp_data,
     out_reg     => OPEN
   );
+
+
+  -- voltage sensor
+
+  gen_tech_fpga_voltage_sens: IF g_sim=FALSE GENERATE
+    u_tech_fpga_voltage_sens : ENTITY tech_fpga_voltage_sens_lib.tech_fpga_voltage_sens
+      GENERIC MAP (
+        g_technology => g_technology
+      )
+      PORT MAP (
+        clock_clk                  => mm_clk,
+        reset_sink_reset           => mm_reset,
+        controller_csr_address     => controller_csr_address,
+        controller_csr_read        => controller_csr_read,
+        controller_csr_write       => controller_csr_write,
+        controller_csr_writedata   => controller_csr_writedata,
+        controller_csr_readdata    => controller_csr_readdata,
+        sample_store_csr_address   => reg_voltage_store_mosi.address,
+        sample_store_csr_read      => reg_voltage_store_mosi.read,
+        sample_store_csr_write     => reg_voltage_store_mosi.write,
+        sample_store_csr_writedata => reg_voltage_store_mosi.writedata,
+        sample_store_csr_readdata  => reg_voltage_store_mosi.readdata,
+        sample_store_irq_irq       => sample_store_irq_irq
+    );
+
+    PROCESS(eoc, mm_rst)
+      BEGIN
+        IF mm_rst = '1' THEN
+          mm_reg_temp_data <= (OTHERS => '0');
+        ELSIF falling_edge(eoc) THEN
+          mm_reg_temp_data <= RESIZE_UVEC(temp_data,c_mem_reg_dat_w);
+        END IF;
+    END PROCESS;
+
+  END GENERATE;
+
+
+
 END str;