Ported tb_tse.vhd and tb_tse_pkg from tse/ in $UNB to technology/tse/ in $RADIOHDL.

Only file name change, definition names need to be changed later to have prefix tech_tse_*.

libraries/technology/tse/hdllib.cfg

@@ -12,3 +12,5 @@ synth_files =
     tech_tse.vhd
 
 test_bench_files =
+    tb_tech_tse_pkg.vhd
+    tb_tech_tse.vhd

libraries/technology/tse/tb_tech_tse.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2009
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib, dp_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE common_lib.eth_layers_pkg.ALL;
+USE WORK.tse_pkg.ALL;
+USE WORK.tb_tse_pkg.ALL;
+
+
+ENTITY tb_tse IS
+  -- Test bench control parameters
+  GENERIC (
+    --   g_data_type = c_tb_tse_data_type_symbols  = 0
+    --   g_data_type = c_tb_tse_data_type_counter  = 1
+    g_data_type : NATURAL := c_tb_tse_data_type_symbols
+  );
+END tb_tse;
+
+
+ARCHITECTURE tb OF tb_tse IS
+
+  -- as 10
+  -- run 50 us
+  
+  CONSTANT sys_clk_period       : TIME := 10 ns;  -- 100 MHz
+  CONSTANT eth_clk_period       : TIME :=  8 ns;  -- 125 MHz
+  CONSTANT cable_delay          : TIME := 12 ns;
+
+  CONSTANT c_promis_en          : BOOLEAN := FALSE;
+  CONSTANT c_tx_ready_latency   : NATURAL := c_tse_tx_ready_latency;  -- 0, 1 are supported, must match TSE MAC c_tse_tx_ready_latency
+  CONSTANT c_nof_tx_not_valid   : NATURAL := 0;  -- when > 0 then pull tx valid low for c_nof_tx_not_valid beats during tx
+
+  CONSTANT c_word_align         : STD_LOGIC_VECTOR(c_eth_word_align_w-1 DOWNTO 0) := TO_UVEC(c_eth_word_align, c_eth_word_align_w);
+  CONSTANT c_dst_mac            : STD_LOGIC_VECTOR(c_eth_mac_slv'RANGE) := X"10FA01020300";
+  CONSTANT c_src_mac            : STD_LOGIC_VECTOR(c_eth_mac_slv'RANGE) := X"123456789ABC";  -- = 12-34-56-78-9A-BC
+  CONSTANT c_ethertype          : STD_LOGIC_VECTOR(c_eth_type_slv'RANGE) := X"10FA";
+  CONSTANT c_etherlen           : STD_LOGIC_VECTOR(c_eth_type_slv'RANGE) := "0000000000010000";
+
+  -- Packet headers
+  CONSTANT c_eth_header_loopback : t_eth_header := (c_word_align, c_src_mac, c_src_mac, c_ethertype);
+  CONSTANT c_eth_header_etherlen : t_eth_header := (c_word_align, c_src_mac, c_src_mac, c_etherlen);
+  
+  SIGNAL total_header_loopback   : t_eth_total_header;
+  SIGNAL total_header_etherlen   : t_eth_total_header;
+  
+  -- Clocks and reset
+  SIGNAL eth_clk           : STD_LOGIC := '0';  -- tse reference clock
+  SIGNAL sys_clk           : STD_LOGIC := '0';  -- system clock
+  SIGNAL st_clk            : STD_LOGIC;         -- stream clock
+  SIGNAL mm_clk            : STD_LOGIC;         -- memory-mapped bus clock
+  SIGNAL mm_rst            : STD_LOGIC;         -- reset synchronous with mm_clk
+
+  -- TSE MAC control interface
+  SIGNAL mm_init           : STD_LOGIC := '1';
+  SIGNAL mm_miso           : t_mem_miso;
+  SIGNAL mm_mosi           : t_mem_mosi;
+  
+  SIGNAL mm_psc_access     : STD_LOGIC;
+
+  -- TSE MAC transmit interface
+  -- . The tb is the ST source
+  SIGNAL tx_en             : STD_LOGIC := '1';
+  SIGNAL tx_siso           : t_dp_siso;
+  SIGNAL tx_sosi           : t_dp_sosi;
+  -- . MAC specific
+  SIGNAL tx_mac_in         : t_tse_tx_mac;
+  SIGNAL tx_mac_out        : t_tse_tx_mac;
+
+  -- TSE MAC receive interface
+  -- . The tb is the ST sink
+  SIGNAL rx_sosi           : t_dp_sosi;
+  SIGNAL rx_siso           : t_dp_siso;
+  -- . MAC specific
+  SIGNAL rx_mac_out        : t_tse_rx_mac;
+
+  -- TSE PHY interface
+  SIGNAL eth_txp           : STD_LOGIC;
+  SIGNAL eth_rxp           : STD_LOGIC;
+
+  SIGNAL tse_led           : t_tse_led;
+
+BEGIN
+
+  -- run 50 us
+  
+  eth_clk <= NOT eth_clk AFTER eth_clk_period/2;  -- TSE reference clock
+  sys_clk <= NOT sys_clk AFTER sys_clk_period/2;  -- System clock
+
+  mm_clk  <= sys_clk;
+  st_clk  <= sys_clk;
+  
+  -- Use signal to leave unused fields 'X'
+  total_header_loopback.eth <= c_eth_header_loopback;
+  total_header_etherlen.eth <= c_eth_header_etherlen;
+
+  p_mm_setup : PROCESS
+  BEGIN
+    mm_init  <= '1';
+    mm_mosi.wr <= '0';
+    mm_mosi.rd <= '0';
+
+    -- reset release
+    mm_rst <= '1';
+    FOR I IN 0 TO 9 LOOP WAIT UNTIL rising_edge(mm_clk); END LOOP;
+    mm_rst <= '0';
+    FOR I IN 0 TO 9 LOOP WAIT UNTIL rising_edge(mm_clk); END LOOP;
+
+    proc_tse_setup(c_promis_en, c_tse_tx_fifo_depth, c_tse_rx_fifo_depth, c_tx_ready_latency,
+                   c_src_mac, mm_psc_access,
+                   mm_clk, mm_miso, mm_mosi);
+    mm_init <= '0';
+    WAIT;
+  END PROCESS;
+
+  
+  p_ff_transmitter : PROCESS
+  BEGIN
+    -- . Avalon ST
+    tx_sosi.data  <= (OTHERS=>'0');
+    tx_sosi.valid <= '0';
+    tx_sosi.sop   <= '0';
+    tx_sosi.eop   <= '0';
+    tx_sosi.empty <= (OTHERS=>'0');
+    tx_sosi.err   <= (OTHERS=>'0');
+    -- . MAC specific
+    tx_mac_in.crc_fwd <= '0';  -- when '0' then TSE MAC generates the TX CRC field
+
+    WHILE mm_init/='0' LOOP
+      WAIT UNTIL rising_edge(st_clk);
+    END LOOP;
+    FOR I IN 0 TO 9 LOOP WAIT UNTIL rising_edge(st_clk); END LOOP;
+
+    -- Loopback txp->rxp so DST_MAC = c_src_mac to send to itself
+    
+    -- TX frame:
+    -- . I=0 is empty payload, so only 4 words of the ETH header with 46 padding zeros, so empty = 2
+    -- . For I=1 to 46 the payload length remains 46 with padding zeros, so empty = 2
+    -- . For I>46 the payload length is I and empty = 4 - (I mod 4)
+    
+--     proc_tse_tx_packet(total_header_etherlen, 16, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, tx_en, tx_siso, tx_sosi);
+--     proc_tse_tx_packet(total_header_loopback, 16, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, tx_en, tx_siso, tx_sosi);
+--     proc_tse_tx_packet(total_header_loopback, 16, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, tx_en, tx_siso, tx_sosi);
+    FOR I IN 0 TO 59 LOOP
+      proc_tse_tx_packet(total_header_loopback, I, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, tx_en, tx_siso, tx_sosi);
+    END LOOP;
+--     proc_tse_tx_packet(total_header_loopback, 100, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, tx_en, tx_siso, tx_sosi);
+--     proc_tse_tx_packet(total_header_loopback, 101, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, tx_en, tx_siso, tx_sosi);
+--     proc_tse_tx_packet(total_header_loopback, 102, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, tx_en, tx_siso, tx_sosi);
+--     proc_tse_tx_packet(total_header_loopback, 103, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, tx_en, tx_siso, tx_sosi);
+--     proc_tse_tx_packet(total_header_loopback, 1500, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, tx_en, tx_siso, tx_sosi);
+--     proc_tse_tx_packet(total_header_loopback, 1499, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, tx_en, tx_siso, tx_sosi);  -- verify st empty
+--     proc_tse_tx_packet(total_header_loopback, 1500, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, tx_en, tx_siso, tx_sosi);
+--     proc_tse_tx_packet(total_header_loopback, 1500, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, tx_en, tx_siso, tx_sosi);
+--     proc_tse_tx_packet(total_header_loopback, 1500, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, tx_en, tx_siso, tx_sosi);
+--     proc_tse_tx_packet(total_header_loopback, 1500, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, tx_en, tx_siso, tx_sosi);
+--     proc_tse_tx_packet(total_header_loopback, 1500, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, tx_en, tx_siso, tx_sosi);
+--     proc_tse_tx_packet(total_header_loopback, 1500, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, tx_en, tx_siso, tx_sosi);
+--     proc_tse_tx_packet(total_header_loopback, 1500, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, tx_en, tx_siso, tx_sosi);
+--     proc_tse_tx_packet(total_header_loopback, 1500, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, tx_en, tx_siso, tx_sosi);
+--     proc_tse_tx_packet(total_header_loopback, 1501, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, tx_en, tx_siso, tx_sosi);  -- verify c_eth_payload_max
+--     proc_tse_tx_packet(total_header_loopback,  100, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, tx_en, tx_siso, tx_sosi);
+
+    WAIT;
+  END PROCESS;
+
+  
+  p_ff_receiver : PROCESS
+  BEGIN
+    -- . Avalon ST
+    rx_siso.ready <= '0';
+
+    WHILE mm_init/='0' LOOP
+      WAIT UNTIL rising_edge(st_clk);
+    END LOOP;
+
+    -- Receive forever
+    WHILE TRUE LOOP
+      proc_tse_rx_packet(total_header_loopback, g_data_type, st_clk, rx_sosi, rx_siso);
+    END LOOP;
+
+    WAIT;
+  END PROCESS;
+
+  
+  dut : ENTITY work.tse            -- uses stratix4 architecture tse_sgmii_lvds
+  PORT MAP (
+    -- Clocks and reset
+    mm_rst         => mm_rst,
+    mm_clk         => mm_clk,
+    eth_clk        => eth_clk,
+    tx_snk_clk     => st_clk,
+    rx_src_clk     => st_clk,
+    
+    -- Memory Mapped Slave
+    mm_sla_in      => mm_mosi,
+    mm_sla_out     => mm_miso,
+    
+    -- MAC transmit interface
+    -- . ST sink
+    tx_snk_in      => tx_sosi,
+    tx_snk_out     => tx_siso,
+    -- . MAC specific
+    tx_mac_in      => tx_mac_in,
+    tx_mac_out     => tx_mac_out,
+    
+    -- MAC receive interface
+    -- . ST Source
+    rx_src_in      => rx_siso,
+    rx_src_out     => rx_sosi,
+    -- . MAC specific
+    rx_mac_out     => rx_mac_out,
+
+    -- PHY interface
+    eth_txp        => eth_txp,
+    eth_rxp        => eth_rxp,
+
+    tse_led        => tse_led
+  );
+
+  -- Loopback
+  eth_rxp <= TRANSPORT eth_txp AFTER cable_delay;
+
+END tb;