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Commit b232c8c7 authored by Eric Kooistra's avatar Eric Kooistra
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Added [section headers].

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with 154 additions and 62 deletions
...@@ -2,9 +2,8 @@ hdl_lib_name = unb1_ddr3_transpose ...@@ -2,9 +2,8 @@ hdl_lib_name = unb1_ddr3_transpose
hdl_library_clause_name = unb1_ddr3_transpose_lib hdl_library_clause_name = unb1_ddr3_transpose_lib
hdl_lib_uses_synth = common mm i2c unb1_board dp eth diagnostics ddr3 hdl_lib_uses_synth = common mm i2c unb1_board dp eth diagnostics ddr3
hdl_lib_uses_sim = hdl_lib_uses_sim =
hdl_lib_excludes = ip_stratixiv_ddr3_uphy_4g_800_slave
hdl_lib_technology = ip_stratixiv hdl_lib_technology = ip_stratixiv
hdl_lib_excludes = ip_stratixiv_ddr3_uphy_4g_800_slave
synth_files = synth_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_ddr3_transpose/sopc_unb_ddr3_transpose.vhd $HDL_BUILD_DIR/unb1/quartus/unb1_ddr3_transpose/sopc_unb_ddr3_transpose.vhd
...@@ -14,6 +13,13 @@ synth_files = ...@@ -14,6 +13,13 @@ synth_files =
test_bench_files = test_bench_files =
tb/vhdl/tb_unb1_ddr3_transpose.vhd tb/vhdl/tb_unb1_ddr3_transpose.vhd
[modelsim_project_file]
modelsim_compile_ip_files =
$RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
[quartus_project_file]
synth_top_level_entity = synth_top_level_entity =
quartus_copy_files = quartus_copy_files =
...@@ -32,7 +38,3 @@ quartus_qip_files = ...@@ -32,7 +38,3 @@ quartus_qip_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_ddr3_transpose/sopc_unb_ddr3_transpose.qip $HDL_BUILD_DIR/unb1/quartus/unb1_ddr3_transpose/sopc_unb_ddr3_transpose.qip
$RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master.qip $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master.qip
modelsim_compile_ip_files =
$RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
...@@ -3,8 +3,6 @@ hdl_library_clause_name = unb1_fn_terminal_db_lib ...@@ -3,8 +3,6 @@ hdl_library_clause_name = unb1_fn_terminal_db_lib
hdl_lib_uses_synth = common technology mm i2c unb1_board diag hdl_lib_uses_synth = common technology mm i2c unb1_board diag
hdl_lib_technology = ip_stratixiv hdl_lib_technology = ip_stratixiv
synth_top_level_entity =
synth_files = synth_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_fn_terminal_db/sopc_unb1_fn_terminal_db.vhd $HDL_BUILD_DIR/unb1/quartus/unb1_fn_terminal_db/sopc_unb1_fn_terminal_db.vhd
src/vhdl/mmm_unb1_fn_terminal_db.vhd src/vhdl/mmm_unb1_fn_terminal_db.vhd
...@@ -13,8 +11,14 @@ synth_files = ...@@ -13,8 +11,14 @@ synth_files =
test_bench_files = test_bench_files =
tb/vhdl/tb_unb1_fn_terminal_db.vhd tb/vhdl/tb_unb1_fn_terminal_db.vhd
[modelsim_project_file]
#modelsim_copy_files = src/hex hex #modelsim_copy_files = src/hex hex
[quartus_project_file]
synth_top_level_entity =
quartus_copy_files = quartus/sopc_unb1_fn_terminal_db.sopc . quartus_copy_files = quartus/sopc_unb1_fn_terminal_db.sopc .
quartus_qsf_files = quartus_qsf_files =
......
...@@ -2,7 +2,6 @@ hdl_lib_name = unb1_minimal ...@@ -2,7 +2,6 @@ hdl_lib_name = unb1_minimal
hdl_library_clause_name = unb1_minimal_lib hdl_library_clause_name = unb1_minimal_lib
hdl_lib_uses_synth = common mm unb1_board hdl_lib_uses_synth = common mm unb1_board
hdl_lib_uses_sim = hdl_lib_uses_sim =
hdl_lib_technology = ip_stratixiv hdl_lib_technology = ip_stratixiv
synth_files = synth_files =
...@@ -14,3 +13,9 @@ synth_files = ...@@ -14,3 +13,9 @@ synth_files =
test_bench_files = test_bench_files =
tb/vhdl/tb_unb1_minimal.vhd tb/vhdl/tb_unb1_minimal.vhd
[modelsim_project_file]
[quartus_project_file]
...@@ -2,7 +2,6 @@ hdl_lib_name = unb1_minimal_mm_arbiter ...@@ -2,7 +2,6 @@ hdl_lib_name = unb1_minimal_mm_arbiter
hdl_library_clause_name = unb1_minimal_mm_arbiter_lib hdl_library_clause_name = unb1_minimal_mm_arbiter_lib
hdl_lib_uses_synth = unb1_board unb1_minimal hdl_lib_uses_synth = unb1_board unb1_minimal
hdl_lib_uses_sim = hdl_lib_uses_sim =
hdl_lib_technology = ip_stratixiv hdl_lib_technology = ip_stratixiv
synth_files = synth_files =
...@@ -11,6 +10,11 @@ synth_files = ...@@ -11,6 +10,11 @@ synth_files =
test_bench_files = test_bench_files =
tb_unb1_minimal_mm_arbiter.vhd tb_unb1_minimal_mm_arbiter.vhd
[modelsim_project_file]
[quartus_project_file]
synth_top_level_entity = synth_top_level_entity =
quartus_copy_files = quartus_copy_files =
......
...@@ -2,7 +2,6 @@ hdl_lib_name = unb1_minimal_qsys ...@@ -2,7 +2,6 @@ hdl_lib_name = unb1_minimal_qsys
hdl_library_clause_name = unb1_minimal_qsys_lib hdl_library_clause_name = unb1_minimal_qsys_lib
hdl_lib_uses_synth = unb1_board unb1_minimal hdl_lib_uses_synth = unb1_board unb1_minimal
hdl_lib_uses_sim = hdl_lib_uses_sim =
hdl_lib_technology = ip_stratixiv hdl_lib_technology = ip_stratixiv
synth_files = synth_files =
...@@ -11,8 +10,10 @@ synth_files = ...@@ -11,8 +10,10 @@ synth_files =
test_bench_files = test_bench_files =
tb_unb1_minimal_qsys.vhd tb_unb1_minimal_qsys.vhd
[modelsim_project_file] [modelsim_project_file]
[quartus_project_file] [quartus_project_file]
synth_top_level_entity = synth_top_level_entity =
......
...@@ -2,7 +2,6 @@ hdl_lib_name = unb1_minimal_qsys_wo_pll ...@@ -2,7 +2,6 @@ hdl_lib_name = unb1_minimal_qsys_wo_pll
hdl_library_clause_name = unb1_minimal_qsys_wo_pll_lib hdl_library_clause_name = unb1_minimal_qsys_wo_pll_lib
hdl_lib_uses_synth = unb1_board common mm hdl_lib_uses_synth = unb1_board common mm
hdl_lib_uses_sim = hdl_lib_uses_sim =
hdl_lib_technology = ip_stratixiv hdl_lib_technology = ip_stratixiv
synth_files = synth_files =
...@@ -13,6 +12,11 @@ synth_files = ...@@ -13,6 +12,11 @@ synth_files =
test_bench_files = test_bench_files =
tb_unb1_minimal_qsys_wo_pll.vhd tb_unb1_minimal_qsys_wo_pll.vhd
[modelsim_project_file]
[quartus_project_file]
synth_top_level_entity = synth_top_level_entity =
quartus_copy_files = quartus_copy_files =
......
...@@ -2,7 +2,6 @@ hdl_lib_name = unb1_minimal_sopc ...@@ -2,7 +2,6 @@ hdl_lib_name = unb1_minimal_sopc
hdl_library_clause_name = unb1_minimal_sopc_lib hdl_library_clause_name = unb1_minimal_sopc_lib
hdl_lib_uses_synth = unb1_board unb1_minimal hdl_lib_uses_synth = unb1_board unb1_minimal
hdl_lib_uses_sim = hdl_lib_uses_sim =
hdl_lib_technology = ip_stratixiv hdl_lib_technology = ip_stratixiv
synth_files = synth_files =
...@@ -11,6 +10,11 @@ synth_files = ...@@ -11,6 +10,11 @@ synth_files =
test_bench_files = test_bench_files =
tb_unb1_minimal_sopc.vhd tb_unb1_minimal_sopc.vhd
[modelsim_project_file]
[quartus_project_file]
synth_top_level_entity = synth_top_level_entity =
quartus_copy_files = quartus_copy_files =
......
...@@ -3,8 +3,6 @@ hdl_library_clause_name = unb1_terminal_bg_mesh_db_lib ...@@ -3,8 +3,6 @@ hdl_library_clause_name = unb1_terminal_bg_mesh_db_lib
hdl_lib_uses_synth = common technology mm i2c unb1_board diag eth tech_tse hdl_lib_uses_synth = common technology mm i2c unb1_board diag eth tech_tse
hdl_lib_technology = ip_stratixiv hdl_lib_technology = ip_stratixiv
synth_top_level_entity =
synth_files = synth_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_terminal_bg_mesh_db/qsys_unb1_terminal_bg_mesh_db/synthesis/qsys_unb1_terminal_bg_mesh_db.v $HDL_BUILD_DIR/unb1/quartus/unb1_terminal_bg_mesh_db/qsys_unb1_terminal_bg_mesh_db/synthesis/qsys_unb1_terminal_bg_mesh_db.v
src/vhdl/mmm_unb1_terminal_bg_mesh_db.vhd src/vhdl/mmm_unb1_terminal_bg_mesh_db.vhd
...@@ -14,8 +12,14 @@ synth_files = ...@@ -14,8 +12,14 @@ synth_files =
test_bench_files = test_bench_files =
tb/vhdl/tb_unb1_terminal_bg_mesh_db.vhd tb/vhdl/tb_unb1_terminal_bg_mesh_db.vhd
[modelsim_project_file]
modelsim_copy_files = src/hex hex modelsim_copy_files = src/hex hex
[quartus_project_file]
synth_top_level_entity =
quartus_copy_files = quartus/qsys_unb1_terminal_bg_mesh_db.qsys . quartus_copy_files = quartus/qsys_unb1_terminal_bg_mesh_db.qsys .
src/hex hex src/hex hex
quartus_qsf_files = quartus_qsf_files =
......
...@@ -2,7 +2,6 @@ hdl_lib_name = unb1_test ...@@ -2,7 +2,6 @@ hdl_lib_name = unb1_test
hdl_library_clause_name = unb1_test_lib hdl_library_clause_name = unb1_test_lib
hdl_lib_uses_synth = common technology mm unb1_board dp eth tech_tse tr_10GbE mdio diagnostics diag io_ddr tech_ddr hdl_lib_uses_synth = common technology mm unb1_board dp eth tech_tse tr_10GbE mdio diagnostics diag io_ddr tech_ddr
hdl_lib_uses_sim = hdl_lib_uses_sim =
hdl_lib_technology = ip_stratixiv hdl_lib_technology = ip_stratixiv
synth_files = synth_files =
...@@ -15,3 +14,9 @@ synth_files = ...@@ -15,3 +14,9 @@ synth_files =
test_bench_files = test_bench_files =
tb/vhdl/tb_unb1_test.vhd tb/vhdl/tb_unb1_test.vhd
[modelsim_project_file]
[quartus_project_file]
...@@ -2,9 +2,11 @@ hdl_lib_name = unb1_test_10GbE ...@@ -2,9 +2,11 @@ hdl_lib_name = unb1_test_10GbE
hdl_library_clause_name = unb1_test_10GbE_lib hdl_library_clause_name = unb1_test_10GbE_lib
hdl_lib_uses_synth = unb1_board unb1_test hdl_lib_uses_synth = unb1_board unb1_test
hdl_lib_uses_sim = hdl_lib_uses_sim =
hdl_lib_excludes = ip_stratixiv_ddr3_uphy_4g_800_master ip_stratixiv_ddr3_uphy_4g_800_slave ip_stratixiv_ddr3_uphy_4g_single_rank_800_master ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave
hdl_lib_technology = ip_stratixiv hdl_lib_technology = ip_stratixiv
hdl_lib_excludes = ip_stratixiv_ddr3_uphy_4g_800_master
ip_stratixiv_ddr3_uphy_4g_800_slave
ip_stratixiv_ddr3_uphy_4g_single_rank_800_master
ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave
synth_files = synth_files =
unb1_test_10GbE.vhd unb1_test_10GbE.vhd
...@@ -12,9 +14,13 @@ synth_files = ...@@ -12,9 +14,13 @@ synth_files =
test_bench_files = test_bench_files =
tb_unb1_test_10GbE.vhd tb_unb1_test_10GbE.vhd
[modelsim_project_file]
modelsim_copy_files = modelsim_copy_files =
../../src/hex hex ../../src/hex hex
[quartus_project_file]
synth_top_level_entity = synth_top_level_entity =
quartus_copy_files = quartus_copy_files =
......
...@@ -2,9 +2,11 @@ hdl_lib_name = unb1_test_10GbE_tx_only ...@@ -2,9 +2,11 @@ hdl_lib_name = unb1_test_10GbE_tx_only
hdl_library_clause_name = unb1_test_10GbE_tx_only_lib hdl_library_clause_name = unb1_test_10GbE_tx_only_lib
hdl_lib_uses_synth = unb1_board unb1_test hdl_lib_uses_synth = unb1_board unb1_test
hdl_lib_uses_sim = hdl_lib_uses_sim =
hdl_lib_excludes = ip_stratixiv_ddr3_uphy_4g_800_master ip_stratixiv_ddr3_uphy_4g_800_slave ip_stratixiv_ddr3_uphy_4g_single_rank_800_master ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave
hdl_lib_technology = ip_stratixiv hdl_lib_technology = ip_stratixiv
hdl_lib_excludes = ip_stratixiv_ddr3_uphy_4g_800_master
ip_stratixiv_ddr3_uphy_4g_800_slave
ip_stratixiv_ddr3_uphy_4g_single_rank_800_master
ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave
synth_files = synth_files =
unb1_test_10GbE_tx_only.vhd unb1_test_10GbE_tx_only.vhd
...@@ -12,9 +14,13 @@ synth_files = ...@@ -12,9 +14,13 @@ synth_files =
test_bench_files = test_bench_files =
tb_unb1_test_10GbE_tx_only.vhd tb_unb1_test_10GbE_tx_only.vhd
[modelsim_project_file]
modelsim_copy_files = modelsim_copy_files =
../../src/hex hex ../../src/hex hex
[quartus_project_file]
synth_top_level_entity = synth_top_level_entity =
quartus_copy_files = quartus_copy_files =
......
...@@ -2,9 +2,11 @@ hdl_lib_name = unb1_test_1GbE ...@@ -2,9 +2,11 @@ hdl_lib_name = unb1_test_1GbE
hdl_library_clause_name = unb1_test_1GbE_lib hdl_library_clause_name = unb1_test_1GbE_lib
hdl_lib_uses_synth = unb1_board unb1_test hdl_lib_uses_synth = unb1_board unb1_test
hdl_lib_uses_sim = hdl_lib_uses_sim =
hdl_lib_excludes = ip_stratixiv_ddr3_uphy_4g_800_master ip_stratixiv_ddr3_uphy_4g_800_slave ip_stratixiv_ddr3_uphy_4g_single_rank_800_master ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave
hdl_lib_technology = ip_stratixiv hdl_lib_technology = ip_stratixiv
hdl_lib_excludes = ip_stratixiv_ddr3_uphy_4g_800_master
ip_stratixiv_ddr3_uphy_4g_800_slave
ip_stratixiv_ddr3_uphy_4g_single_rank_800_master
ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave
synth_files = synth_files =
unb1_test_1GbE.vhd unb1_test_1GbE.vhd
...@@ -12,9 +14,13 @@ synth_files = ...@@ -12,9 +14,13 @@ synth_files =
test_bench_files = test_bench_files =
tb_unb1_test_1GbE.vhd tb_unb1_test_1GbE.vhd
[modelsim_project_file]
modelsim_copy_files = modelsim_copy_files =
../../src/hex hex ../../src/hex hex
[quartus_project_file]
synth_top_level_entity = synth_top_level_entity =
quartus_copy_files = quartus_copy_files =
......
...@@ -2,9 +2,10 @@ hdl_lib_name = unb1_test_all ...@@ -2,9 +2,10 @@ hdl_lib_name = unb1_test_all
hdl_library_clause_name = unb1_test_all_lib hdl_library_clause_name = unb1_test_all_lib
hdl_lib_uses_synth = unb1_board unb1_test hdl_lib_uses_synth = unb1_board unb1_test
hdl_lib_uses_sim = hdl_lib_uses_sim =
hdl_lib_excludes = ip_stratixiv_ddr3_uphy_4g_800_slave ip_stratixiv_ddr3_uphy_4g_single_rank_800_master ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave
hdl_lib_technology = ip_stratixiv hdl_lib_technology = ip_stratixiv
hdl_lib_excludes = ip_stratixiv_ddr3_uphy_4g_800_slave
ip_stratixiv_ddr3_uphy_4g_single_rank_800_master
ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave
synth_files = synth_files =
unb1_test_all.vhd unb1_test_all.vhd
...@@ -12,9 +13,16 @@ synth_files = ...@@ -12,9 +13,16 @@ synth_files =
test_bench_files = test_bench_files =
tb_unb1_test_all.vhd tb_unb1_test_all.vhd
[modelsim_project_file]
modelsim_copy_files = modelsim_copy_files =
../../src/hex hex ../../src/hex hex
modelsim_compile_ip_files =
$RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
[quartus_project_file]
synth_top_level_entity = synth_top_level_entity =
quartus_copy_files = quartus_copy_files =
...@@ -38,6 +46,3 @@ quartus_qip_files = ...@@ -38,6 +46,3 @@ quartus_qip_files =
$RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master.qip $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master.qip
#$RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/generated/ip_stratixiv_ddr3_uphy_4g_800_slave.qip #$RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/generated/ip_stratixiv_ddr3_uphy_4g_800_slave.qip
modelsim_compile_ip_files =
$RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
...@@ -2,9 +2,10 @@ hdl_lib_name = unb1_test_ddr ...@@ -2,9 +2,10 @@ hdl_lib_name = unb1_test_ddr
hdl_library_clause_name = unb1_test_ddr_lib hdl_library_clause_name = unb1_test_ddr_lib
hdl_lib_uses_synth = unb1_board unb1_test hdl_lib_uses_synth = unb1_board unb1_test
hdl_lib_uses_sim = hdl_lib_uses_sim =
hdl_lib_excludes = ip_stratixiv_ddr3_uphy_4g_800_slave ip_stratixiv_ddr3_uphy_4g_single_rank_800_master ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave
hdl_lib_technology = ip_stratixiv hdl_lib_technology = ip_stratixiv
hdl_lib_excludes = ip_stratixiv_ddr3_uphy_4g_800_slave
ip_stratixiv_ddr3_uphy_4g_single_rank_800_master
ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave
synth_files = synth_files =
unb1_test_ddr.vhd unb1_test_ddr.vhd
...@@ -12,9 +13,16 @@ synth_files = ...@@ -12,9 +13,16 @@ synth_files =
test_bench_files = test_bench_files =
tb_unb1_test_ddr.vhd tb_unb1_test_ddr.vhd
[modelsim_project_file]
modelsim_copy_files = modelsim_copy_files =
../../src/hex hex ../../src/hex hex
modelsim_compile_ip_files =
$RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
[quartus_project_file]
synth_top_level_entity = synth_top_level_entity =
quartus_copy_files = quartus_copy_files =
...@@ -38,6 +46,3 @@ quartus_qip_files = ...@@ -38,6 +46,3 @@ quartus_qip_files =
$RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master.qip $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master.qip
#$RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/generated/ip_stratixiv_ddr3_uphy_4g_800_slave.qip #$RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/generated/ip_stratixiv_ddr3_uphy_4g_800_slave.qip
modelsim_compile_ip_files =
$RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
...@@ -2,9 +2,12 @@ hdl_lib_name = unb1_test_ddr_16g_MB_I ...@@ -2,9 +2,12 @@ hdl_lib_name = unb1_test_ddr_16g_MB_I
hdl_library_clause_name = unb1_test_ddr_16g_MB_I_lib hdl_library_clause_name = unb1_test_ddr_16g_MB_I_lib
hdl_lib_uses_synth = unb1_board unb1_test hdl_lib_uses_synth = unb1_board unb1_test
hdl_lib_uses_sim = hdl_lib_uses_sim =
hdl_lib_excludes = ip_stratixiv_ddr3_uphy_4g_800_master ip_stratixiv_ddr3_uphy_4g_800_slave ip_stratixiv_ddr3_uphy_4g_single_rank_800_master ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave
hdl_lib_technology = ip_stratixiv hdl_lib_technology = ip_stratixiv
hdl_lib_excludes = ip_stratixiv_ddr3_uphy_4g_800_master
ip_stratixiv_ddr3_uphy_4g_800_slave
ip_stratixiv_ddr3_uphy_4g_single_rank_800_master
ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave
synth_files = synth_files =
unb1_test_ddr_16g_MB_I.vhd unb1_test_ddr_16g_MB_I.vhd
...@@ -12,9 +15,16 @@ synth_files = ...@@ -12,9 +15,16 @@ synth_files =
test_bench_files = test_bench_files =
tb_unb1_test_ddr_16g_MB_I.vhd tb_unb1_test_ddr_16g_MB_I.vhd
[modelsim_project_file]
modelsim_copy_files = modelsim_copy_files =
../../src/hex hex ../../src/hex hex
modelsim_compile_ip_files =
$RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/copy_hex_files.tcl
[quartus_project_file]
synth_top_level_entity = synth_top_level_entity =
quartus_copy_files = quartus_copy_files =
...@@ -37,6 +47,3 @@ quartus_qip_files = ...@@ -37,6 +47,3 @@ quartus_qip_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_16g_MB_I/qsys_unb1_test/synthesis/qsys_unb1_test.qip $HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_16g_MB_I/qsys_unb1_test/synthesis/qsys_unb1_test.qip
$RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/generated/ip_stratixiv_ddr3_uphy_16g_dual_rank_800.qip $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/generated/ip_stratixiv_ddr3_uphy_16g_dual_rank_800.qip
modelsim_compile_ip_files =
$RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/copy_hex_files.tcl
...@@ -2,9 +2,11 @@ hdl_lib_name = unb1_test_ddr_16g_MB_II ...@@ -2,9 +2,11 @@ hdl_lib_name = unb1_test_ddr_16g_MB_II
hdl_library_clause_name = unb1_test_ddr_16g_MB_II_lib hdl_library_clause_name = unb1_test_ddr_16g_MB_II_lib
hdl_lib_uses_synth = unb1_board unb1_test hdl_lib_uses_synth = unb1_board unb1_test
hdl_lib_uses_sim = hdl_lib_uses_sim =
hdl_lib_excludes = ip_stratixiv_ddr3_uphy_4g_800_master ip_stratixiv_ddr3_uphy_4g_800_slave ip_stratixiv_ddr3_uphy_4g_single_rank_800_master ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave
hdl_lib_technology = ip_stratixiv hdl_lib_technology = ip_stratixiv
hdl_lib_excludes = ip_stratixiv_ddr3_uphy_4g_800_master
ip_stratixiv_ddr3_uphy_4g_800_slave
ip_stratixiv_ddr3_uphy_4g_single_rank_800_master
ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave
synth_files = synth_files =
unb1_test_ddr_16g_MB_II.vhd unb1_test_ddr_16g_MB_II.vhd
...@@ -12,9 +14,16 @@ synth_files = ...@@ -12,9 +14,16 @@ synth_files =
test_bench_files = test_bench_files =
tb_unb1_test_ddr_16g_MB_II.vhd tb_unb1_test_ddr_16g_MB_II.vhd
[modelsim_project_file]
modelsim_copy_files = modelsim_copy_files =
../../src/hex hex ../../src/hex hex
modelsim_compile_ip_files =
$RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/copy_hex_files.tcl
[quartus_project_file]
synth_top_level_entity = synth_top_level_entity =
quartus_copy_files = quartus_copy_files =
...@@ -37,6 +46,3 @@ quartus_qip_files = ...@@ -37,6 +46,3 @@ quartus_qip_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_16g_MB_II/qsys_unb1_test/synthesis/qsys_unb1_test.qip $HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_16g_MB_II/qsys_unb1_test/synthesis/qsys_unb1_test.qip
$RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/generated/ip_stratixiv_ddr3_uphy_16g_dual_rank_800.qip $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/generated/ip_stratixiv_ddr3_uphy_16g_dual_rank_800.qip
modelsim_compile_ip_files =
$RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/copy_hex_files.tcl
...@@ -2,22 +2,28 @@ hdl_lib_name = unb1_test_ddr_16g_MB_I_II ...@@ -2,22 +2,28 @@ hdl_lib_name = unb1_test_ddr_16g_MB_I_II
hdl_library_clause_name = unb1_test_ddr_16g_MB_I_II_lib hdl_library_clause_name = unb1_test_ddr_16g_MB_I_II_lib
hdl_lib_uses_synth = unb1_board unb1_test hdl_lib_uses_synth = unb1_board unb1_test
hdl_lib_uses_sim = hdl_lib_uses_sim =
hdl_lib_technology = ip_stratixiv
hdl_lib_excludes = ip_stratixiv_ddr3_uphy_4g_single_rank_800_master hdl_lib_excludes = ip_stratixiv_ddr3_uphy_4g_single_rank_800_master
ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave
ip_stratixiv_ddr3_uphy_4g_800_master ip_stratixiv_ddr3_uphy_4g_800_master
ip_stratixiv_ddr3_uphy_4g_800_slave ip_stratixiv_ddr3_uphy_4g_800_slave
hdl_lib_technology = ip_stratixiv
synth_files = synth_files =
unb1_test_ddr_16g_MB_I_II.vhd unb1_test_ddr_16g_MB_I_II.vhd
test_bench_files = test_bench_files =
tb_unb1_test_ddr_16g_MB_I_II.vhd tb_unb1_test_ddr_16g_MB_I_II.vhd
[modelsim_project_file]
modelsim_copy_files = modelsim_copy_files =
../../src/hex hex ../../src/hex hex
modelsim_compile_ip_files =
$RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/copy_hex_files.tcl
[quartus_project_file]
synth_top_level_entity = synth_top_level_entity =
quartus_copy_files = quartus_copy_files =
...@@ -40,6 +46,3 @@ quartus_qip_files = ...@@ -40,6 +46,3 @@ quartus_qip_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_16g_MB_I_II/qsys_unb1_test/synthesis/qsys_unb1_test.qip $HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_16g_MB_I_II/qsys_unb1_test/synthesis/qsys_unb1_test.qip
$RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/generated/ip_stratixiv_ddr3_uphy_16g_dual_rank_800.qip $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/generated/ip_stratixiv_ddr3_uphy_16g_dual_rank_800.qip
modelsim_compile_ip_files =
$RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/copy_hex_files.tcl
...@@ -2,9 +2,11 @@ hdl_lib_name = unb1_test_ddr_MB_I ...@@ -2,9 +2,11 @@ hdl_lib_name = unb1_test_ddr_MB_I
hdl_library_clause_name = unb1_test_ddr_MB_I_lib hdl_library_clause_name = unb1_test_ddr_MB_I_lib
hdl_lib_uses_synth = unb1_board unb1_test hdl_lib_uses_synth = unb1_board unb1_test
hdl_lib_uses_sim = hdl_lib_uses_sim =
hdl_lib_excludes = ip_stratixiv_ddr3_uphy_16g_dual_rank_800 ip_stratixiv_ddr3_uphy_4g_800_slave ip_stratixiv_ddr3_uphy_4g_800_master ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave
hdl_lib_technology = ip_stratixiv hdl_lib_technology = ip_stratixiv
hdl_lib_excludes = ip_stratixiv_ddr3_uphy_16g_dual_rank_800
ip_stratixiv_ddr3_uphy_4g_800_slave
ip_stratixiv_ddr3_uphy_4g_800_master
ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave
synth_files = synth_files =
unb1_test_ddr_MB_I.vhd unb1_test_ddr_MB_I.vhd
...@@ -12,9 +14,16 @@ synth_files = ...@@ -12,9 +14,16 @@ synth_files =
test_bench_files = test_bench_files =
tb_unb1_test_ddr_MB_I.vhd tb_unb1_test_ddr_MB_I.vhd
[modelsim_project_file]
modelsim_copy_files = modelsim_copy_files =
../../src/hex hex ../../src/hex hex
modelsim_compile_ip_files =
$RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
[quartus_project_file]
synth_top_level_entity = synth_top_level_entity =
quartus_copy_files = quartus_copy_files =
...@@ -37,6 +46,3 @@ quartus_qip_files = ...@@ -37,6 +46,3 @@ quartus_qip_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_MB_I/qsys_unb1_test/synthesis/qsys_unb1_test.qip $HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_MB_I/qsys_unb1_test/synthesis/qsys_unb1_test.qip
$RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
modelsim_compile_ip_files =
$RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
...@@ -2,9 +2,12 @@ hdl_lib_name = unb1_test_ddr_MB_II ...@@ -2,9 +2,12 @@ hdl_lib_name = unb1_test_ddr_MB_II
hdl_library_clause_name = unb1_test_ddr_MB_II_lib hdl_library_clause_name = unb1_test_ddr_MB_II_lib
hdl_lib_uses_synth = unb1_board unb1_test hdl_lib_uses_synth = unb1_board unb1_test
hdl_lib_uses_sim = hdl_lib_uses_sim =
hdl_lib_excludes = ip_stratixiv_ddr3_uphy_16g_dual_rank_800 ip_stratixiv_ddr3_uphy_4g_800_slave ip_stratixiv_ddr3_uphy_4g_800_master ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave
hdl_lib_technology = ip_stratixiv hdl_lib_technology = ip_stratixiv
hdl_lib_excludes = ip_stratixiv_ddr3_uphy_16g_dual_rank_800
ip_stratixiv_ddr3_uphy_4g_800_slave
ip_stratixiv_ddr3_uphy_4g_800_master
ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave
synth_files = synth_files =
unb1_test_ddr_MB_II.vhd unb1_test_ddr_MB_II.vhd
...@@ -12,9 +15,16 @@ synth_files = ...@@ -12,9 +15,16 @@ synth_files =
test_bench_files = test_bench_files =
tb_unb1_test_ddr_MB_II.vhd tb_unb1_test_ddr_MB_II.vhd
[modelsim_project_file]
modelsim_copy_files = modelsim_copy_files =
../../src/hex hex ../../src/hex hex
modelsim_compile_ip_files =
$RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
[quartus_project_file]
synth_top_level_entity = synth_top_level_entity =
quartus_copy_files = quartus_copy_files =
...@@ -37,6 +47,3 @@ quartus_qip_files = ...@@ -37,6 +47,3 @@ quartus_qip_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_MB_II/qsys_unb1_test/synthesis/qsys_unb1_test.qip $HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_MB_II/qsys_unb1_test/synthesis/qsys_unb1_test.qip
$RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
modelsim_compile_ip_files =
$RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
...@@ -2,22 +2,27 @@ hdl_lib_name = unb1_test_ddr_MB_I_II ...@@ -2,22 +2,27 @@ hdl_lib_name = unb1_test_ddr_MB_I_II
hdl_library_clause_name = unb1_test_ddr_MB_I_II_lib hdl_library_clause_name = unb1_test_ddr_MB_I_II_lib
hdl_lib_uses_synth = unb1_board unb1_test hdl_lib_uses_synth = unb1_board unb1_test
hdl_lib_uses_sim = hdl_lib_uses_sim =
hdl_lib_technology = ip_stratixiv
hdl_lib_excludes = ip_stratixiv_ddr3_uphy_16g_dual_rank_800 hdl_lib_excludes = ip_stratixiv_ddr3_uphy_16g_dual_rank_800
ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave
ip_stratixiv_ddr3_uphy_4g_800_master ip_stratixiv_ddr3_uphy_4g_800_master
ip_stratixiv_ddr3_uphy_4g_800_slave ip_stratixiv_ddr3_uphy_4g_800_slave
hdl_lib_technology = ip_stratixiv
synth_files = synth_files =
unb1_test_ddr_MB_I_II.vhd unb1_test_ddr_MB_I_II.vhd
test_bench_files = test_bench_files =
tb_unb1_test_ddr_MB_I_II.vhd tb_unb1_test_ddr_MB_I_II.vhd
[modelsim_project_file]
modelsim_copy_files = modelsim_copy_files =
../../src/hex hex ../../src/hex hex
modelsim_compile_ip_files =
$RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
[quartus_project_file]
synth_top_level_entity = synth_top_level_entity =
quartus_copy_files = quartus_copy_files =
...@@ -40,6 +45,3 @@ quartus_qip_files = ...@@ -40,6 +45,3 @@ quartus_qip_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_MB_I_II/qsys_unb1_test/synthesis/qsys_unb1_test.qip $HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_MB_I_II/qsys_unb1_test/synthesis/qsys_unb1_test.qip
$RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
modelsim_compile_ip_files =
$RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
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