diff --git a/applications/aartfaac/designs/aartfaac_bn_sdo/hdllib.cfg b/applications/aartfaac/designs/aartfaac_bn_sdo/hdllib.cfg
index 7d0c5616000ed794a30da54944229b898d38fbe4..d55c7bbfb80f46144cdd66816ee8cbac8861cab8 100644
--- a/applications/aartfaac/designs/aartfaac_bn_sdo/hdllib.cfg
+++ b/applications/aartfaac/designs/aartfaac_bn_sdo/hdllib.cfg
@@ -2,18 +2,8 @@ hdl_lib_name = aartfaac_bn_sdo
hdl_library_clause_name = aartfaac_bn_sdo_lib
hdl_lib_uses_synth = unb1_board rsp_terminal ss
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_stratixiv
-synth_top_level_entity =
-
-quartus_copy_files =
- src/quartus/sopc_aartfaac_bn_sdo.sopc .
- src/hex/ hex
-
-modelsim_copy_files =
- src/hex/ hex
-
synth_files =
$HDL_BUILD_DIR/unb1/quartus/aartfaac_bn_sdo/sopc_aartfaac_bn_sdo.vhd
src/vhdl/mmm_aartfaac_bn_sdo.vhd
@@ -23,6 +13,19 @@ synth_files =
test_bench_files =
tb/vhdl/tb_aartfaac_bn_sdo.vhd
+
+[modelsim_project_file]
+modelsim_copy_files =
+ src/hex/ hex
+
+
+[quartus_project_file]
+synth_top_level_entity =
+
+quartus_copy_files =
+ src/quartus/sopc_aartfaac_bn_sdo.sopc .
+ src/hex/ hex
+
quartus_qsf_files =
$RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
diff --git a/applications/aartfaac/designs/aartfaac_fn_sdo/hdllib.cfg b/applications/aartfaac/designs/aartfaac_fn_sdo/hdllib.cfg
index 67c77bf83ab7ae039b1971eea85e2ec9ce60a19b..53620291b83132ac5c253ff64c6747fc5aed9535 100644
--- a/applications/aartfaac/designs/aartfaac_fn_sdo/hdllib.cfg
+++ b/applications/aartfaac/designs/aartfaac_fn_sdo/hdllib.cfg
@@ -2,16 +2,8 @@ hdl_lib_name = aartfaac_fn_sdo
hdl_library_clause_name = aartfaac_fn_sdo_lib
hdl_lib_uses_synth = unb1_board tr_xaui tr_10GbE tr_nonbonded
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_stratixiv
-synth_top_level_entity =
-
-quartus_copy_files =
- src/quartus/sopc_aartfaac_fn_sdo.sopc .
-
-modelsim_copy_files =
-
synth_files =
$HDL_BUILD_DIR/unb1/quartus/aartfaac_fn_sdo/sopc_aartfaac_fn_sdo.vhd
src/vhdl/mmm_aartfaac_fn_sdo.vhd
@@ -19,6 +11,17 @@ synth_files =
test_bench_files =
+
+[modelsim_project_file]
+modelsim_copy_files =
+
+
+[quartus_project_file]
+synth_top_level_entity =
+
+quartus_copy_files =
+ src/quartus/sopc_aartfaac_fn_sdo.sopc .
+
quartus_qsf_files =
$RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
diff --git a/applications/aartfaac/libraries/rsp_serdes/hdllib.cfg b/applications/aartfaac/libraries/rsp_serdes/hdllib.cfg
index 6b32076dd56ebf155659d8c74ca258d595517f56..2279be29254cc5a89ab02993501d3f65affab0e9 100644
--- a/applications/aartfaac/libraries/rsp_serdes/hdllib.cfg
+++ b/applications/aartfaac/libraries/rsp_serdes/hdllib.cfg
@@ -2,7 +2,6 @@ hdl_lib_name = rsp_serdes
hdl_library_clause_name = rsp_serdes_lib
hdl_lib_uses_synth =
hdl_lib_uses_sim = common dp
-
hdl_lib_technology =
synth_files =
@@ -11,3 +10,9 @@ synth_files =
test_bench_files =
$SVN/Aartfaac/trunk/Firmware/modules/rsp_serdes/tb/vhdl/tb_rsp_serdes.vhd
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+
diff --git a/applications/aartfaac/libraries/rsp_terminal/hdllib.cfg b/applications/aartfaac/libraries/rsp_terminal/hdllib.cfg
index 647500e0a04504e4c504bb449eb52d210623733f..b185aeb6e35f4b3d25e3a31c17e98b1fdab3bd3c 100644
--- a/applications/aartfaac/libraries/rsp_terminal/hdllib.cfg
+++ b/applications/aartfaac/libraries/rsp_terminal/hdllib.cfg
@@ -18,5 +18,11 @@ test_bench_files =
$SVN/Aartfaac/trunk/Firmware/modules/rsp_terminal/tb/vhdl/tb_rsp_terminal.vhd
$SVN/Aartfaac/trunk/Firmware/modules/rsp_terminal/tb/vhdl/tb_tb_rsp_terminal.vhd
+
+[modelsim_project_file]
modelsim_copy_files =
$SVN/Aartfaac/trunk/Firmware/modules/rsp_terminal/src/hex/ hex
+
+
+[quartus_project_file]
+
diff --git a/applications/aartfaac/systems/aartfaac_sdo/hdllib.cfg b/applications/aartfaac/systems/aartfaac_sdo/hdllib.cfg
index 22b951949d8884df5dfd6593a1efa242e6e8e357..8b347b977e1de9e9c9bf841e4bf3d156fadd0e3a 100644
--- a/applications/aartfaac/systems/aartfaac_sdo/hdllib.cfg
+++ b/applications/aartfaac/systems/aartfaac_sdo/hdllib.cfg
@@ -5,17 +5,19 @@ hdl_lib_uses_sim = aartfaac_bn_sdo aartfaac_fn_sdo
hdl_lib_technology = ip_stratixiv
-synth_top_level_entity =
-
-quartus_copy_files =
-
-modelsim_copy_files =
-
synth_files =
test_bench_files =
tb/vhdl/tb_aartfaac_sdo.vhd
+
+[modelsim_project_file]
+modelsim_copy_files =
+
+
+[quartus_project_file]
+synth_top_level_entity =
+quartus_copy_files =
quartus_qsf_files =
quartus_tcl_files =
quartus_vhdl_files =
diff --git a/applications/apertif/designs/apertif_unb1_bn_filterbank/hdllib.cfg b/applications/apertif/designs/apertif_unb1_bn_filterbank/hdllib.cfg
index 8f9b5b52c313d97fe61c0c6ab1380f2a1aa7b766..cb4aa78ebe1f7986d981de95e70e64a3b9ebe0cf 100644
--- a/applications/apertif/designs/apertif_unb1_bn_filterbank/hdllib.cfg
+++ b/applications/apertif/designs/apertif_unb1_bn_filterbank/hdllib.cfg
@@ -3,8 +3,6 @@ hdl_library_clause_name = apertif_unb1_bn_filterbank_lib
hdl_lib_uses_synth = common technology tech_mac_10g tr_10GbE mm i2c unb1_board bf wpfb aduh reorder
hdl_lib_technology = ip_stratixiv
-synth_top_level_entity =
-
synth_files =
$RADIOHDL/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_pkg.vhd
$RADIOHDL/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_input.vhd
@@ -18,10 +16,16 @@ synth_files =
test_bench_files =
tb/vhdl/tb_apertif_unb1_bn_filterbank.vhd
+
+[modelsim_project_file]
modelsim_copy_files = src/hex hex
$RADIOHDL/libraries/io/i2c/tb/data data
$RADIOHDL/libraries/base/diag/src/data data
+
+[quartus_project_file]
+synth_top_level_entity =
+
quartus_copy_files = quartus/sopc_apertif_unb1_bn_filterbank.sopc .
src/hex hex
$RADIOHDL/libraries/io/i2c/tb/data data
diff --git a/applications/apertif/designs/apertif_unb1_cor_mesh_ref/hdllib.cfg b/applications/apertif/designs/apertif_unb1_cor_mesh_ref/hdllib.cfg
index 8c1aaf2e4e9f6f246acb664e3bddca321f19b24e..ae598d2140f2547dfe3bfc63640bd73cfe60d04a 100644
--- a/applications/apertif/designs/apertif_unb1_cor_mesh_ref/hdllib.cfg
+++ b/applications/apertif/designs/apertif_unb1_cor_mesh_ref/hdllib.cfg
@@ -3,8 +3,6 @@ hdl_library_clause_name = apertif_unb1_cor_mesh_ref_lib
hdl_lib_uses_synth = common technology mm i2c unb1_board diag eth tech_tse reorder apertif
hdl_lib_technology = ip_stratixiv
-synth_top_level_entity =
-
synth_files =
$HDL_BUILD_DIR/unb1/quartus/apertif_unb1_cor_mesh_ref/qsys_apertif_unb1_cor_mesh_ref/synthesis/qsys_apertif_unb1_cor_mesh_ref.v
src/vhdl/mmm_apertif_unb1_cor_mesh_ref.vhd
@@ -13,9 +11,15 @@ synth_files =
test_bench_files =
tb/vhdl/tb_apertif_unb1_cor_mesh_ref.vhd
+
+[modelsim_project_file]
modelsim_copy_files = src/hex hex
+
+[quartus_project_file]
+synth_top_level_entity =
+
quartus_copy_files = quartus/qsys_apertif_unb1_cor_mesh_ref.qsys .
src/hex hex
quartus_qsf_files =
diff --git a/applications/apertif/designs/apertif_unb1_correlator/hdllib.cfg b/applications/apertif/designs/apertif_unb1_correlator/hdllib.cfg
index 9f6ed50ebedc277a8a4e36f13bad4342d31a42ae..f7c3b817e09af5338aac16f846573f52d9e980c6 100644
--- a/applications/apertif/designs/apertif_unb1_correlator/hdllib.cfg
+++ b/applications/apertif/designs/apertif_unb1_correlator/hdllib.cfg
@@ -2,19 +2,8 @@ hdl_lib_name = apertif_unb1_correlator
hdl_library_clause_name = apertif_unb1_correlator_lib
hdl_lib_uses_synth = common mm dp i2c unb1_board tr_10GbE correlator diag rTwoSDF wpfb st filter fft apertif bf
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_stratixiv
-synth_top_level_entity =
-
-quartus_copy_files =
- quartus/qsys_apertif_unb1_correlator.qsys .
- quartus/sopc_apertif_unb1_correlator.sopc .
- src/hex/ hex
-
-modelsim_copy_files =
- src/hex hex
-
synth_files =
$HDL_BUILD_DIR/unb1/quartus/apertif_unb1_correlator/qsys_apertif_unb1_correlator/synthesis/qsys_apertif_unb1_correlator.v
$HDL_BUILD_DIR/unb1/quartus/apertif_unb1_correlator/sopc_apertif_unb1_correlator.vhd
@@ -25,6 +14,20 @@ synth_files =
test_bench_files =
tb/vhdl/tb_apertif_unb1_correlator.vhd
+
+[modelsim_project_file]
+modelsim_copy_files =
+ src/hex hex
+
+
+[quartus_project_file]
+synth_top_level_entity =
+
+quartus_copy_files =
+ quartus/qsys_apertif_unb1_correlator.qsys .
+ quartus/sopc_apertif_unb1_correlator.sopc .
+ src/hex/ hex
+
quartus_qsf_files =
$RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
diff --git a/applications/apertif/designs/apertif_unb1_correlator/revisions/apertif_unb1_correlator_filter/hdllib.cfg b/applications/apertif/designs/apertif_unb1_correlator/revisions/apertif_unb1_correlator_filter/hdllib.cfg
index 283a945ea46f5456cc80bcdda08646535a54764f..a58dc6689f6401cca0ae81b36b08f87c1cb18424 100644
--- a/applications/apertif/designs/apertif_unb1_correlator/revisions/apertif_unb1_correlator_filter/hdllib.cfg
+++ b/applications/apertif/designs/apertif_unb1_correlator/revisions/apertif_unb1_correlator_filter/hdllib.cfg
@@ -2,18 +2,8 @@ hdl_lib_name = apertif_unb1_correlator_filter
hdl_library_clause_name = apertif_unb1_correlator_filter_lib
hdl_lib_uses_synth = common mm dp i2c unb1_board tr_10GbE correlator diag rTwoSDF wpfb st filter fft apertif bf
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_stratixiv
-synth_top_level_entity =
-
-quartus_copy_files =
- ../../quartus/qsys_apertif_unb1_correlator.qsys .
- ../../src/hex/ hex
-
-modelsim_copy_files =
- ../../src/hex hex
-
synth_files =
$HDL_BUILD_DIR/unb1/quartus/apertif_unb1_correlator_filter/qsys_apertif_unb1_correlator/synthesis/qsys_apertif_unb1_correlator.v
../../src/vhdl/apertif_unb1_correlator_pkg.vhd
@@ -30,6 +20,19 @@ synth_files =
test_bench_files =
tb_apertif_unb1_correlator_filter.vhd
+
+[modelsim_project_file]
+modelsim_copy_files =
+ ../../src/hex hex
+
+
+[quartus_project_file]
+synth_top_level_entity =
+
+quartus_copy_files =
+ ../../quartus/qsys_apertif_unb1_correlator.qsys .
+ ../../src/hex/ hex
+
quartus_qsf_files =
$RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
diff --git a/applications/apertif/designs/apertif_unb1_correlator/revisions/apertif_unb1_correlator_full/hdllib.cfg b/applications/apertif/designs/apertif_unb1_correlator/revisions/apertif_unb1_correlator_full/hdllib.cfg
index 2bee6a247b84c3ea63150790a06e47e922b1a85b..0e41ff9d568abc56084d13f5afd73c5ce31042cc 100644
--- a/applications/apertif/designs/apertif_unb1_correlator/revisions/apertif_unb1_correlator_full/hdllib.cfg
+++ b/applications/apertif/designs/apertif_unb1_correlator/revisions/apertif_unb1_correlator_full/hdllib.cfg
@@ -2,18 +2,8 @@ hdl_lib_name = apertif_unb1_correlator_full
hdl_library_clause_name = apertif_unb1_correlator_full_lib
hdl_lib_uses_synth = common mm dp i2c unb1_board tr_10GbE correlator diag rTwoSDF wpfb st filter fft apertif bf
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_stratixiv
-synth_top_level_entity =
-
-quartus_copy_files =
- ../../quartus/qsys_apertif_unb1_correlator.qsys .
- ../../src/hex/ hex
-
-modelsim_copy_files =
- ../../src/hex hex
-
synth_files =
$HDL_BUILD_DIR/unb1/quartus/apertif_unb1_correlator_full/qsys_apertif_unb1_correlator/synthesis/qsys_apertif_unb1_correlator.v
../../src/vhdl/apertif_unb1_correlator_pkg.vhd
@@ -30,6 +20,19 @@ synth_files =
test_bench_files =
tb_apertif_unb1_correlator_full.vhd
+
+[modelsim_project_file]
+modelsim_copy_files =
+ ../../src/hex hex
+
+
+[quartus_project_file]
+synth_top_level_entity =
+
+quartus_copy_files =
+ ../../quartus/qsys_apertif_unb1_correlator.qsys .
+ ../../src/hex/ hex
+
quartus_qsf_files =
$RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
diff --git a/applications/apertif/designs/apertif_unb1_correlator/revisions/apertif_unb1_correlator_lite/hdllib.cfg b/applications/apertif/designs/apertif_unb1_correlator/revisions/apertif_unb1_correlator_lite/hdllib.cfg
index 0a2932a8a61a8c867fb0093af1ba07331ab602ca..d8f7ff437a48eba9bfc4611ed89f82b413ab0832 100644
--- a/applications/apertif/designs/apertif_unb1_correlator/revisions/apertif_unb1_correlator_lite/hdllib.cfg
+++ b/applications/apertif/designs/apertif_unb1_correlator/revisions/apertif_unb1_correlator_lite/hdllib.cfg
@@ -2,19 +2,8 @@ hdl_lib_name = apertif_unb1_correlator_lite
hdl_library_clause_name = apertif_unb1_correlator_lite_lib
hdl_lib_uses_synth = common mm dp i2c unb1_board tr_10GbE correlator diag rTwoSDF wpfb st filter fft apertif bf
hdl_lib_uses_sim = apertif_unb1_fn_bf_emu
-
hdl_lib_technology = ip_stratixiv
-synth_top_level_entity =
-
-quartus_copy_files =
- ../../quartus/qsys_apertif_unb1_correlator.qsys .
- ../../src/hex/ hex
-
-modelsim_copy_files =
- ../../src/hex hex
- ../../../apertif_unb1_fn_bf_emu/src/hex hex
-
synth_files =
$HDL_BUILD_DIR/unb1/quartus/apertif_unb1_correlator_lite/qsys_apertif_unb1_correlator/synthesis/qsys_apertif_unb1_correlator.v
../../src/vhdl/apertif_unb1_correlator_pkg.vhd
@@ -32,6 +21,20 @@ synth_files =
test_bench_files =
tb_apertif_unb1_correlator_lite.vhd
+
+[modelsim_project_file]
+modelsim_copy_files =
+ ../../src/hex hex
+ ../../../apertif_unb1_fn_bf_emu/src/hex hex
+
+
+[quartus_project_file]
+synth_top_level_entity =
+
+quartus_copy_files =
+ ../../quartus/qsys_apertif_unb1_correlator.qsys .
+ ../../src/hex/ hex
+
quartus_qsf_files =
$RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
diff --git a/applications/apertif/designs/apertif_unb1_correlator/revisions/apertif_unb1_correlator_lite_bg/hdllib.cfg b/applications/apertif/designs/apertif_unb1_correlator/revisions/apertif_unb1_correlator_lite_bg/hdllib.cfg
index bd4af0a284c57b07125d33b6a21e109fd2c2960d..8da3000e2e2bb6e7a51cad1ac511be6d722f7b84 100644
--- a/applications/apertif/designs/apertif_unb1_correlator/revisions/apertif_unb1_correlator_lite_bg/hdllib.cfg
+++ b/applications/apertif/designs/apertif_unb1_correlator/revisions/apertif_unb1_correlator_lite_bg/hdllib.cfg
@@ -2,18 +2,8 @@ hdl_lib_name = apertif_unb1_correlator_lite_bg
hdl_library_clause_name = apertif_unb1_correlator_lite_bg_lib
hdl_lib_uses_synth = common mm dp i2c unb1_board tr_10GbE correlator diag rTwoSDF wpfb st filter fft apertif bf
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_stratixiv
-synth_top_level_entity =
-
-quartus_copy_files =
- ../../quartus/qsys_apertif_unb1_correlator.qsys .
- ../../src/hex/ hex
-
-modelsim_copy_files =
- ../../src/hex hex
-
synth_files =
$HDL_BUILD_DIR/unb1/quartus/apertif_unb1_correlator_lite_bg/qsys_apertif_unb1_correlator/synthesis/qsys_apertif_unb1_correlator.v
../../src/vhdl/apertif_unb1_correlator_pkg.vhd
@@ -32,6 +22,19 @@ test_bench_files =
tb_apertif_unb1_correlator_lite_bg.vhd
../../tb/vhdl/tb_apertif_unb1_correlator_output_framer.vhd
+
+[modelsim_project_file]
+modelsim_copy_files =
+ ../../src/hex hex
+
+
+[quartus_project_file]
+synth_top_level_entity =
+
+quartus_copy_files =
+ ../../quartus/qsys_apertif_unb1_correlator.qsys .
+ ../../src/hex/ hex
+
quartus_qsf_files =
$RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
diff --git a/applications/apertif/designs/apertif_unb1_correlator/revisions/apertif_unb1_correlator_lite_bg_8/hdllib.cfg b/applications/apertif/designs/apertif_unb1_correlator/revisions/apertif_unb1_correlator_lite_bg_8/hdllib.cfg
index 117a3279aac6237d09f93f23c2d397d30cff1302..65e579b6c263b848bbf7a69a62020632d8c2e517 100644
--- a/applications/apertif/designs/apertif_unb1_correlator/revisions/apertif_unb1_correlator_lite_bg_8/hdllib.cfg
+++ b/applications/apertif/designs/apertif_unb1_correlator/revisions/apertif_unb1_correlator_lite_bg_8/hdllib.cfg
@@ -2,18 +2,8 @@ hdl_lib_name = apertif_unb1_correlator_lite_bg_8
hdl_library_clause_name = apertif_unb1_correlator_lite_bg_8_lib
hdl_lib_uses_synth = common mm dp i2c unb1_board tr_10GbE correlator diag rTwoSDF wpfb st filter fft apertif bf
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_stratixiv
-synth_top_level_entity =
-
-quartus_copy_files =
- ../../quartus/qsys_apertif_unb1_correlator.qsys .
- ../../src/hex/ hex
-
-modelsim_copy_files =
- ../../src/hex hex
-
synth_files =
$HDL_BUILD_DIR/unb1/quartus/apertif_unb1_correlator_lite_bg_8/qsys_apertif_unb1_correlator/synthesis/qsys_apertif_unb1_correlator.v
../../src/vhdl/apertif_unb1_correlator_pkg.vhd
@@ -32,6 +22,19 @@ test_bench_files =
tb_apertif_unb1_correlator_lite_bg_8.vhd
../../tb/vhdl/tb_apertif_unb1_correlator_output_framer.vhd
+
+[modelsim_project_file]
+modelsim_copy_files =
+ ../../src/hex hex
+
+
+[quartus_project_file]
+synth_top_level_entity =
+
+quartus_copy_files =
+ ../../quartus/qsys_apertif_unb1_correlator.qsys .
+ ../../src/hex/ hex
+
quartus_qsf_files =
$RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
diff --git a/applications/apertif/designs/apertif_unb1_correlator/revisions/apertif_unb1_correlator_mesh_distr_ref/hdllib.cfg b/applications/apertif/designs/apertif_unb1_correlator/revisions/apertif_unb1_correlator_mesh_distr_ref/hdllib.cfg
index 5d03c0695477e35ce027550409afacd9ebe2d13e..8710354f191c7581dc1a1156eb6cfd60a1547fae 100644
--- a/applications/apertif/designs/apertif_unb1_correlator/revisions/apertif_unb1_correlator_mesh_distr_ref/hdllib.cfg
+++ b/applications/apertif/designs/apertif_unb1_correlator/revisions/apertif_unb1_correlator_mesh_distr_ref/hdllib.cfg
@@ -2,18 +2,8 @@ hdl_lib_name = apertif_unb1_correlator_mesh_distr_ref
hdl_library_clause_name = apertif_unb1_correlator_mesh_distr_ref_lib
hdl_lib_uses_synth = common mm dp i2c unb1_board tr_10GbE correlator diag rTwoSDF wpfb st filter fft apertif bf
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_stratixiv
-synth_top_level_entity =
-
-quartus_copy_files =
- ../../quartus/qsys_apertif_unb1_correlator.qsys .
- ../../src/hex/ hex
-
-modelsim_copy_files =
- ../../src/hex hex
-
synth_files =
$HDL_BUILD_DIR/unb1/quartus/apertif_unb1_correlator_mesh_distr_ref/qsys_apertif_unb1_correlator/synthesis/qsys_apertif_unb1_correlator.v
../../src/vhdl/apertif_unb1_correlator_pkg.vhd
@@ -30,6 +20,19 @@ synth_files =
test_bench_files =
tb_apertif_unb1_correlator_mesh_distr_ref.vhd
+
+[modelsim_project_file]
+modelsim_copy_files =
+ ../../src/hex hex
+
+
+[quartus_project_file]
+synth_top_level_entity =
+
+quartus_copy_files =
+ ../../quartus/qsys_apertif_unb1_correlator.qsys .
+ ../../src/hex/ hex
+
quartus_qsf_files =
$RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
diff --git a/applications/apertif/designs/apertif_unb1_correlator/revisions/apertif_unb1_correlator_mesh_ref/hdllib.cfg b/applications/apertif/designs/apertif_unb1_correlator/revisions/apertif_unb1_correlator_mesh_ref/hdllib.cfg
index bba6d68d45cad3ee4643f109346542b87545ef5c..5f6dc0b0d7fde6a725a67d9b8cbc556cfd6d0f9c 100644
--- a/applications/apertif/designs/apertif_unb1_correlator/revisions/apertif_unb1_correlator_mesh_ref/hdllib.cfg
+++ b/applications/apertif/designs/apertif_unb1_correlator/revisions/apertif_unb1_correlator_mesh_ref/hdllib.cfg
@@ -2,18 +2,8 @@ hdl_lib_name = apertif_unb1_correlator_mesh_ref
hdl_library_clause_name = apertif_unb1_correlator_mesh_ref_lib
hdl_lib_uses_synth = common mm dp i2c unb1_board tr_10GbE correlator diag rTwoSDF wpfb st filter fft apertif bf
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_stratixiv
-synth_top_level_entity =
-
-quartus_copy_files =
- ../../quartus/qsys_apertif_unb1_correlator.qsys .
- ../../src/hex/ hex
-
-modelsim_copy_files =
- ../../src/hex hex
-
synth_files =
$HDL_BUILD_DIR/unb1/quartus/apertif_unb1_correlator_mesh_ref/qsys_apertif_unb1_correlator/synthesis/qsys_apertif_unb1_correlator.v
../../src/vhdl/apertif_unb1_correlator_pkg.vhd
@@ -31,6 +21,19 @@ synth_files =
test_bench_files =
tb_apertif_unb1_correlator_mesh_ref.vhd
+
+[modelsim_project_file]
+modelsim_copy_files =
+ ../../src/hex hex
+
+
+[quartus_project_file]
+synth_top_level_entity =
+
+quartus_copy_files =
+ ../../quartus/qsys_apertif_unb1_correlator.qsys .
+ ../../src/hex/ hex
+
quartus_qsf_files =
$RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
diff --git a/applications/apertif/designs/apertif_unb1_correlator/revisions/apertif_unb1_correlator_rx_only/hdllib.cfg b/applications/apertif/designs/apertif_unb1_correlator/revisions/apertif_unb1_correlator_rx_only/hdllib.cfg
index fb83e07e1972b82dc2b6e4dc19bf6026f8b80aed..212c46f80f7e806f2a8633dc8d1ef3d1ae286450 100644
--- a/applications/apertif/designs/apertif_unb1_correlator/revisions/apertif_unb1_correlator_rx_only/hdllib.cfg
+++ b/applications/apertif/designs/apertif_unb1_correlator/revisions/apertif_unb1_correlator_rx_only/hdllib.cfg
@@ -2,19 +2,8 @@ hdl_lib_name = apertif_unb1_correlator_rx_only
hdl_library_clause_name = apertif_unb1_correlator_rx_only_lib
hdl_lib_uses_synth = common mm dp i2c unb1_board tr_10GbE correlator diag rTwoSDF wpfb st filter fft apertif bf
hdl_lib_uses_sim = apertif_unb1_fn_bf_emu
-
hdl_lib_technology = ip_stratixiv
-synth_top_level_entity =
-
-quartus_copy_files =
- ../../quartus/qsys_apertif_unb1_correlator.qsys .
- ../../src/hex/ hex
-
-modelsim_copy_files =
- ../../src/hex hex
- ../../../apertif_unb1_fn_bf_emu/src/hex hex
-
synth_files =
$HDL_BUILD_DIR/unb1/quartus/apertif_unb1_correlator_rx_only/qsys_apertif_unb1_correlator/synthesis/qsys_apertif_unb1_correlator.v
../../src/vhdl/apertif_unb1_correlator_pkg.vhd
@@ -31,6 +20,20 @@ synth_files =
test_bench_files =
+
+[modelsim_project_file]
+modelsim_copy_files =
+ ../../src/hex hex
+ ../../../apertif_unb1_fn_bf_emu/src/hex hex
+
+
+[quartus_project_file]
+synth_top_level_entity =
+
+quartus_copy_files =
+ ../../quartus/qsys_apertif_unb1_correlator.qsys .
+ ../../src/hex/ hex
+
quartus_qsf_files =
$RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
diff --git a/applications/apertif/designs/apertif_unb1_correlator/revisions/apertif_unb1_correlator_simple/hdllib.cfg b/applications/apertif/designs/apertif_unb1_correlator/revisions/apertif_unb1_correlator_simple/hdllib.cfg
index 9cfe8f4f2b93fb6f83ea4a9a7cd09aadc8296c2e..089b488499fcfc93fa9a4c35dba5344bb79484b8 100644
--- a/applications/apertif/designs/apertif_unb1_correlator/revisions/apertif_unb1_correlator_simple/hdllib.cfg
+++ b/applications/apertif/designs/apertif_unb1_correlator/revisions/apertif_unb1_correlator_simple/hdllib.cfg
@@ -2,18 +2,8 @@ hdl_lib_name = apertif_unb1_correlator_simple
hdl_library_clause_name = apertif_unb1_correlator_simple_lib
hdl_lib_uses_synth = common mm dp i2c unb1_board tr_10GbE correlator diag rTwoSDF wpfb st filter fft apertif bf
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_stratixiv
-synth_top_level_entity =
-
-quartus_copy_files =
- ../../quartus/qsys_apertif_unb1_correlator.qsys .
- ../../src/hex/ hex
-
-modelsim_copy_files =
- ../../src/hex hex
-
synth_files =
$HDL_BUILD_DIR/unb1/quartus/apertif_unb1_correlator_simple/qsys_apertif_unb1_correlator/synthesis/qsys_apertif_unb1_correlator.v
../../src/vhdl/apertif_unb1_correlator_pkg.vhd
@@ -30,6 +20,19 @@ synth_files =
test_bench_files =
tb_apertif_unb1_correlator_simple.vhd
+
+[modelsim_project_file]
+modelsim_copy_files =
+ ../../src/hex hex
+
+
+[quartus_project_file]
+synth_top_level_entity =
+
+quartus_copy_files =
+ ../../quartus/qsys_apertif_unb1_correlator.qsys .
+ ../../src/hex/ hex
+
quartus_qsf_files =
$RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
diff --git a/applications/apertif/designs/apertif_unb1_correlator/revisions/sim_apertif_unb1_correlator_nodes/hdllib.cfg b/applications/apertif/designs/apertif_unb1_correlator/revisions/sim_apertif_unb1_correlator_nodes/hdllib.cfg
index 835e6b5f7abd65b2a085c50798b10e0b789567c8..f6e893fd4d213b37c8861c4d0e6e82289b7b0046 100644
--- a/applications/apertif/designs/apertif_unb1_correlator/revisions/sim_apertif_unb1_correlator_nodes/hdllib.cfg
+++ b/applications/apertif/designs/apertif_unb1_correlator/revisions/sim_apertif_unb1_correlator_nodes/hdllib.cfg
@@ -2,22 +2,13 @@ hdl_lib_name = sim_apertif_unb1_correlator_nodes
hdl_library_clause_name = sim_apertif_unb1_correlator_nodes_lib
hdl_lib_uses_synth = common mm dp correlator diag rTwoSDF wpfb st filter fft apertif bf unb1_board tr_10GbE
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_stratixiv
-synth_top_level_entity =
-
-quartus_copy_files =
-
-modelsim_copy_files =
- ../../src/hex hex
-
synth_files =
../../src/vhdl/apertif_unb1_correlator_pkg.vhd
../../src/vhdl/apertif_unb1_correlator_output_framer.vhd
../../src/vhdl/apertif_unb1_correlator_vis_offload.vhd
../../src/vhdl/node_apertif_unb1_correlator_input_sync_insert.vhd
-
../../src/vhdl/node_apertif_unb1_correlator_input.vhd
../../src/vhdl/node_apertif_unb1_correlator_mesh.vhd
../../src/vhdl/node_apertif_unb1_correlator_processing.vhd
@@ -26,6 +17,17 @@ synth_files =
test_bench_files =
tb_node_apertif_unb1_correlator_input.vhd
+
+[modelsim_project_file]
+modelsim_copy_files =
+ ../../src/hex hex
+
+
+[quartus_project_file]
+synth_top_level_entity =
+
+quartus_copy_files =
+
quartus_qsf_files =
quartus_tcl_files =
diff --git a/applications/apertif/designs/apertif_unb1_fn_beamformer/revisions/apertif_unb1_fn_beamformer_base/hdllib.cfg b/applications/apertif/designs/apertif_unb1_fn_beamformer/revisions/apertif_unb1_fn_beamformer_base/hdllib.cfg
index 33687cbb006f9c43b167ffc23e17d5f181a39634..325598ff8bec0ec130f836b3bef527934af08a10 100644
--- a/applications/apertif/designs/apertif_unb1_fn_beamformer/revisions/apertif_unb1_fn_beamformer_base/hdllib.cfg
+++ b/applications/apertif/designs/apertif_unb1_fn_beamformer/revisions/apertif_unb1_fn_beamformer_base/hdllib.cfg
@@ -7,8 +7,6 @@ hdl_lib_excludes = ip_stratixiv_ddr3_uphy_4g_800_master
ip_stratixiv_ddr3_uphy_4g_single_rank_800_master
ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave
-synth_top_level_entity =
-
synth_files =
../../../../../../libraries/dsp/bf/designs/unb1_fn_bf/src/vhdl/node_unb1_fn_bf.vhd
$HDL_BUILD_DIR/unb1/quartus/apertif_unb1_fn_beamformer_base/sopc_apertif_unb1_fn_beamformer.vhd
@@ -22,8 +20,18 @@ synth_files =
test_bench_files =
tb_apertif_unb1_fn_beamformer_base.vhd
+
+[modelsim_project_file]
modelsim_copy_files = ../../src/hex hex
+modelsim_search_libraries =
+ altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver stratixiv_ver stratixiv_hssi_ver stratixiv_pcie_hip_ver
+ altera lpm sgate altera_mf altera_lnsim stratixiv stratixiv_hssi stratixiv_pcie_hip
+
+
+[quartus_project_file]
+synth_top_level_entity =
+
quartus_copy_files = ../../quartus/sopc_apertif_unb1_fn_beamformer.sopc .
quartus_qsf_files =
@@ -36,9 +44,5 @@ quartus_tcl_files =
quartus_qip_files =
$HDL_BUILD_DIR/unb1/quartus/apertif_unb1_fn_beamformer_base/sopc_apertif_unb1_fn_beamformer.qip
-modelsim_search_libraries =
- altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver stratixiv_ver stratixiv_hssi_ver stratixiv_pcie_hip_ver
- altera lpm sgate altera_mf altera_lnsim stratixiv stratixiv_hssi stratixiv_pcie_hip
-
quartus_sdc_files =
$RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
diff --git a/applications/apertif/designs/apertif_unb1_fn_beamformer/revisions/apertif_unb1_fn_beamformer_bg_bf_tp/hdllib.cfg b/applications/apertif/designs/apertif_unb1_fn_beamformer/revisions/apertif_unb1_fn_beamformer_bg_bf_tp/hdllib.cfg
index e42ee18d6e6480bd3956e3bcb2426e3182c20417..63de8bc3e21a2cf1828443efe939774cb5a25816 100644
--- a/applications/apertif/designs/apertif_unb1_fn_beamformer/revisions/apertif_unb1_fn_beamformer_bg_bf_tp/hdllib.cfg
+++ b/applications/apertif/designs/apertif_unb1_fn_beamformer/revisions/apertif_unb1_fn_beamformer_bg_bf_tp/hdllib.cfg
@@ -6,8 +6,6 @@ hdl_lib_excludes = ip_stratixiv_ddr3_uphy_4g_800_master
ip_stratixiv_ddr3_uphy_4g_800_slave
ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave
-synth_top_level_entity = apertif_unb1_fn_beamformer_bg_bf_tp
-
synth_files =
../../../../../../libraries/dsp/bf/designs/unb1_fn_bf/src/vhdl/node_unb1_fn_bf.vhd
$HDL_BUILD_DIR/unb1/quartus/apertif_unb1_fn_beamformer_bg_bf_tp/sopc_apertif_unb1_fn_beamformer.vhd
@@ -21,8 +19,21 @@ synth_files =
test_bench_files =
tb_apertif_unb1_fn_beamformer_bg_bf_tp.vhd
+
+[modelsim_project_file]
modelsim_copy_files = ../../src/hex hex
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
+
+modelsim_search_libraries =
+ altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver stratixiv_ver stratixiv_hssi_ver stratixiv_pcie_hip_ver
+ altera lpm sgate altera_mf altera_lnsim stratixiv stratixiv_hssi stratixiv_pcie_hip
+
+
+[quartus_project_file]
+synth_top_level_entity = apertif_unb1_fn_beamformer_bg_bf_tp
+
quartus_copy_files = ../../quartus/sopc_apertif_unb1_fn_beamformer.sopc .
../../src/hex hex
@@ -37,10 +48,3 @@ quartus_tcl_files =
quartus_qip_files =
$HDL_BUILD_DIR/unb1/quartus/apertif_unb1_fn_beamformer_bg_bf_tp/sopc_apertif_unb1_fn_beamformer.qip
-modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
-
-modelsim_search_libraries =
- altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver stratixiv_ver stratixiv_hssi_ver stratixiv_pcie_hip_ver
- altera lpm sgate altera_mf altera_lnsim stratixiv stratixiv_hssi stratixiv_pcie_hip
-
diff --git a/applications/apertif/designs/apertif_unb1_fn_beamformer/revisions/apertif_unb1_fn_beamformer_bg_tp/hdllib.cfg b/applications/apertif/designs/apertif_unb1_fn_beamformer/revisions/apertif_unb1_fn_beamformer_bg_tp/hdllib.cfg
index 6ab084a2b2a69066d85c8104ab564158fa7bc7ab..ebfc6cf96c282b3713aafbdd78a7c1021c84dfb5 100644
--- a/applications/apertif/designs/apertif_unb1_fn_beamformer/revisions/apertif_unb1_fn_beamformer_bg_tp/hdllib.cfg
+++ b/applications/apertif/designs/apertif_unb1_fn_beamformer/revisions/apertif_unb1_fn_beamformer_bg_tp/hdllib.cfg
@@ -6,8 +6,6 @@ hdl_lib_excludes = ip_stratixiv_ddr3_uphy_4g_800_master
ip_stratixiv_ddr3_uphy_4g_800_slave
ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave
-synth_top_level_entity = apertif_unb1_fn_beamformer_bg_tp
-
synth_files =
../../../../../../libraries/dsp/bf/designs/unb1_fn_bf/src/vhdl/node_unb1_fn_bf.vhd
$HDL_BUILD_DIR/unb1/quartus/apertif_unb1_fn_beamformer_bg_tp/sopc_apertif_unb1_fn_beamformer.vhd
@@ -21,8 +19,21 @@ synth_files =
test_bench_files =
tb_apertif_unb1_fn_beamformer_bg_tp.vhd
+
+[modelsim_project_file]
modelsim_copy_files = ../../src/hex hex
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
+
+modelsim_search_libraries =
+ altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver stratixiv_ver stratixiv_hssi_ver stratixiv_pcie_hip_ver
+ altera lpm sgate altera_mf altera_lnsim stratixiv stratixiv_hssi stratixiv_pcie_hip
+
+
+[quartus_project_file]
+synth_top_level_entity = apertif_unb1_fn_beamformer_bg_tp
+
quartus_copy_files = ../../quartus/sopc_apertif_unb1_fn_beamformer.sopc .
../../src/hex hex
@@ -36,11 +47,3 @@ quartus_tcl_files =
quartus_qip_files =
$HDL_BUILD_DIR/unb1/quartus/apertif_unb1_fn_beamformer_bg_tp/sopc_apertif_unb1_fn_beamformer.qip
-
-modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
-
-modelsim_search_libraries =
- altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver stratixiv_ver stratixiv_hssi_ver stratixiv_pcie_hip_ver
- altera lpm sgate altera_mf altera_lnsim stratixiv stratixiv_hssi stratixiv_pcie_hip
-
diff --git a/applications/apertif/designs/apertif_unb1_fn_beamformer/revisions/apertif_unb1_fn_beamformer_transpose/hdllib.cfg b/applications/apertif/designs/apertif_unb1_fn_beamformer/revisions/apertif_unb1_fn_beamformer_transpose/hdllib.cfg
index 0b0c7c5ed6bc3360be211499967d616b05f65b3e..3e5b81f372ef8c57e1e630fa10c3e12f3ab8f01d 100644
--- a/applications/apertif/designs/apertif_unb1_fn_beamformer/revisions/apertif_unb1_fn_beamformer_transpose/hdllib.cfg
+++ b/applications/apertif/designs/apertif_unb1_fn_beamformer/revisions/apertif_unb1_fn_beamformer_transpose/hdllib.cfg
@@ -7,8 +7,6 @@ hdl_lib_excludes = ip_stratixiv_ddr3_uphy_4g_800_master
ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave
ip_stratixiv_ddr3_uphy_16g_dual_rank_800
-synth_top_level_entity = apertif_unb1_fn_beamformer_transpose
-
synth_files =
../../../../../../libraries/dsp/bf/designs/unb1_fn_bf/src/vhdl/node_unb1_fn_bf.vhd
$HDL_BUILD_DIR/unb1/quartus/apertif_unb1_fn_beamformer_trans/sopc_apertif_unb1_fn_beamformer.vhd
@@ -22,8 +20,21 @@ synth_files =
test_bench_files =
tb_apertif_unb1_fn_beamformer_trans.vhd
+
+[modelsim_project_file]
modelsim_copy_files = ../../src/hex hex
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
+
+modelsim_search_libraries =
+ altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver stratixiv_ver stratixiv_hssi_ver stratixiv_pcie_hip_ver
+ altera lpm sgate altera_mf altera_lnsim stratixiv stratixiv_hssi stratixiv_pcie_hip
+
+
+[quartus_project_file]
+synth_top_level_entity = apertif_unb1_fn_beamformer_transpose
+
quartus_copy_files = ../../quartus/sopc_apertif_unb1_fn_beamformer.sopc .
../../src/hex hex
@@ -39,12 +50,5 @@ quartus_qip_files =
$RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
$HDL_BUILD_DIR/unb1/quartus/apertif_unb1_fn_beamformer_trans/sopc_apertif_unb1_fn_beamformer.qip
-modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
-
-modelsim_search_libraries =
- altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver stratixiv_ver stratixiv_hssi_ver stratixiv_pcie_hip_ver
- altera lpm sgate altera_mf altera_lnsim stratixiv stratixiv_hssi stratixiv_pcie_hip
-
quartus_sdc_files =
$RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
diff --git a/applications/apertif/designs/apertif_unb1_fn_bf_emu/hdllib.cfg b/applications/apertif/designs/apertif_unb1_fn_bf_emu/hdllib.cfg
index 41290e791f37e2e3d69e93d83867550241d0494b..3f1f0f3cc7c261efb4721964cbaaf18011a8c5a8 100644
--- a/applications/apertif/designs/apertif_unb1_fn_bf_emu/hdllib.cfg
+++ b/applications/apertif/designs/apertif_unb1_fn_bf_emu/hdllib.cfg
@@ -3,8 +3,6 @@ hdl_library_clause_name = apertif_unb1_fn_bf_emu_lib
hdl_lib_uses_synth = common technology tech_mac_10g tr_10GbE mm i2c unb1_board bf apertif
hdl_lib_technology = ip_stratixiv
-synth_top_level_entity =
-
synth_files =
$HDL_BUILD_DIR/unb1/quartus/apertif_unb1_fn_bf_emu/sopc_apertif_unb1_fn_bf_emu.vhd
../apertif_unb1_fn_beamformer/src/vhdl/apertif_unb1_fn_beamformer_udp_offload.vhd
@@ -14,8 +12,18 @@ synth_files =
test_bench_files =
tb/vhdl/tb_apertif_unb1_fn_bf_emu.vhd
+
+[modelsim_project_file]
modelsim_copy_files = src/hex hex
+modelsim_search_libraries =
+ altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver stratixiv_ver stratixiv_hssi_ver stratixiv_pcie_hip_ver
+ altera lpm sgate altera_mf altera_lnsim stratixiv stratixiv_hssi stratixiv_pcie_hip
+
+
+[quartus_project_file]
+synth_top_level_entity =
+
quartus_copy_files =
quartus/sopc_apertif_unb1_fn_bf_emu.sopc .
src/hex hex
@@ -29,8 +37,5 @@ quartus_tcl_files =
quartus_qip_files =
$HDL_BUILD_DIR/unb1/quartus/apertif_unb1_fn_bf_emu/sopc_apertif_unb1_fn_bf_emu.qip
-modelsim_search_libraries =
- altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver stratixiv_ver stratixiv_hssi_ver stratixiv_pcie_hip_ver
- altera lpm sgate altera_mf altera_lnsim stratixiv stratixiv_hssi stratixiv_pcie_hip
quartus_sdc_files =
$RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
diff --git a/applications/apertif/libraries/apertif/hdllib.cfg b/applications/apertif/libraries/apertif/hdllib.cfg
index 1ebbb7bcda643df0b6efc6f62bb2d4426693f2a9..3599df31695cf21ec9112c1283dab8afe821b554 100644
--- a/applications/apertif/libraries/apertif/hdllib.cfg
+++ b/applications/apertif/libraries/apertif/hdllib.cfg
@@ -7,3 +7,10 @@ synth_files =
src/vhdl/apertif_udp_offload_pkg.vhd
test_bench_files =
+
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+
diff --git a/applications/apertif/matlab/corner_turn.m b/applications/apertif/matlab/corner_turn.m
index f9de300e87f33eb0228deeb99bc59521cb205c28..95551dc32e0bfd40364d449865a1b5e576d409b0 100644
--- a/applications/apertif/matlab/corner_turn.m
+++ b/applications/apertif/matlab/corner_turn.m
@@ -20,26 +20,29 @@
%-----------------------------------------------------------------------------
% Author: E. Kooistra, 2016
%
-% Purpose : Collect blocks of data and then corner turn the data blocks.
+% Purpose : Collect M blocks of in_data(1:K) and then transpose [M] and [K].
% Description :
%
+% The corner turn can also include the last L blocks from the previous
+% interval, so then tranpsose [L+M] and [K].
+%
% M=nof_block
% K=block_size
% L=tail_nof_block
%
-% Buffer at in_sync (i.e. when bi == M):
-% 1 in_data(1:K)
-% 2 in_data(1:K)
-% ...
-% M in_data(1:K)
-%
-% Tail buffer at in_sync:
+% Tail previous buffer at in_sync:
%
% M-L+1 in_data(1:K)
% M-L+2 in_data(1:K)
% ...
% M-L+L in_data(1:K)
%
+% Buffer at in_sync (i.e. when bi == M):
+% 1 in_data(1:K)
+% 2 in_data(1:K)
+% ...
+% M in_data(1:K)
+%
% Output at in_sync when output_type = 'matrix':
%
% 1 in_data(1)(1:L,1:M)
diff --git a/applications/apertif/matlab/delay_tracking_pfb.m b/applications/apertif/matlab/delay_tracking_pfb.m
index d1f404ae1f603c8b04c3dd979e7dcf8dcb241dfb..10479f7fcf870742eb0febf0b0681baf96b8a692 100644
--- a/applications/apertif/matlab/delay_tracking_pfb.m
+++ b/applications/apertif/matlab/delay_tracking_pfb.m
@@ -48,16 +48,18 @@ close all;
fig=0;
tb.model = 'floating point';
-tb.model = 'fixed point';
+%tb.model = 'fixed point';
tb.nof_complex = 2;
-tb.nof_subbands = 512;
-tb.bsn_init = 0;
-tb.subband_nr = 113; % subband range 0:511, can be fraction
-%tb.subband_nr = 113.5;
-tb.subband_i = round(tb.subband_nr);
+tb.nof_subbands = 32;
+tb.subband_wg = 0.1*32; % subband range 0:tb.nof_subbands-1, can be fraction
+%tb.subband_wg = 13.5;
+tb.subband_i = floor(tb.subband_wg); % natural subband index in range 0:tb.nof_subbands-1
tb.subband_fft_size = tb.nof_complex*tb.nof_subbands; % subband filterbank real FFT
-tb.nof_blocks = 61;
+tb.nof_tsub = 500;
+
+fs = 1; % normalized sample frequency
+fsub = fs/tb.subband_fft_size; % subband frequency relative to fs
% DP quantization, width 0 is use double, width > 0 is use nof bits for data
if strcmp(tb.model, 'floating point')
@@ -70,6 +72,7 @@ if strcmp(tb.model, 'floating point')
ctrl_pfft_subband.data_w = 0;
ctrl_spec_subband.db_low = -150;
+ ctrl_spec_subband.db_low = -70;
else
ctrl_wg.data_w = 8;
lsb = 1/2^ctrl_wg.data_w;
@@ -92,9 +95,14 @@ if ctrl_wg.agwn_sigma>0
ctrl_wg.ampl = 0.9;
end
%ctrl_wg.ampl = 0.01;
-ctrl_wg.offset = 0; % DC offset
-ctrl_wg.freq = tb.subband_nr/tb.subband_fft_size; % normalized fs
+ctrl_wg.freq = tb.subband_wg*fsub;
+ctrl_wg.df = 0.01*fsub; % increment freq by df per block to create chirp
ctrl_wg.phase = 0; % normalized 2pi
+if ctrl_wg.freq == 0
+ ctrl_wg.offset = 1; % DC offset
+else
+ ctrl_wg.offset = 0; % DC offset
+end
% Delay tracking
ctrl_dt.block_size = tb.subband_fft_size;
@@ -102,9 +110,6 @@ ctrl_dt.buffer = zeros(1, 2*ctrl_dt.block_size);
ctrl_dt.step = 4; % Delay step is Psub = 4 factor, for 4 samples per clock
ctrl_dt.dt = 0; % Delay setting in +- number of ctrl_dt.step time samples of ADC or WG
-% BSN source
-ctrl_bsn_source.bsn = tb.bsn_init; % Start BSN
-
% Subband FIR filter parameters
ctrl_pfir_subband.downsample_factor = tb.subband_fft_size;
ctrl_pfir_subband.nof_taps = 16; % Number of taps
@@ -151,17 +156,25 @@ ctrl_pfft_subband.complex = false;
ctrl_pfft_subband.gain = ctrl_pfft_subband.fft_size;
% Reorder subband select parameters
-ctrl_reorder_subband.select = tb.subband_i + [1 2];
ctrl_reorder_subband.select = tb.subband_i + 1;
+ctrl_reorder_subband.select = tb.subband_i + 1 + [0:2];
+ctrl_reorder_subband.select = 1:tb.nof_subbands;
ctrl_reorder_subband.block_size = length(ctrl_reorder_subband.select);
-% Run the data path processing (one block per row)
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+% Run the data path processing
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
t_start = cputime;
-data_dt = zeros(tb.nof_blocks, tb.subband_fft_size);
-data_pfir_subband = zeros(tb.nof_blocks, tb.subband_fft_size);
-data_pfft_subband = zeros(tb.nof_blocks, tb.nof_subbands);
-data_reorder_subband = zeros(tb.nof_blocks, ctrl_reorder_subband.block_size);
-for bi = 1:tb.nof_blocks
+data_dt = zeros(tb.nof_tsub, tb.subband_fft_size);
+data_pfir_subband = zeros(tb.nof_tsub, tb.subband_fft_size);
+data_pfft_subband = zeros(tb.nof_tsub, tb.nof_subbands);
+data_reorder_subband = zeros(tb.nof_tsub, ctrl_reorder_subband.block_size);
+for bi = 1:tb.nof_tsub
+ % Timing
+ if bi==1
+ ctrl_bsn_source.bsn = 0; % Start BSN source
+ end
+
% Control
if ctrl_bsn_source.bsn == 30
ctrl_dt.dt = ctrl_dt.dt - ctrl_dt.step; % Apply delay step
@@ -184,10 +197,17 @@ end
t_stop = cputime;
disp(sprintf('Total processing time: %f seconds', t_stop-t_start));
+
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
% Plot data path results
-ts = (0:tb.subband_fft_size*tb.nof_blocks-1)/tb.subband_fft_size; % time of ADC / WG samples in block periods
-tsub = (0:tb.nof_subbands*tb.nof_blocks-1)/tb.nof_subbands; % time in subband periods
-tblock = (0:tb.nof_blocks-1); % time in blocks
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+ts = (1:tb.subband_fft_size*tb.nof_tsub)/tb.subband_fft_size; % time of ADC / WG samples in subband periods
+tsub_all = (1: tb.nof_subbands*tb.nof_tsub)/tb.nof_subbands; % time in subband periods for block of subbands
+tsub_one = (1: tb.nof_tsub); % time in subband periods for one subband
+
+sub_i = tb.subband_i + [1: tb.nof_subbands: tb.nof_subbands*tb.nof_tsub]; % get indices of all subband_i
+
+sel_sub_i = find(ctrl_reorder_subband.select == tb.subband_i + 1, 1); % find index of subband_i in selected subbands
% Plot DT output
fig=fig+1;
@@ -196,8 +216,8 @@ figure(fig);
data = data_dt';
plot(ts, data(:))
ylim([-1.3 1.3]);
-title(sprintf('Delay tracking output data (WG subband %6.3f)', tb.subband_nr));
-xlabel('Time [T bsn]');
+title(sprintf('Delay tracking output data (WG subband %6.3f)', tb.subband_wg));
+xlabel(sprintf('Time 1:%d [Tsub]', tb.nof_tsub));
ylabel('Voltage');
grid on;
@@ -225,48 +245,53 @@ figure('position', [300+fig*20 200-fig*20 1000 800]);
figure(fig);
data = data_pfir_subband';
plot(ts, data(:))
-title(sprintf('Subband polyphase FIR filter output - FFT input data (WG subband %6.3f)', tb.subband_nr));
-ylim([-2 2]); % DT step when tb.subband_nr is .5 causes double range
-xlabel('Time [T bsn]');
+title(sprintf('Subband polyphase FIR filter output - FFT input data (WG subband %6.3f)', tb.subband_wg));
+ylim([-2 2]); % DT step when tb.subband_wg is .5 causes double range
+xlabel(sprintf('Time 1:%d [Tsub]', tb.nof_tsub));
ylabel('Voltage');
grid on;
% Plot PFFT subbands spectrum and phase
-ampl = abs(data_pfft_subband);
-phase = angle(data_pfft_subband)*180/pi;
-noise = ampl < 0.1*max(ampl(:));
-phase(noise) = 0; % force phase of too small signals to 0
+sub_ampl = abs(data_pfft_subband);
+sub_ampl_max = max(sub_ampl(:));
+sub_phase = angle(data_pfft_subband)*180/pi;
+x = sub_ampl < 0.1*sub_ampl_max;
+sub_phase(x) = 0; % force phase of too small signals to 0
fig=fig+1;
figure('position', [300+fig*20 200-fig*20 1000 800]);
figure(fig);
subplot(2,1,1);
-data = ampl';
-plot(tsub, data(:))
-title('Subband data - amplitude');
-xlabel(sprintf('Subband 0:%d at time [T bsn]', tb.nof_subbands-1));
+data = sub_ampl';
+data = data(:);
+plot(tsub_all, data, 'k', tsub_all(sub_i), data(sub_i), 'ko', tsub_all(sub_i+1), data(sub_i+1), 'kx');
+title(sprintf('Subband data - amplitude (o = subband index %d for WG subband = %6.3f, x = next)', tb.subband_i, tb.subband_wg));
+xlabel(sprintf('Subbands 0:%d at time 1:%d [Tsub]', tb.nof_subbands-1, tb.nof_tsub));
ylabel('Voltage');
grid on;
subplot(2,1,2);
-data = phase';
-plot(tsub, data(:))
+data = sub_phase';
+data = data(:);
+plot(tsub_all, data, 'k', tsub_all(sub_i), data(sub_i), 'ko', tsub_all(sub_i+1), data(sub_i+1), 'kx');
ylim([-180 180])
-title('Subband data - phase');
-xlabel(sprintf('Subband 0:%d at time [T bsn]', tb.nof_subbands-1));
+title(sprintf('Subband data - amplitude (o = subband index %d for WG subband = %6.3f, x = next)', tb.subband_i, tb.subband_wg));
+xlabel(sprintf('Subbands 0:%d at time 1:%d [Tsub]', tb.nof_subbands-1, tb.nof_tsub));
ylabel('Phase [degrees]');
grid on;
% Plot phase step due to DT step for the subband that is set in the WG
-%phase = angle(data_pfft_subband(:, tb.subband_i + 1))*180/pi;
-phase = angle(data_reorder_subband(:,1))*180/pi;
-
+if isempty(sel_sub_i)
+ wg_sub_phase = angle(data_pfft_subband(:, tb.subband_i + 1))*180/pi; % use Matlab indexing if subband is not selected
+else
+ wg_sub_phase = angle(data_reorder_subband(:, sel_sub_i))*180/pi; % use functional reorder subband
+end
fig=fig+1;
figure('position', [300+fig*20 200-fig*20 1000 800]);
figure(fig);
-plot(tblock, phase, '-o')
+plot(tsub_one, wg_sub_phase, '-o')
ylim([-180 180])
title(sprintf('Subband phase for subband %d in range 0:%d', tb.subband_i, tb.nof_subbands-1));
-xlabel('Time [T bsn]');
+xlabel(sprintf('Time 1:%d [Tsub]', tb.nof_tsub));
ylabel('Phase [degrees]');
grid on;
@@ -274,9 +299,7 @@ grid on;
fig=fig+1;
figure('position', [300+fig*20 200-fig*20 1000 800]);
figure(fig);
-data = abs(data_pfft_subband);
-data_abs_max = max(data(:));
-data = db(data); % no need to scale data, range is already normalized
+data = db(sub_ampl); % no need to scale data, range is already normalized
x = ctrl_spec_subband.db_low;
%x = floor(min(data(data~=-Inf)))
data(data<x) = x;
@@ -285,7 +308,7 @@ mymap = jet(-x);
colormap(mymap);
imagesc(data',[x 0]);
colorbar;
-title(sprintf('Subband spectogram (max value = %f = %f dB)', data_abs_max, db(data_abs_max)));
-xlabel('Time [T bsn]');
-ylabel('Subband');
+title(sprintf('Subband spectogram (max value = %f = %f dB)', sub_ampl_max, db(sub_ampl_max)));
+xlabel(sprintf('Time 1:%d [Tsub]', tb.nof_tsub));
+ylabel(sprintf('Subbands 1:%d', tb.nof_subbands));
diff --git a/applications/apertif/matlab/pfir.m b/applications/apertif/matlab/pfir.m
index 0a98ea43659e5aad12ebeef965105aab92f5f211..006da601e30565158ab2d87bf94d6e1e21ced30a 100644
--- a/applications/apertif/matlab/pfir.m
+++ b/applications/apertif/matlab/pfir.m
@@ -26,7 +26,10 @@
function [state, out_data] = pfir(ctrl, in_data)
% Data processing
-for t = 1:ctrl.downsample_factor
+for t = ctrl.downsample_factor:-1:1
+ if t==1
+ ctrl.Zdelays(t,:)
+ end
[out_data(t), ctrl.Zdelays(t,:)] = filter(ctrl.coeff(t,:), 1, in_data(t), ctrl.Zdelays(t,:)); % range ctrl.nof_taps coefficients and range ctrl.nof_taps-1 Zdelays
end
diff --git a/applications/apertif/matlab/two_pfb.m b/applications/apertif/matlab/two_pfb.m
index e7d281221b523f9ab56bb3ee65f9025a6a15fd88..68e2bdaba08dbbbb7c5a169c30293f689535f97e 100644
--- a/applications/apertif/matlab/two_pfb.m
+++ b/applications/apertif/matlab/two_pfb.m
@@ -35,36 +35,60 @@
% -1:1.
% * Two poly phase filterbanks (PFB)
% Model subband filterbank and channel filterbank to make fine channels
-% per subband.
+% per subband. The corner turner operates directly on the selected
+% subbands to have time samples grouped per subband as input for the
+% channel filter. The sync interval sets the number of blocks per
+% corner turn. From subband to subband the the channel filter should
+% rerun the impulse reponse tail of the previous sync interval.
+% However if the sync interval is very large, than this rerun may be
+% ignored to simplify the implementation.
+% * Then Apertif subband beamformer is not modelled, therefore the corner
+% turn operates on the selected subbands. The channel correlator is not
+% modelled, but typically the sync interval will be equal to the
+% integration interval of 1.024 s (= 800000 subband blocks).
clear all;
close all;
fig=0;
tb.model = 'floating point';
-tb.model = 'fixed point';
+%tb.model = 'fixed point';
tb.nof_complex = 2;
-tb.nof_subbands = 512;
-tb.subband_nr = 113; % subband range 0:511, can be fraction
-%tb.subband_nr = 113.5;
-tb.subband_i = round(tb.subband_nr);
-tb.subband_fft_size = tb.nof_complex*tb.nof_subbands; % subband filterbank real FFT
-tb.sync_interval = 50; % nof blocks per sync interval
-tb.nof_sync = 2;
-tb.nof_blocks = tb.nof_sync*tb.sync_interval+1;
+tb.nof_subbands = 32;
+tb.nof_channels = 8;
+tb.subband_wg = 0+7/8+0.1; % subband range 0:tb.nof_subbands-1, can be fraction
+tb.subband_i = floor(tb.subband_wg); % natural subband index in range 0:tb.nof_subbands-1
+tb.channel_wg = tb.subband_wg - tb.subband_i; % use subband fraction as WG channel offset frequency within subband
+tb.channel_i = floor(tb.channel_wg*tb.nof_channels); % natural channel index in range 0:tb.nof_channels-1
+tb.subband_fft_size = tb.nof_subbands*tb.nof_complex; % subband filterbank real FFT
+tb.channel_fft_size = tb.nof_channels; % channel filterbank complex FFT
+
+tb.nof_tsync = 2; % nof sync intervals, the corner turn operates per sync interval
+tb.nof_tchan_per_sync = 20; % nof channel periods per sync interval
+tb.nof_tchan = tb.nof_tsync*tb.nof_tchan_per_sync;
+tb.nof_tsub_per_sync = tb.nof_tchan_per_sync*tb.channel_fft_size; % nof subband periods per sync interval, must be multiple of nof channels per subband
+tb.nof_tsub = tb.nof_tsync*tb.nof_tsub_per_sync+1; % one extra to be able to finish output of last sync interval
% DP quantization, width 0 is use double, width > 0 is use nof bits for data
if strcmp(tb.model, 'floating point')
ctrl_wg.data_w = 0;
ctrl_wg.agwn_sigma = 0; % AGWN sigma
%ctrl_wg.agwn_sigma = 0.01;
+
ctrl_pfir_subband.coeff_w = 0;
ctrl_pfir_subband.scale_w = 0;
ctrl_pfir_subband.data_w = 0;
ctrl_pfft_subband.data_w = 0;
ctrl_spec_subband.db_low = -150;
+
+ ctrl_pfir_channel.coeff_w = 0;
+ ctrl_pfir_channel.scale_w = 0;
+ ctrl_pfir_channel.data_w = 0;
+ ctrl_pfft_channel.data_w = 0;
+
+ ctrl_spec_channel.db_low = -150;
else
ctrl_wg.data_w = 8;
lsb = 1/2^ctrl_wg.data_w;
@@ -75,8 +99,13 @@ else
ctrl_pfir_subband.data_w = 16;
ctrl_pfft_subband.data_w = 16;
- ctrl_spec_subband.data_w = 10;
- ctrl_spec_subband.db_low = floor(-20 - 6.02 * ctrl_spec_subband.data_w);
+ ctrl_pfir_channel.coeff_w = 9;
+ ctrl_pfir_channel.scale_w = 1;
+ ctrl_pfir_channel.data_w = 16;
+ ctrl_pfft_channel.data_w = 16;
+
+ ctrl_spec_channel.data_w = 10;
+ ctrl_spec_channel.db_low = floor(-20 - 6.02 * ctrl_spec_channel.data_w);
end
% Waveform generator
@@ -87,9 +116,13 @@ if ctrl_wg.agwn_sigma>0
ctrl_wg.ampl = 0.9;
end
%ctrl_wg.ampl = 0.01;
-ctrl_wg.offset = 0; % DC offset
-ctrl_wg.freq = tb.subband_nr/tb.subband_fft_size; % normalized fs
+ctrl_wg.freq = tb.subband_wg/tb.subband_fft_size; % normalized fs
ctrl_wg.phase = 0; % normalized 2pi
+if ctrl_wg.freq == 0
+ ctrl_wg.offset = 1; % DC offset
+else
+ ctrl_wg.offset = 0; % DC offset
+end
% Delay tracking
ctrl_dt.block_size = tb.subband_fft_size;
@@ -133,47 +166,82 @@ end
%ctrl_pfir_subband.coeff = fliplr(coeff);
%ctrl_pfir_subband.coeff = flipud(coeff);
-ctrl_pfir_subband.coeff = coeff;
+ctrl_pfir_subband.coeff = coeff;
ctrl_pfir_subband.Zdelays = zeros(ctrl_pfir_subband.downsample_factor, ctrl_pfir_subband.nof_taps-1);
-ctrl_pfir_subband.gain = sum(ctrl_pfir_subband.coeff(:)) / ctrl_pfir_subband.downsample_factor;
+ctrl_pfir_subband.gain = sum(ctrl_pfir_subband.coeff(:)) / ctrl_pfir_subband.downsample_factor;
% Subband FFT parameters
ctrl_pfft_subband.fft_size = tb.subband_fft_size;
ctrl_pfft_subband.complex = false;
-ctrl_pfft_subband.gain = ctrl_pfft_subband.fft_size;
+ctrl_pfft_subband.gain = ctrl_pfft_subband.fft_size;
% Subband select reorder parameters
-ctrl_reorder_subband.select = tb.subband_i + 1 +[-5:5];
+ctrl_reorder_subband.select = tb.subband_i + 1 + [0:2];
%ctrl_reorder_subband.select = tb.subband_i + 1;
+%ctrl_reorder_subband.select = 1:tb.nof_subbands;
ctrl_reorder_subband.block_size = length(ctrl_reorder_subband.select);
% Subband corner turn parameters
-ctrl_corner_turn.tail_nof_block = 0;
-ctrl_corner_turn.nof_block = tb.sync_interval;
+ctrl_corner_turn.nof_block = tb.nof_tsub_per_sync;
ctrl_corner_turn.block_size = ctrl_reorder_subband.block_size;
-ctrl_corner_turn.tail_buffer = zeros(ctrl_corner_turn.tail_nof_block, ctrl_corner_turn.block_size);
ctrl_corner_turn.buffer = zeros(ctrl_corner_turn.nof_block, ctrl_corner_turn.block_size);
ctrl_corner_turn.output_type = 'serial'; % 'serial' or 'matrix'
ctrl_corner_turn.bi = 1; % block index
+% Channel FIR filter parameters
+ctrl_pfir_channel.downsample_factor = tb.channel_fft_size;
+ctrl_pfir_channel.nof_taps = 8; % Number of taps
+ctrl_pfir_channel.nof_coefficients = ctrl_pfir_channel.downsample_factor*ctrl_pfir_channel.nof_taps; % Number of filter coefficients (taps)
+ctrl_pfir_channel.r_pass = 0.001;
+ctrl_pfir_channel.r_stop = 0.0001;
+ctrl_pfir_channel.hp_factor = 1.050; % Adjust channel half power bandwidth
+ctrl_pfir_channel.hp_factor = 1;
+ctrl_pfir_channel.BWchan = ctrl_pfir_channel.hp_factor / tb.channel_fft_size; % Channel bandwidth
+ctrl_pfir_channel.config.design = 'fir1';
+ctrl_pfir_channel.config.design = 'fircls1'; % 'fir1', 'fircls1', 'lofar file'
+ctrl_pfir_channel.config.design_flag = 'trace'; % 'trace'
+ctrl_pfir_channel.config.interpolate = 'interpft'; % 'resample', 'fourier', 'interpft'
+ctrl_pfir_channel.coeff = pfir_coeff(ctrl_pfir_channel.downsample_factor,....
+ ctrl_pfir_channel.nof_taps, ...
+ ctrl_pfir_channel.BWchan, ...
+ ctrl_pfir_channel.r_pass, ...
+ ctrl_pfir_channel.r_stop, ...
+ ctrl_pfir_channel.coeff_w, ...
+ ctrl_pfir_channel.config);
+ctrl_pfir_channel.Zdelays = zeros(ctrl_pfir_channel.downsample_factor, ctrl_pfir_channel.nof_taps-1);
+ctrl_pfir_channel.gain = sum(ctrl_pfir_channel.coeff(:)) / ctrl_pfir_channel.downsample_factor;
+
+% Subband corner turn tail nof block depends on FIR impulse response length
+ctrl_corner_turn.tail_nof_block = (ctrl_pfir_channel.nof_taps-1)*ctrl_pfir_channel.downsample_factor;
+ctrl_corner_turn.tail_buffer = zeros(ctrl_corner_turn.tail_nof_block, ctrl_corner_turn.block_size);
+
+% Channel FFT parameters
+ctrl_pfft_channel.fft_size = tb.channel_fft_size;
+ctrl_pfft_channel.complex = true;
+ctrl_pfft_channel.gain = ctrl_pfft_channel.fft_size;
+
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
% Run the data path processing
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
t_start = cputime;
-% - DP at subband block rate (one block per row)
-data_dt = zeros(tb.nof_blocks, tb.subband_fft_size);
-data_pfir_subband = zeros(tb.nof_blocks, tb.subband_fft_size);
-data_pfft_subband = zeros(tb.nof_blocks, tb.nof_subbands);
-data_reorder_subband = zeros(tb.nof_blocks, ctrl_reorder_subband.block_size);
-data_corner_turn = zeros(tb.nof_sync, ctrl_corner_turn.block_size * (ctrl_corner_turn.tail_nof_block+ctrl_corner_turn.nof_block));
+%--------------------------------------------------------------------------
+% - DP at subband block rate (one tsub block per row)
+%--------------------------------------------------------------------------
+data_dt = zeros(tb.nof_tsub, tb.subband_fft_size);
+data_pfir_subband = zeros(tb.nof_tsub, tb.subband_fft_size);
+data_pfft_subband = zeros(tb.nof_tsub, tb.nof_subbands);
+data_reorder_subband = zeros(tb.nof_tsub, ctrl_reorder_subband.block_size);
+data_corner_turn = zeros(tb.nof_tsync, ctrl_corner_turn.block_size * (ctrl_corner_turn.tail_nof_block+ctrl_corner_turn.nof_block));
si = 1;
-for bi = 1:tb.nof_blocks
+for bi = 1:tb.nof_tsub
% Timing
if bi==1
- sync = 0;
+ dp_sync = 0;
ctrl_bsn_source.bsn = 0; % Start BSN source
else
- sync = mod(ctrl_bsn_source.bsn, tb.sync_interval) == 0;
+ dp_sync = mod(ctrl_bsn_source.bsn, tb.nof_tsub_per_sync) == 0;
end
% Control
@@ -188,7 +256,7 @@ for bi = 1:tb.nof_blocks
[ctrl_pfir_subband, block_pfir_subband] = pfir( ctrl_pfir_subband, block_dt);
[ block_pfft_subband] = pfft( ctrl_pfft_subband, block_pfir_subband);
[ctrl_reorder_subband, block_reorder_subband] = reorder_serial(ctrl_reorder_subband, block_pfft_subband);
- [ctrl_corner_turn, block_corner_turn] = corner_turn( ctrl_corner_turn, block_reorder_subband, sync);
+ [ctrl_corner_turn, block_corner_turn] = corner_turn( ctrl_corner_turn, block_reorder_subband, dp_sync);
% Capture data at each DP interface
data_dt(bi, :) = block_dt;
@@ -196,33 +264,86 @@ for bi = 1:tb.nof_blocks
data_pfft_subband(bi, :) = block_pfft_subband;
data_reorder_subband(bi, :) = block_reorder_subband;
- if sync
+ if dp_sync
data_corner_turn(si, :) = block_corner_turn;
si = si + 1;
end
end
-% - DP at sync interval rate (one interval per row)
-for si = 1:tb.nof_sync
-end
+%--------------------------------------------------------------------------
+% - DP at sync interval rate (one tsync block per row)
+%--------------------------------------------------------------------------
+Nchan = tb.nof_channels; % number of channels per subband, = tb.nof_channels = tb.channel_fft_size = 64
+Ksub = ctrl_reorder_subband.block_size; % number of selected subbands, = 384 for 300MHz
+Kchan = Ksub*Nchan; % total number of channels in the selected subbands, = 384*64= 24576
+Lsub = ctrl_corner_turn.tail_nof_block; % number of subband periods in tail of previous sync interval, = 0 or (>= nof_taps-1) * FFT size in the channel FIR filter, = 7*64 = 448
+Msub = tb.nof_tsub_per_sync; % number of subband periods per corner turn sync interval, = 1.024s * 781250 = 800000
+Lchan = Lsub/Nchan; % number of channel periods in previous sync interval tail, = 8
+Mchan = tb.nof_tchan_per_sync; % number of channel periods in corner turn sync interval, = Msub/tb.channel_fft_size = 800000/64 = 12500
+Msync = tb.nof_tsync; % number of sync periods
+
+sprintf(['Nchan = %d\n', ...
+ 'Ksub = %d\n', ...
+ 'Kchan = %d\n', ...
+ 'Lsub = %d\n', ...
+ 'Msub = %d\n', ...
+ 'Lchan = %d\n', ...
+ 'Mchan = %d\n', ...
+ 'Msync = %d\n'], Nchan, Ksub, Kchan, Lsub, Msub, Lchan, Mchan, Msync)
+
+sprintf([' Ksub * Mchan = %d\n', ...
+ ' Ksub * (Lchan + Mchan) = %d\n', ...
+ ' Nchan * Ksub * (Lchan + Mchan) = %d\n', ...
+ 'Msync * Nchan * Ksub * (Lchan + Mchan) = %d\n'], Ksub*Mchan, Ksub*(Lchan+Mchan), Nchan*Ksub*(Lchan+Mchan), Msync*Nchan*Ksub*(Lchan+Mchan))
+data_pfir_channel = zeros(Nchan, Ksub*Mchan, Msync);
+data_pfft_channel = zeros(Nchan, Ksub*Mchan, Msync);
+for si = 1:Msync
+ % Data path (DP)
+ % - data_corner_turn(si, :) = subband(1)(1:Lsub,1:Msub), subband(2)(1:Lsub,1:Msub), ..., subband(Ksub)(1:Lsub,1:Msub)
+ data = reshape(data_corner_turn(si, :), Nchan, Ksub*(Lchan+Mchan));
+ cj = 0;
+ for ci = 1:Ksub*(Lchan+Mchan)
+ % Data path (DP)
+ [ctrl_pfir_channel, block_pfir_channel] = pfir(ctrl_pfir_channel, data(:, ci)); % input block of Nchan subband samples in time
+ [ block_pfft_channel] = pfft(ctrl_pfft_channel, block_pfir_channel);
+
+ % Capture data at each DP interface, skip the response for the Lchan tail
+ if (Lchan==0) || (mod(ci-1, Lchan+Mchan) >= Lchan)
+ cj = cj+1;
+ data_pfir_channel(:, cj, si) = block_pfir_channel;
+ data_pfft_channel(:, cj, si) = block_pfft_channel; % capture block of Nchan channel samples
+ end
+ end
+end
t_stop = cputime;
disp(sprintf('Total processing time: %f seconds', t_stop-t_start));
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
% Plot data path results
-ts = (0:tb.subband_fft_size*tb.nof_blocks-1)/tb.subband_fft_size; % time of ADC / WG samples in block periods
-tsub = (0:tb.nof_subbands*tb.nof_blocks-1)/tb.nof_subbands; % time in subband periods
-tblock = (0:tb.nof_blocks-1); % time in blocks
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+ts = (1:tb.subband_fft_size*tb.nof_tsub)/tb.subband_fft_size; % time of ADC / WG samples in subband periods
+tsub_all = (1: tb.nof_subbands*tb.nof_tsub)/tb.nof_subbands; % time in subband periods for block of subbands
+tsub_one = (1: tb.nof_tsub); % time in subband periods for one subband
+
+sub_i = tb.subband_i + [1: tb.nof_subbands: tb.nof_subbands*tb.nof_tsub]; % get indices of all subband_i
+
+sel_sub_i = find(ctrl_reorder_subband.select == tb.subband_i + 1, 1); % find index of subband_i in selected subbands
+
+tchan_all = (1: Mchan*Msync*Kchan)/Kchan; % time in channel periods for block of selected subbands channels
+tchan_one = (1: tb.nof_tchan); % time in channel periods for one subband
+
+%chan_i =
% Plot DT output
fig=fig+1;
-figure('position', [300+fig*20 200-fig*20 1000 800]);
+figure('position', [300+fig*20 200-fig*10 1000 800]);
figure(fig);
data = data_dt';
plot(ts, data(:))
ylim([-1.3 1.3]);
-title(sprintf('Delay tracking output data (WG subband %6.3f)', tb.subband_nr));
-xlabel('Time [T bsn]');
+title(sprintf('Delay tracking output data (WG subband %6.3f)', tb.subband_wg));
+xlabel(sprintf('Time 1:%d [Tsub]', tb.nof_tsub));
ylabel('Voltage');
grid on;
@@ -235,7 +356,7 @@ hf_abs = abs(fftshift(fft(h / sum(h), NL)));
hi = 1:NL; % coefficients index
fx = (hi - NL/2-1) / L; % frequency axis in subband units
fig=fig+1;
-figure('position', [300+fig*20 200-fig*20 1000 800]);
+figure('position', [300+fig*20 200-fig*10 1000 800]);
figure(fig);
plot(fx, db(hf_abs)); % db() = 20*log10 for voltage
%xlim([-3 3]);
@@ -246,91 +367,141 @@ ylabel('Magnitude [dB]');
% Plot subband PFIR output
fig=fig+1;
-figure('position', [300+fig*20 200-fig*20 1000 800]);
+figure('position', [300+fig*20 200-fig*10 1000 800]);
figure(fig);
data = data_pfir_subband';
plot(ts, data(:))
-title(sprintf('Subband polyphase FIR filter output - FFT input data (WG subband %6.3f)', tb.subband_nr));
-ylim([-2 2]); % DT step when tb.subband_nr is .5 causes double range
-xlabel('Time [T bsn]');
+title(sprintf('Subband polyphase FIR filter output - FFT input data (WG subband %6.3f)', tb.subband_wg));
+ylim([-2 2]); % DT step when tb.subband_wg is .5 causes double range
+xlabel(sprintf('Time 1:%d [Tsub]', tb.nof_tsub));
ylabel('Voltage');
grid on;
% Plot PFFT subbands spectrum and phase
-ampl = abs(data_pfft_subband);
-phase = angle(data_pfft_subband)*180/pi;
-noise = ampl < 0.1*max(ampl(:));
-phase(noise) = 0; % force phase of too small signals to 0
+sub_ampl = abs(data_pfft_subband);
+sub_ampl_max = max(sub_ampl(:));
+sub_phase = angle(data_pfft_subband)*180/pi;
+x = sub_ampl < 0.1*sub_ampl_max;
+sub_phase(x) = 0; % force phase of too small signals to 0
fig=fig+1;
-figure('position', [300+fig*20 200-fig*20 1000 800]);
+figure('position', [300+fig*20 200-fig*10 1000 800]);
figure(fig);
subplot(2,1,1);
-data = ampl';
-plot(tsub, data(:))
-title('Subband data - amplitude');
-xlabel(sprintf('Subband 0:%d at time [T bsn]', tb.nof_subbands-1));
+data = sub_ampl';
+data = data(:);
+plot(tsub_all, data, 'k', tsub_all(sub_i), data(sub_i), 'ko', tsub_all(sub_i+1), data(sub_i+1), 'kx');
+title(sprintf('Subband data - amplitude (o = subband index %d for WG subband = %6.3f, x = next)', tb.subband_i, tb.subband_wg));
+xlabel(sprintf('Subbands 0:%d at time 1:%d [Tsub]', tb.nof_subbands-1, tb.nof_tsub));
ylabel('Voltage');
grid on;
subplot(2,1,2);
-data = phase';
-plot(tsub, data(:))
+data = sub_phase';
+data = data(:);
+plot(tsub_all, data, 'k', tsub_all(sub_i), data(sub_i), 'ko', tsub_all(sub_i+1), data(sub_i+1), 'kx');
ylim([-180 180])
-title('Subband data - phase');
-xlabel(sprintf('Subband 0:%d at time [T bsn]', tb.nof_subbands-1));
+title(sprintf('Subband data - amplitude (o = subband index %d for WG subband = %6.3f, x = next)', tb.subband_i, tb.subband_wg));
+xlabel(sprintf('Subbands 0:%d at time 1:%d [Tsub]', tb.nof_subbands-1, tb.nof_tsub));
ylabel('Phase [degrees]');
grid on;
% Plot phase step due to DT step for the subband that is set in the WG
-%phase = angle(data_pfft_subband(:, tb.subband_i + 1))*180/pi;
-phase = angle(data_reorder_subband(:,1))*180/pi;
-
+if isempty(sel_sub_i)
+ wg_sub_phase = angle(data_pfft_subband(:, tb.subband_i + 1))*180/pi; % use Matlab indexing if subband is not selected
+else
+ wg_sub_phase = angle(data_reorder_subband(:, sel_sub_i))*180/pi; % use functional reorder subband
+end
fig=fig+1;
-figure('position', [300+fig*20 200-fig*20 1000 800]);
+figure('position', [300+fig*20 200-fig*10 1000 800]);
figure(fig);
-plot(tblock, phase, '-o')
+plot(tsub_one, wg_sub_phase, '-o')
ylim([-180 180])
title(sprintf('Subband phase for subband %d in range 0:%d', tb.subband_i, tb.nof_subbands-1));
-xlabel('Time [T bsn]');
+xlabel(sprintf('Time 1:%d [Tsub]', tb.nof_tsub));
ylabel('Phase [degrees]');
grid on;
% Plot subband spectrogram
fig=fig+1;
-figure('position', [300+fig*20 200-fig*20 1000 800]);
+figure('position', [300+fig*20 200-fig*10 1000 800]);
figure(fig);
-data = abs(data_pfft_subband);
-data_abs_max = max(data(:));
-data = db(data); % no need to scale data, range is already normalized
+data = db(sub_ampl); % no need to scale data, range is already normalized
x = ctrl_spec_subband.db_low;
-%x = floor(min(data(data~=-Inf)))
data(data<x) = x;
mymap = jet(-x);
-%mymap(1,:) = [0 0 0]; % force black for dB(0)
colormap(mymap);
imagesc(data',[x 0]);
colorbar;
-title(sprintf('Subband spectogram (max value = %f = %f dB)', data_abs_max, db(data_abs_max)));
-xlabel('Time [T bsn]');
-ylabel('Subband');
+title(sprintf('Subband spectogram (max value = %f = %f dB)', sub_ampl_max, db(sub_ampl_max)));
+xlabel(sprintf('Time 1:%d [Tsub]', tb.nof_tsub));
+ylabel(sprintf('Subbands 1:%d', tb.nof_subbands));
% Plot corner turn subband spectrogram
fig=fig+1;
-figure('position', [300+fig*20 200-fig*20 1000 800]);
+figure('position', [300+fig*20 200-fig*10 1000 800]);
figure(fig);
-data = data_corner_turn(1,:); % take one sync interval
-data = reshape(data, ctrl_corner_turn.tail_nof_block+ctrl_corner_turn.nof_block, ctrl_corner_turn.block_size);
-data = abs(data);
-data_abs_max = max(data(:));
-data = db(data); % no need to scale data, range is already normalized
+ct_sub_data = data_corner_turn(1,:); % take one sync interval
+ct_sub_data = reshape(ct_sub_data, ctrl_corner_turn.tail_nof_block+ctrl_corner_turn.nof_block, ctrl_corner_turn.block_size);
+if ctrl_corner_turn.tail_nof_block>0
+ ct_sub_data = ct_sub_data(ctrl_corner_turn.tail_nof_block+1:ctrl_corner_turn.tail_nof_block+ctrl_corner_turn.nof_block, :);
+end
+ct_sub_ampl = abs(ct_sub_data);
+ct_sub_ampl_max = max(ct_sub_ampl(:));
+data = db(ct_sub_ampl); % no need to scale data, range is already normalized
x = ctrl_spec_subband.db_low;
-%x = floor(min(data(data~=-Inf)))
data(data<x) = x;
mymap = jet(-x);
-%mymap(1,:) = [0 0 0]; % force black for dB(0)
colormap(mymap);
imagesc(data',[x 0]);
colorbar;
-title(sprintf('Corner turn subband spectogram (max value = %f = %f dB)', data_abs_max, db(data_abs_max)));
-xlabel('Time [T bsn]');
-ylabel('Subband');
+title(sprintf('Corner turn subband spectogram for 1 sync interval (max value = %f = %f dB)', ct_sub_ampl_max, db(ct_sub_ampl_max)));
+xlabel(sprintf('Time 1:%d [Tsub]', Msub));
+ylabel(sprintf('%d selected subbands', Ksub));
+
+% Plot PFFT channel spectrum and phase
+% - Matlab has fastest array index first, Python has fastest array index last
+data = reshape(data_pfft_channel, [Nchan, Mchan, Ksub, Msync]); % Matlab data[Nchan][Mchan][Ksub][Msync]
+data = permute(data, [2,4,1,3]); % Matlab data[Mchan][Msync][Nchan][Ksub]
+data = reshape(data, [Mchan*Msync, Nchan*Ksub]); % group time samples across sync intervals and group channels across subbands
+
+chan_ampl = abs(data);
+chan_ampl_max = max(chan_ampl(:));
+chan_phase = angle(data)*180/pi;
+x = chan_ampl < 0.1*chan_ampl_max;
+chan_phase(x) = 0; % force phase of too small signals to 0
+
+fig=fig+1;
+figure('position', [300+fig*20 200-fig*10 1000 800]);
+figure(fig);
+subplot(2,1,1);
+data = chan_ampl';
+data = data(:);
+plot(tchan_all, data)
+title('Channel data - amplitude');
+xlabel(sprintf('%d channels (0:%d from %d selected subbands) at time 1:%d [Tchan]', Kchan, Nchan-1, Ksub, tb.nof_tchan));
+ylabel('Voltage');
+grid on;
+subplot(2,1,2);
+data = chan_phase';
+data = data(:);
+plot(tchan_all, data)
+ylim([-180 180])
+title('Channel data - phase');
+xlabel(sprintf('%d channels (0:%d from %d selected subbands) at time 1:%d [Tchan]', Kchan, Nchan-1, Ksub, tb.nof_tchan));
+ylabel('Phase [degrees]');
+grid on;
+
+% Plot channel spectrogram
+fig=fig+1;
+figure('position', [300+fig*20 200-fig*10 1000 800]);
+figure(fig);
+data = db(chan_ampl); % no need to scale data, range is already normalized
+x = ctrl_spec_channel.db_low;
+data(data<x) = x;
+mymap = jet(-x);
+colormap(mymap);
+imagesc(data',[x 0]);
+colorbar;
+title(sprintf('Channel spectogram (max value = %f = %f dB)', chan_ampl_max, db(chan_ampl_max)));
+xlabel(sprintf('Time 1:%d [Tchan]', tb.nof_tchan));
+ylabel(sprintf('%d channels (0:%d from %d selected subbands)', Kchan, Nchan-1, Ksub));
diff --git a/applications/apertif/matlab/wg.m b/applications/apertif/matlab/wg.m
index f447fe8999cf2913c8b0cdf5290606f82efdd047..a877842ce13e8964461dd75d80b8ec21b9529aa3 100644
--- a/applications/apertif/matlab/wg.m
+++ b/applications/apertif/matlab/wg.m
@@ -24,6 +24,7 @@
% Description :
% The WG data is normalized to -1:1. Data outside this range is clipped,
% so use ampl >> 1 to create square wave.
+% With df ~= 0 the WG creates a chirp.
function [state, data] = wg(ctrl)
@@ -52,4 +53,5 @@ end
% Keep state for next call
state = ctrl;
+state.freq = ctrl.freq+ctrl.df;
state.phase = ctrl.freq*ctrl.block_size+ctrl.phase;
diff --git a/applications/apertif/systems/apertif_bf_xc/hdllib.cfg b/applications/apertif/systems/apertif_bf_xc/hdllib.cfg
index abf264eb9f6ce09e502412080cc83f59cf914435..4bd1feb4d128cc4659f6cf83ecb252ffd6376d07 100644
--- a/applications/apertif/systems/apertif_bf_xc/hdllib.cfg
+++ b/applications/apertif/systems/apertif_bf_xc/hdllib.cfg
@@ -4,10 +4,14 @@ hdl_lib_uses_synth =
hdl_lib_uses_sim = apertif_unb1_correlator apertif_unb1_fn_beamformer
hdl_lib_technology = ip_stratixiv
-modelsim_copy_files =
-
synth_files =
test_bench_files =
tb/vhdl/tb_apertif_bf_xc.vhd
+
+[modelsim_project_file]
+modelsim_copy_files =
+
+
+[quartus_project_file]
diff --git a/applications/apertif/systems/apertif_bg_xc/hdllib.cfg b/applications/apertif/systems/apertif_bg_xc/hdllib.cfg
index 7ae12bb31098439abee588736b0fb0cf9a2ffe58..05bbee6d5ca8bddca187c1e16bf8d1889e3260cb 100644
--- a/applications/apertif/systems/apertif_bg_xc/hdllib.cfg
+++ b/applications/apertif/systems/apertif_bg_xc/hdllib.cfg
@@ -2,15 +2,18 @@ hdl_lib_name = apertif_bg_xc
hdl_library_clause_name = apertif_bg_xc_lib
hdl_lib_uses_synth =
hdl_lib_uses_sim = apertif_unb1_correlator apertif_unb1_fn_bf_emu
-
hdl_lib_technology = ip_stratixiv
-modelsim_copy_files =
- ../../designs/apertif_unb1_fn_bf_emu/src/hex/ hex/
- $RADIOHDL/libraries/dsp/filter/src/hex/ mif
-
synth_files =
test_bench_files =
tb/vhdl/tb_apertif_bg_xc.vhd
+
+[modelsim_project_file]
+modelsim_copy_files =
+ ../../designs/apertif_unb1_fn_bf_emu/src/hex/ hex/
+ $RADIOHDL/libraries/dsp/filter/src/hex/ mif
+
+
+[quartus_project_file]
diff --git a/applications/arts/designs/arts_unb1_bg_offload/hdllib.cfg b/applications/arts/designs/arts_unb1_bg_offload/hdllib.cfg
index e72d0e95433ccd4f20de6ea6467be37e3aa9d19d..a8900ed80b7ac41fa640b8f1f859b511bdc3fabd 100644
--- a/applications/arts/designs/arts_unb1_bg_offload/hdllib.cfg
+++ b/applications/arts/designs/arts_unb1_bg_offload/hdllib.cfg
@@ -1,27 +1,37 @@
hdl_lib_name = arts_unb1_bg_offload
hdl_library_clause_name = arts_unb1_bg_offload_lib
hdl_lib_uses_synth = common dp mm diag unb1_board
+hdl_lib_technology = ip_stratixiv
+
synth_files =
src/vhdl/arts_offload_fifo.vhd
src/vhdl/mm_master.vhd
src/vhdl/arts_unb1_bg_offload.vhd
-synth_top_level_entity =
+
test_bench_files =
tb/vhdl/tb_arts_unb1_bg_offload.vhd
-quartus_copy_files =
- quartus/qsys_mm_master.qsys .
- src/hex hex
+
+[modelsim_project_file]
modelsim_copy_files =
src/hex hex
-hdl_lib_technology = ip_stratixiv
+
+[quartus_project_file]
+synth_top_level_entity =
+
+quartus_copy_files =
+ quartus/qsys_mm_master.qsys .
+ src/hex hex
+
quartus_qsf_files =
$RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+
quartus_sdc_files =
$RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
quartus_qip_files =
$HDL_BUILD_DIR/unb1/quartus/arts_unb1_bg_offload/qsys_mm_master/synthesis/qsys_mm_master.qip
+
quartus_tcl_files =
-$RADIOHDL/applications/arts/designs/arts_unb1_bg_offload/quartus/pinning/arts_unb1_bg_offload_pins.tcl
+ $RADIOHDL/applications/arts/designs/arts_unb1_bg_offload/quartus/pinning/arts_unb1_bg_offload_pins.tcl
diff --git a/applications/arts/designs/arts_unb1_sc1/src/generated/hdllib.cfg b/applications/arts/designs/arts_unb1_sc1/src/generated/hdllib.cfg
index b85e8ade457de71871d486f0dee5081b9d582eaa..890c2b8d4e50c5bd8e5cff7759dfd1b59342c524 100644
--- a/applications/arts/designs/arts_unb1_sc1/src/generated/hdllib.cfg
+++ b/applications/arts/designs/arts_unb1_sc1/src/generated/hdllib.cfg
@@ -1,24 +1,35 @@
hdl_lib_name = arts_unb1_sc1_bg_single_pol
hdl_library_clause_name = arts_unb1_sc1_bg_single_pol_lib
hdl_lib_uses_synth = common dp mm diag bf unb1_board
+hdl_lib_technology = ip_stratixiv
+
synth_files =
../arts_unb1_sc1_offload.vhd
../generated/mm_master.vhd
../generated/arts_unb1_sc1_bg_single_pol.vhd
-synth_top_level_entity =
+
test_bench_files =
tb_arts_unb1_sc1_bg_single_pol.vhd
+
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+synth_top_level_entity =
+
quartus_copy_files =
qsys_mm_master.qsys .
-hdl_lib_technology = ip_stratixiv
quartus_qsf_files =
$RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+
quartus_sdc_files =
-
-$RADIOHDL/applications/arts/designs/arts_unb1_sc1/quartus/arts_unb1_sc1_bg_single_pol.sdc
+ $RADIOHDL/applications/arts/designs/arts_unb1_sc1/quartus/arts_unb1_sc1_bg_single_pol.sdc
+
quartus_qip_files =
$HDL_BUILD_DIR/unb1/quartus/arts_unb1_sc1_bg_single_pol/qsys_mm_master/synthesis/qsys_mm_master.qip
$HDL_BUILD_DIR/unb2/quartus/arts_unb1_sc1_bg_single_pol/qsys_mm_master/synthesis/qsys_mm_master.qip
+
quartus_tcl_files =
arts_unb1_sc1_bg_single_pol_pins.tcl
diff --git a/applications/arts/designs/arts_unb1_sc1_bf_offload/hdllib.cfg b/applications/arts/designs/arts_unb1_sc1_bf_offload/hdllib.cfg
index 05e807f0451fd163542c28b2ea2bf1c9542fe43b..d6dd13bdebe2edba318c0e0301ded7d1f102672b 100644
--- a/applications/arts/designs/arts_unb1_sc1_bf_offload/hdllib.cfg
+++ b/applications/arts/designs/arts_unb1_sc1_bf_offload/hdllib.cfg
@@ -2,29 +2,38 @@ hdl_lib_name = arts_unb1_sc1_bf_offload
hdl_library_clause_name = arts_unb1_sc1_bf_offload_lib
hdl_lib_uses_synth = common dp mm diag bf tr_10GbE apertif unb1_board
hdl_lib_uses_sim = apertif_unb1_fn_bf_emu
+hdl_lib_technology = ip_stratixiv
+
synth_files =
src/vhdl/arts_offload_fifo.vhd
src/vhdl/mm_master.vhd
src/vhdl/arts_unb1_sc1_bf_offload.vhd
-synth_top_level_entity =
+
test_bench_files =
tb/vhdl/tb_arts_unb1_sc1_bf_offload.vhd
-quartus_copy_files =
- quartus/qsys_mm_master.qsys .
- src/hex hex
+
+[modelsim_project_file]
modelsim_copy_files =
../../../apertif/designs/apertif_unb1_fn_bf_emu/src/hex/ hex
src/hex hex
-hdl_lib_technology = ip_stratixiv
+
+[quartus_project_file]
+synth_top_level_entity =
+
+quartus_copy_files =
+ quartus/qsys_mm_master.qsys .
+ src/hex hex
+
quartus_qsf_files =
$RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
quartus_qip_files =
$HDL_BUILD_DIR/unb1/quartus/arts_unb1_sc1_bf_offload/qsys_mm_master/synthesis/qsys_mm_master.qip
+
quartus_tcl_files =
-$RADIOHDL/applications/arts/designs/arts_unb1_sc1_bf_offload/quartus/pinning/arts_unb1_sc1_bf_offload_pins.tcl
+ $RADIOHDL/applications/arts/designs/arts_unb1_sc1_bf_offload/quartus/pinning/arts_unb1_sc1_bf_offload_pins.tcl
quartus_sdc_files =
$RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
diff --git a/applications/arts/designs/arts_unb2_sc1/src/generated/hdllib.cfg b/applications/arts/designs/arts_unb2_sc1/src/generated/hdllib.cfg
index 6ab5d2f99200971fc423d3328e4c789542fa1100..d35b91c4985ce030a56265e4b50cf00db051d055 100644
--- a/applications/arts/designs/arts_unb2_sc1/src/generated/hdllib.cfg
+++ b/applications/arts/designs/arts_unb2_sc1/src/generated/hdllib.cfg
@@ -1,24 +1,35 @@
hdl_lib_name = arts_unb2_sc1_bg_single_pol
hdl_library_clause_name = arts_unb2_sc1_bg_single_pol_lib
hdl_lib_uses_synth = common dp mm diag bf unb2_board
+hdl_lib_technology = ip_arria10
+
synth_files =
../arts_sc1_offload.vhd
../generated/mm_master.vhd
../generated/arts_unb2_sc1_bg_single_pol.vhd
-synth_top_level_entity =
+
test_bench_files =
tb_arts_unb2_sc1_bg_single_pol.vhd
+
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+synth_top_level_entity =
+
quartus_copy_files =
qsys_mm_master.qsys .
-hdl_lib_technology = ip_arria10
quartus_qsf_files =
$RADIOHDL/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
+
quartus_sdc_files =
-
-$RADIOHDL/applications/arts/designs/arts_unb2_sc1/quartus/arts_unb2_sc1_bg_single_pol.sdc
+ $RADIOHDL/applications/arts/designs/arts_unb2_sc1/quartus/arts_unb2_sc1_bg_single_pol.sdc
+
quartus_qip_files =
$HDL_BUILD_DIR/unb1/quartus/arts_unb2_sc1_bg_single_pol/qsys_mm_master/synthesis/qsys_mm_master.qip
$HDL_BUILD_DIR/unb2/quartus/arts_unb2_sc1_bg_single_pol/qsys_mm_master/synthesis/qsys_mm_master.qip
+
quartus_tcl_files =
-$RADIOHDL/applications/arts/designs/arts_unb2_sc1/quartus/pinning/arts_unb2_sc1_bg_single_pol_pins.tcl
+ $RADIOHDL/applications/arts/designs/arts_unb2_sc1/quartus/pinning/arts_unb2_sc1_bg_single_pol_pins.tcl
diff --git a/applications/arts/designs/arts_unb2a_fmax_test/src/generated/hdllib.cfg b/applications/arts/designs/arts_unb2a_fmax_test/src/generated/hdllib.cfg
index d11d49fd79d09d9d1cde004b4a983c604bf55f0e..6929f6a45a5bf32e7c4f9473dc20480747ac1f5a 100644
--- a/applications/arts/designs/arts_unb2a_fmax_test/src/generated/hdllib.cfg
+++ b/applications/arts/designs/arts_unb2a_fmax_test/src/generated/hdllib.cfg
@@ -1,23 +1,34 @@
hdl_lib_name = arts_unb2a_fmax_test
hdl_library_clause_name = arts_unb2a_fmax_test_lib
hdl_lib_uses_synth = common dp mm diag bf unb2a_board
+hdl_lib_technology = ip_arria10_e3sge3
+
synth_files =
../arts_sc1_offload.vhd
../generated/mm_master.vhd
../generated/arts_unb2a_fmax_test.vhd
-synth_top_level_entity =
+
test_bench_files =
tb_arts_unb2a_fmax_test.vhd
+
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+synth_top_level_entity =
+
quartus_copy_files =
qsys_mm_master.qsys .
-hdl_lib_technology = ip_arria10_e3sge3
quartus_qsf_files =
$RADIOHDL/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf
+
quartus_sdc_files =
-
-$RADIOHDL/applications/arts/designs/arts_unb2a_fmax_test/quartus/arts_unb2a_fmax_test.sdc
+ $RADIOHDL/applications/arts/designs/arts_unb2a_fmax_test/quartus/arts_unb2a_fmax_test.sdc
+
quartus_qip_files =
$HDL_BUILD_DIR/unb2a/quartus/arts_unb2a_fmax_test/qsys_mm_master/synthesis/qsys_mm_master.qip
+
quartus_tcl_files =
-$RADIOHDL/applications/arts/designs/arts_unb2a_fmax_test/quartus/pinning/arts_unb2a_fmax_test_pins.tcl
+ $RADIOHDL/applications/arts/designs/arts_unb2a_fmax_test/quartus/pinning/arts_unb2a_fmax_test_pins.tcl
diff --git a/applications/compaan/designs/compaan_unb1_10g/hdllib.cfg b/applications/compaan/designs/compaan_unb1_10g/hdllib.cfg
index b10d8221417fe014dbea7b5ebbc229ce37ef279e..a419fe77cf3592018c432d3e2bd8ec1619b1eba2 100644
--- a/applications/compaan/designs/compaan_unb1_10g/hdllib.cfg
+++ b/applications/compaan/designs/compaan_unb1_10g/hdllib.cfg
@@ -3,11 +3,6 @@ hdl_library_clause_name = compaan_unb1_10g_lib
hdl_lib_uses_synth = common unb1_board dp eth tech_tse diag compaan tr_10GbE
hdl_lib_technology = ip_stratixiv
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
-
-synth_top_level_entity =
-
synth_files =
$HDL_BUILD_DIR/unb1/quartus/compaan_unb1_10g/sopc_compaan_unb1_10g.vhd
src/vhdl/pkg_signals.vhd
@@ -17,6 +12,13 @@ synth_files =
test_bench_files =
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+synth_top_level_entity =
+
quartus_copy_files = quartus/sopc_compaan_unb1_10g.sopc .
quartus_qsf_files =
diff --git a/applications/compaan/designs/compaan_unb1_10g/revisions/compaan_unb1_10g_blockgen/hdllib.cfg b/applications/compaan/designs/compaan_unb1_10g/revisions/compaan_unb1_10g_blockgen/hdllib.cfg
index cd09351a98f468e20696a6c5c39f0ab2dce5fc6b..c112ae55f5a5992cbcae22446422d2396ce64038 100644
--- a/applications/compaan/designs/compaan_unb1_10g/revisions/compaan_unb1_10g_blockgen/hdllib.cfg
+++ b/applications/compaan/designs/compaan_unb1_10g/revisions/compaan_unb1_10g_blockgen/hdllib.cfg
@@ -3,11 +3,6 @@ hdl_library_clause_name = compaan_unb1_10g_blockgen_lib
hdl_lib_uses_synth = common unb1_board dp eth tech_tse diag compaan tr_10GbE
hdl_lib_technology = ip_stratixiv
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
-
-synth_top_level_entity =
-
synth_files =
$HDL_BUILD_DIR/unb1/quartus/compaan_unb1_10g_blockgen/sopc_compaan_unb1_10g.vhd
../../src/vhdl/pkg_signals.vhd
@@ -19,6 +14,13 @@ synth_files =
test_bench_files =
../../tb/vhdl/tb_compaan_unb1_10g_bg_lb.vhd
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+synth_top_level_entity =
+
quartus_copy_files = ../../quartus/sopc_compaan_unb1_10g.sopc .
quartus_qsf_files =
@@ -31,6 +33,3 @@ quartus_qip_files = $HDL_BUILD_DIR/unb1/quartus/compaan_unb1_10g_blockgen/sopc_c
quartus_sdc_files =
$RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
-
-
-
diff --git a/applications/compaan/designs/compaan_unb1_10g/revisions/compaan_unb1_10g_compaan/hdllib.cfg b/applications/compaan/designs/compaan_unb1_10g/revisions/compaan_unb1_10g_compaan/hdllib.cfg
index 93b20f4422a9c8eee1b068d2b398cba8121f509b..ce349bed0b721b98b9b14125fae3ba86986dd6b8 100644
--- a/applications/compaan/designs/compaan_unb1_10g/revisions/compaan_unb1_10g_compaan/hdllib.cfg
+++ b/applications/compaan/designs/compaan_unb1_10g/revisions/compaan_unb1_10g_compaan/hdllib.cfg
@@ -3,11 +3,6 @@ hdl_library_clause_name = compaan_unb1_10g_compaan_lib
hdl_lib_uses_synth = common unb1_board dp eth tech_tse diag compaan tr_10GbE
hdl_lib_technology = ip_stratixiv
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
-
-synth_top_level_entity =
-
synth_files =
$HDL_BUILD_DIR/unb1/quartus/compaan_unb1_10g_compaan/sopc_compaan_unb1_10g.vhd
../../src/vhdl/pkg_signals.vhd
@@ -19,6 +14,13 @@ synth_files =
test_bench_files =
../../tb/vhdl/tb_compaan_unb1_10g_bg_lb.vhd
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+synth_top_level_entity =
+
quartus_copy_files = ../../quartus/sopc_compaan_unb1_10g.sopc .
quartus_qsf_files =
diff --git a/applications/compaan/designs/compaan_unb1_10g/revisions/compaan_unb1_10g_loopback/hdllib.cfg b/applications/compaan/designs/compaan_unb1_10g/revisions/compaan_unb1_10g_loopback/hdllib.cfg
index 4f8a6d41c5b71fe8ecaa6a7212d29f128d26d215..80581ea1422f69081484da1cd211575d52cacd45 100644
--- a/applications/compaan/designs/compaan_unb1_10g/revisions/compaan_unb1_10g_loopback/hdllib.cfg
+++ b/applications/compaan/designs/compaan_unb1_10g/revisions/compaan_unb1_10g_loopback/hdllib.cfg
@@ -3,11 +3,6 @@ hdl_library_clause_name = compaan_unb1_10g_loopback_lib
hdl_lib_uses_synth = common unb1_board dp eth tech_tse diag compaan tr_10GbE
hdl_lib_technology = ip_stratixiv
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
-
-synth_top_level_entity =
-
synth_files =
$HDL_BUILD_DIR/unb1/quartus/compaan_unb1_10g_loopback/sopc_compaan_unb1_10g.vhd
../../src/vhdl/pkg_signals.vhd
@@ -19,6 +14,13 @@ synth_files =
test_bench_files =
../../tb/vhdl/tb_compaan_unb1_10g_bg_lb.vhd
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+synth_top_level_entity =
+
quartus_copy_files = ../../quartus/sopc_compaan_unb1_10g.sopc .
quartus_qsf_files =
diff --git a/applications/compaan/designs/compaan_unb1_10g_app/hdllib.cfg b/applications/compaan/designs/compaan_unb1_10g_app/hdllib.cfg
index 2a1a20d4299a0bc0eccbf1570f4d1e5789b9efa3..3f88257c579bde28e75cefe4e51169107f5b53f7 100644
--- a/applications/compaan/designs/compaan_unb1_10g_app/hdllib.cfg
+++ b/applications/compaan/designs/compaan_unb1_10g_app/hdllib.cfg
@@ -3,8 +3,6 @@ hdl_library_clause_name = compaan_unb1_10g_app_lib
hdl_lib_uses_synth = common unb1_board dp eth tech_tse diag tr_10GbE compaan
hdl_lib_technology = ip_stratixiv
-synth_top_level_entity =
-
synth_files =
src/vhdl/compaan_unb1_10g_pkg.vhd
src/vhdl/compaan_design.vhd
@@ -16,6 +14,13 @@ synth_files =
test_bench_files =
tb/vhdl/tb_compaan_unb1_10g_app.vhd
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+synth_top_level_entity =
+
quartus_copy_files = quartus/qsys_compaan_unb1_10g_app.qsys .
quartus_qsf_files =
diff --git a/applications/compaan/designs/compaan_unb1_10g_bg_db/hdllib.cfg b/applications/compaan/designs/compaan_unb1_10g_bg_db/hdllib.cfg
index 9966e451d9d13506a7cc588a7b6a524bececd83d..8b18f9298c841fa877dd540d61fe10ecbe0af9d0 100644
--- a/applications/compaan/designs/compaan_unb1_10g_bg_db/hdllib.cfg
+++ b/applications/compaan/designs/compaan_unb1_10g_bg_db/hdllib.cfg
@@ -3,8 +3,6 @@ hdl_library_clause_name = compaan_unb1_10g_bg_db_lib
hdl_lib_uses_synth = common unb1_board dp eth tech_tse diag tr_10GbE
hdl_lib_technology = ip_stratixiv
-synth_top_level_entity =
-
synth_files =
src/vhdl/mmm_compaan_unb1_10g_bg_db.vhd
src/vhdl/compaan_unb1_10g_bg_db.vhd
@@ -12,6 +10,13 @@ synth_files =
test_bench_files =
tb/vhdl/tb_compaan_unb1_10g_bg_db.vhd
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+synth_top_level_entity =
+
quartus_copy_files = quartus/qsys_compaan_unb1_10g_bg_db.qsys .
quartus_qsf_files =
diff --git a/applications/compaan/designs/compaan_unb1_dp_offload/hdllib.cfg b/applications/compaan/designs/compaan_unb1_dp_offload/hdllib.cfg
index b42a7fd064a7e0ec0000dd0a3aaed82de2dce82c..107cb2864a3f25d186686fcadc321d47e1ec3cd5 100644
--- a/applications/compaan/designs/compaan_unb1_dp_offload/hdllib.cfg
+++ b/applications/compaan/designs/compaan_unb1_dp_offload/hdllib.cfg
@@ -3,9 +3,6 @@ hdl_library_clause_name = compaan_unb1_dp_offload_lib
hdl_lib_uses_synth = common unb1_board dp eth tech_tse diag compaan
hdl_lib_technology = ip_stratixiv
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
-
synth_files =
$HDL_BUILD_DIR/quartus/compaan_unb1_dp_offload/sopc_compaan_unb1_dp_offload.vhd
src/vhdl/pkg_signals.vhd
@@ -19,6 +16,11 @@ test_bench_files =
tb/vhdl/tb_compaan_unb1_dp_offload_bg_lb.vhd
tb/vhdl/tb_compaan_unb1_dp_offload_bg_co.vhd
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
quartus_sdc_files =
$RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
diff --git a/applications/compaan/designs/compaan_unb1_dp_offload/revisions/compaan_unb1_dp_offload_bg/hdllib.cfg b/applications/compaan/designs/compaan_unb1_dp_offload/revisions/compaan_unb1_dp_offload_bg/hdllib.cfg
index 45e1ee166e8d0425e0c7858ff79cb4a756efe300..11b0b21ce8fd708cb0dfa0acecf2dd0186328cd6 100644
--- a/applications/compaan/designs/compaan_unb1_dp_offload/revisions/compaan_unb1_dp_offload_bg/hdllib.cfg
+++ b/applications/compaan/designs/compaan_unb1_dp_offload/revisions/compaan_unb1_dp_offload_bg/hdllib.cfg
@@ -3,11 +3,6 @@ hdl_library_clause_name = compaan_unb1_dp_offload_bg_lib
hdl_lib_uses_synth = common unb1_board dp eth tech_tse diag compaan
hdl_lib_technology = ip_stratixiv
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
-
-synth_top_level_entity =
-
synth_files =
$HDL_BUILD_DIR/unb1/quartus/compaan_unb1_dp_offload_bg/sopc_compaan_unb1_dp_offload.vhd
../../src/vhdl/pkg_signals.vhd
@@ -22,6 +17,13 @@ test_bench_files =
../../tb/vhdl/tb_compaan_unb1_dp_offload_bg_lb.vhd
../../tb/vhdl/tb_compaan_unb1_dp_offload_bg_co.vhd
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+synth_top_level_entity =
+
quartus_copy_files = ../../quartus/sopc_compaan_unb1_dp_offload.sopc .
quartus_qsf_files =
diff --git a/applications/compaan/designs/compaan_unb1_dp_offload/revisions/compaan_unb1_dp_offload_co/hdllib.cfg b/applications/compaan/designs/compaan_unb1_dp_offload/revisions/compaan_unb1_dp_offload_co/hdllib.cfg
index 40bb05306dc1608eb191a4f4f240847524e49bd8..369565cb0a527b105b5d25f171b345891ad23580 100644
--- a/applications/compaan/designs/compaan_unb1_dp_offload/revisions/compaan_unb1_dp_offload_co/hdllib.cfg
+++ b/applications/compaan/designs/compaan_unb1_dp_offload/revisions/compaan_unb1_dp_offload_co/hdllib.cfg
@@ -3,11 +3,6 @@ hdl_library_clause_name = compaan_unb1_dp_offload_co_lib
hdl_lib_uses_synth = common unb1_board dp eth tech_tse diag compaan
hdl_lib_technology = ip_stratixiv
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
-
-synth_top_level_entity =
-
synth_files =
$HDL_BUILD_DIR/unb1/quartus/compaan_unb1_dp_offload_co/sopc_compaan_unb1_dp_offload.vhd
../../src/vhdl/pkg_signals.vhd
@@ -22,6 +17,14 @@ test_bench_files =
../../tb/vhdl/tb_compaan_unb1_dp_offload_bg_lb.vhd
../../tb/vhdl/tb_compaan_unb1_dp_offload_bg_co.vhd
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+synth_top_level_entity =
+
+
quartus_copy_files = ../../quartus/sopc_compaan_unb1_dp_offload.sopc .
quartus_qsf_files =
diff --git a/applications/compaan/designs/compaan_unb1_dp_offload/revisions/compaan_unb1_dp_offload_lb/hdllib.cfg b/applications/compaan/designs/compaan_unb1_dp_offload/revisions/compaan_unb1_dp_offload_lb/hdllib.cfg
index bf3f9147aa2929e05a20d7e2dd0549474a6006a6..42fbe5f127313593d98dcefaecae58fcd48c19b3 100644
--- a/applications/compaan/designs/compaan_unb1_dp_offload/revisions/compaan_unb1_dp_offload_lb/hdllib.cfg
+++ b/applications/compaan/designs/compaan_unb1_dp_offload/revisions/compaan_unb1_dp_offload_lb/hdllib.cfg
@@ -3,11 +3,6 @@ hdl_library_clause_name = compaan_unb1_dp_offload_lb_lib
hdl_lib_uses_synth = common unb1_board dp eth tech_tse diag compaan
hdl_lib_technology = ip_stratixiv
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
-
-synth_top_level_entity =
-
synth_files =
$HDL_BUILD_DIR/unb1/quartus/compaan_unb1_dp_offload_lb/sopc_compaan_unb1_dp_offload.vhd
../../src/vhdl/pkg_signals.vhd
@@ -22,6 +17,13 @@ test_bench_files =
../../tb/vhdl/tb_compaan_unb1_dp_offload_bg_lb.vhd
../../tb/vhdl/tb_compaan_unb1_dp_offload_bg_co.vhd
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+synth_top_level_entity =
+
quartus_copy_files = ../../quartus/sopc_compaan_unb1_dp_offload.sopc .
quartus_qsf_files =
diff --git a/applications/compaan/libraries/hdllib.cfg b/applications/compaan/libraries/hdllib.cfg
index 88538c1211caa775e184c104fd3d01828caf204c..d3cbec3c2472db877bf69472758682d529b1b58b 100644
--- a/applications/compaan/libraries/hdllib.cfg
+++ b/applications/compaan/libraries/hdllib.cfg
@@ -1,7 +1,6 @@
hdl_lib_name = compaan
hdl_library_clause_name = compaan_lib
hdl_lib_uses_synth = common technology ip_arria10_fifo ip_stratixiv_fifo tech_fifo dp ip_stratixiv_ram ip_arria10_ram tech_memory
-
hdl_lib_technology = ip_stratixiv
synth_files =
@@ -45,3 +44,10 @@ synth_files =
src/vhdl/ipcore.vhd
test_bench_files =
+
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+
diff --git a/applications/compaan/libraries/vhdl_altera/compaandesign_com/common/altera/hdllib.cfg b/applications/compaan/libraries/vhdl_altera/compaandesign_com/common/altera/hdllib.cfg
index 42fe0e0764cc98cf28e4e7092396789f8a613d29..7415be80bd55d5b8b9c29d07eefdf170e5fb6e15 100644
--- a/applications/compaan/libraries/vhdl_altera/compaandesign_com/common/altera/hdllib.cfg
+++ b/applications/compaan/libraries/vhdl_altera/compaandesign_com/common/altera/hdllib.cfg
@@ -3,13 +3,15 @@ hdl_library_clause_name = compaandesign_com_common_altera_1_lib
hdl_lib_uses_synth = common dp
hdl_lib_technology = ip_stratixiv
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
-
-# Specify here all the files you want to be included in the library.
synth_files =
src/vhdl/fsl_v20.vhd
test_bench_files =
+
+[modelsim_project_file]
modelsim_copy_files =
+
+
+[quartus_project_file]
+
diff --git a/applications/compaan/libraries/vhdl_altera/compaandesign_com/common/common/hdllib.cfg b/applications/compaan/libraries/vhdl_altera/compaandesign_com/common/common/hdllib.cfg
index f2be4df5fd77c6368f30c19e360bbf75532c9998..9fccfe0bb8bdb4853d77ee21e97bd6585e6d6007 100644
--- a/applications/compaan/libraries/vhdl_altera/compaandesign_com/common/common/hdllib.cfg
+++ b/applications/compaan/libraries/vhdl_altera/compaandesign_com/common/common/hdllib.cfg
@@ -3,13 +3,15 @@ hdl_library_clause_name = compaandesign_com_common_common_1_lib
hdl_lib_uses_synth =
hdl_lib_technology = ip_stratixiv
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
-
-# Specify here all the files you want to be included in the library.
synth_files =
src/vhdl/hw_node_pkg.vhd
test_bench_files =
+
+[modelsim_project_file]
modelsim_copy_files =
+
+
+[quartus_project_file]
+
diff --git a/applications/compaan/libraries/vhdl_altera/compaandesign_com/common/const_connector/hdllib.cfg b/applications/compaan/libraries/vhdl_altera/compaandesign_com/common/const_connector/hdllib.cfg
index b0677c9a95e5cee494314c618b795e0d4713fa01..cebacc969f3b0c6628cb050d3f22150ec6cece41 100644
--- a/applications/compaan/libraries/vhdl_altera/compaandesign_com/common/const_connector/hdllib.cfg
+++ b/applications/compaan/libraries/vhdl_altera/compaandesign_com/common/const_connector/hdllib.cfg
@@ -3,13 +3,15 @@ hdl_library_clause_name = compaandesign_com_common_const_connector_1_lib
hdl_lib_uses_synth =
hdl_lib_technology = ip_stratixiv
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
-
-# Specify here all the files you want to be included in the library.
synth_files =
src/vhdl/const_connector.vhd
test_bench_files =
+
+[modelsim_project_file]
modelsim_copy_files =
+
+
+[quartus_project_file]
+
diff --git a/applications/compaan/libraries/vhdl_altera/compaandesign_com/common/extern_connector/hdllib.cfg b/applications/compaan/libraries/vhdl_altera/compaandesign_com/common/extern_connector/hdllib.cfg
index 1e07fc0d1a6bf57592bac686707bc1d193e92e9a..59dd1b4a278f2cc0b68d4eed1f447e5ac0882ce1 100644
--- a/applications/compaan/libraries/vhdl_altera/compaandesign_com/common/extern_connector/hdllib.cfg
+++ b/applications/compaan/libraries/vhdl_altera/compaandesign_com/common/extern_connector/hdllib.cfg
@@ -3,13 +3,15 @@ hdl_library_clause_name = compaandesign_com_common_extern_connector_1_lib
hdl_lib_uses_synth =
hdl_lib_technology = ip_stratixiv
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
-
-# Specify here all the files you want to be included in the library.
synth_files =
src/vhdl/extern_connector.vhd
test_bench_files =
+
+[modelsim_project_file]
modelsim_copy_files =
+
+
+[quartus_project_file]
+
diff --git a/applications/compaan/libraries/vhdl_altera/compaandesign_com/common/fifo/hdllib.cfg b/applications/compaan/libraries/vhdl_altera/compaandesign_com/common/fifo/hdllib.cfg
index b72c7f121fb7b58492eca41fb1091c79a40c0d7e..77021e60bc6416d31c034ca1f0173a3dda2c91ef 100644
--- a/applications/compaan/libraries/vhdl_altera/compaandesign_com/common/fifo/hdllib.cfg
+++ b/applications/compaan/libraries/vhdl_altera/compaandesign_com/common/fifo/hdllib.cfg
@@ -3,10 +3,6 @@ hdl_library_clause_name = compaandesign_com_common_fifo_1_lib
hdl_lib_uses_synth = compaandesign_com_common_altera_1
hdl_lib_technology = ip_stratixiv
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
-
-# Specify here all the files you want to be included in the library.
synth_files =
src/vhdl/async_fifo_bram.vhd
src/vhdl/async_fifo.vhd
@@ -18,4 +14,10 @@ synth_files =
test_bench_files =
+
+[modelsim_project_file]
modelsim_copy_files =
+
+
+[quartus_project_file]
+
diff --git a/applications/compaan/libraries/vhdl_altera/compaandesign_com/common/hwnode/hdllib.cfg b/applications/compaan/libraries/vhdl_altera/compaandesign_com/common/hwnode/hdllib.cfg
index a8a07f827b996c97b23beed8e495647f4a33e9f1..49dc9893c3c47c28669aafba377db4207fce21d7 100644
--- a/applications/compaan/libraries/vhdl_altera/compaandesign_com/common/hwnode/hdllib.cfg
+++ b/applications/compaan/libraries/vhdl_altera/compaandesign_com/common/hwnode/hdllib.cfg
@@ -3,10 +3,6 @@ hdl_library_clause_name = compaandesign_com_common_hwnode_1_lib
hdl_lib_uses_synth = compaandesign_com_common_common_1 compaandesign_com_common_altera_1
hdl_lib_technology = ip_stratixiv
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
-
-# Specify here all the files you want to be included in the library.
synth_files =
src/vhdl/controller.vhd
src/vhdl/counter.vhd
@@ -19,4 +15,10 @@ synth_files =
test_bench_files =
+
+[modelsim_project_file]
modelsim_copy_files =
+
+
+[quartus_project_file]
+
diff --git a/applications/compaan/libraries/vhdl_altera/compaandesign_com/common/wire_connector/hdllib.cfg b/applications/compaan/libraries/vhdl_altera/compaandesign_com/common/wire_connector/hdllib.cfg
index 72183708144acbf3d30442c17e34c79b3325f917..c93ece68d93014c9049617fdd6df06117dab13e3 100644
--- a/applications/compaan/libraries/vhdl_altera/compaandesign_com/common/wire_connector/hdllib.cfg
+++ b/applications/compaan/libraries/vhdl_altera/compaandesign_com/common/wire_connector/hdllib.cfg
@@ -3,13 +3,15 @@ hdl_library_clause_name = compaandesign_com_common_wire_connector_1_lib
hdl_lib_uses_synth =
hdl_lib_technology = ip_stratixiv
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
-
-# Specify here all the files you want to be included in the library.
synth_files =
src/vhdl/wire_connector.vhd
test_bench_files =
+
+[modelsim_project_file]
modelsim_copy_files =
+
+
+[quartus_project_file]
+
diff --git a/applications/compaan/libraries/vhdl_altera/compaandesign_com/ipcore2rtl/functions/hdllib.cfg b/applications/compaan/libraries/vhdl_altera/compaandesign_com/ipcore2rtl/functions/hdllib.cfg
index 5c0ba00ff11df137556f02545a380fa58ea8a01f..325e06a33f23f111e1b65813e1cf26b03045508c 100644
--- a/applications/compaan/libraries/vhdl_altera/compaandesign_com/ipcore2rtl/functions/hdllib.cfg
+++ b/applications/compaan/libraries/vhdl_altera/compaandesign_com/ipcore2rtl/functions/hdllib.cfg
@@ -3,10 +3,6 @@ hdl_library_clause_name = compaandesign_com_ipcore2rtl_functions_1_lib
hdl_lib_uses_synth = compaandesign_com_common_hwnode_1 compaandesign_com_common_common_1
hdl_lib_technology = ip_stratixiv
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
-
-# Specify here all the files you want to be included in the library.
synth_files =
src/vhdl/compaan_outlinedproc0.vhd
src/vhdl/compaan_outlinedproc0_pipeline.vhd
@@ -17,4 +13,9 @@ synth_files =
test_bench_files =
+
+[modelsim_project_file]
modelsim_copy_files =
+
+
+[quartus_project_file]
diff --git a/applications/compaan/libraries/vhdl_altera/compaandesign_com/ipcore2rtl/hwn_nd_1/hdllib.cfg b/applications/compaan/libraries/vhdl_altera/compaandesign_com/ipcore2rtl/hwn_nd_1/hdllib.cfg
index bc7ff43915c03efe0a505df9ed4aa892b63d288b..e4a030a3246b42a5a793838abc8cca7f66576e1d 100644
--- a/applications/compaan/libraries/vhdl_altera/compaandesign_com/ipcore2rtl/hwn_nd_1/hdllib.cfg
+++ b/applications/compaan/libraries/vhdl_altera/compaandesign_com/ipcore2rtl/hwn_nd_1/hdllib.cfg
@@ -3,10 +3,6 @@ hdl_library_clause_name = compaandesign_com_ipcore2rtl_hwn_nd_1_1_lib
hdl_lib_uses_synth = compaandesign_com_ipcore2rtl_functions_1 compaandesign_com_common_hwnode_1 compaandesign_com_common_common_1
hdl_lib_technology = ip_stratixiv
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
-
-# Specify here all the files you want to be included in the library.
synth_files =
src/vhdl/ipcore2rtl_hwn_nd_1_execution_unit.vhd
src/vhdl/ipcore2rtl_hwn_nd_1_eval_logic_rd.vhd
@@ -15,4 +11,10 @@ synth_files =
test_bench_files =
+
+[modelsim_project_file]
modelsim_copy_files =
+
+
+[quartus_project_file]
+
diff --git a/applications/compaan/libraries/vhdl_altera/compaandesign_com/ipcore2rtl/hwn_nd_2/hdllib.cfg b/applications/compaan/libraries/vhdl_altera/compaandesign_com/ipcore2rtl/hwn_nd_2/hdllib.cfg
index fbc97274bd14bbd46864a1d324270dbb01543302..7dcabc08d6e0f94cbd53b45068497ec3ce494b71 100644
--- a/applications/compaan/libraries/vhdl_altera/compaandesign_com/ipcore2rtl/hwn_nd_2/hdllib.cfg
+++ b/applications/compaan/libraries/vhdl_altera/compaandesign_com/ipcore2rtl/hwn_nd_2/hdllib.cfg
@@ -3,10 +3,6 @@ hdl_library_clause_name = compaandesign_com_ipcore2rtl_hwn_nd_2_1_lib
hdl_lib_uses_synth = compaandesign_com_ipcore2rtl_functions_1 compaandesign_com_common_hwnode_1 compaandesign_com_common_common_1
hdl_lib_technology = ip_stratixiv
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
-
-# Specify here all the files you want to be included in the library.
synth_files =
src/vhdl/ipcore2rtl_hwn_nd_2_execution_unit.vhd
src/vhdl/ipcore2rtl_hwn_nd_2_eval_logic_rd.vhd
@@ -15,4 +11,10 @@ synth_files =
test_bench_files =
+
+[modelsim_project_file]
modelsim_copy_files =
+
+
+[quartus_project_file]
+
diff --git a/applications/compaan/libraries/vhdl_altera/compaandesign_com/ipcore2rtl/hwn_nd_3/hdllib.cfg b/applications/compaan/libraries/vhdl_altera/compaandesign_com/ipcore2rtl/hwn_nd_3/hdllib.cfg
index abe75a4174e343eee1cb5f210dbab33446e96ae4..5b1cdc40eee6dfde5ed405a7eba1cc0dd46e6448 100644
--- a/applications/compaan/libraries/vhdl_altera/compaandesign_com/ipcore2rtl/hwn_nd_3/hdllib.cfg
+++ b/applications/compaan/libraries/vhdl_altera/compaandesign_com/ipcore2rtl/hwn_nd_3/hdllib.cfg
@@ -3,10 +3,6 @@ hdl_library_clause_name = compaandesign_com_ipcore2rtl_hwn_nd_3_1_lib
hdl_lib_uses_synth = compaandesign_com_ipcore2rtl_functions_1 compaandesign_com_common_hwnode_1 compaandesign_com_common_common_1
hdl_lib_technology = ip_stratixiv
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
-
-# Specify here all the files you want to be included in the library.
synth_files =
src/vhdl/ipcore2rtl_hwn_nd_3_execution_unit.vhd
src/vhdl/ipcore2rtl_hwn_nd_3_eval_logic_rd.vhd
@@ -15,4 +11,10 @@ synth_files =
test_bench_files =
+
+[modelsim_project_file]
modelsim_copy_files =
+
+
+[quartus_project_file]
+
diff --git a/applications/compaan/libraries/vhdl_altera/compaandesign_com/ipcore2rtl/register_rf/hdllib.cfg b/applications/compaan/libraries/vhdl_altera/compaandesign_com/ipcore2rtl/register_rf/hdllib.cfg
index 921a0a4da0357d634a0acd3d0886d9a9b045788d..57709345403db928cc8f58d7572cba1fc1907f5c 100644
--- a/applications/compaan/libraries/vhdl_altera/compaandesign_com/ipcore2rtl/register_rf/hdllib.cfg
+++ b/applications/compaan/libraries/vhdl_altera/compaandesign_com/ipcore2rtl/register_rf/hdllib.cfg
@@ -3,13 +3,15 @@ hdl_library_clause_name = compaandesign_com_ipcore2rtl_register_rf_1_lib
hdl_lib_uses_synth =
hdl_lib_technology = ip_stratixiv
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
-
-# Specify here all the files you want to be included in the library.
synth_files =
src/vhdl/register_rf.vhd
test_bench_files =
+
+[modelsim_project_file]
modelsim_copy_files =
+
+
+[quartus_project_file]
+
diff --git a/applications/compaan/libraries/vhdl_altera/hdllib.cfg b/applications/compaan/libraries/vhdl_altera/hdllib.cfg
index af71b8418a27e09016c6c333ccad42319ef00543..1d1d8e9da832d65b5a71d98032c55ff7d0bb2d59 100644
--- a/applications/compaan/libraries/vhdl_altera/hdllib.cfg
+++ b/applications/compaan/libraries/vhdl_altera/hdllib.cfg
@@ -1,13 +1,8 @@
hdl_lib_name = ipcore
hdl_library_clause_name = ipcore_lib
-
hdl_lib_uses_synth = compaandesign_com_ipcore2rtl_hwn_nd_3_1 compaandesign_com_ipcore2rtl_hwn_nd_1_1 compaandesign_com_ipcore2rtl_register_rf_1 compaandesign_com_ipcore2rtl_hwn_nd_2_1 compaandesign_com_common_altera_1
hdl_lib_technology = ip_stratixiv
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
-
-# Specify here all the files you want to be included in the library.
synth_files =
src/vhdl/ipcore.vhd
src/vhdl/ipcore2rtl_ed_1_ip_wrapper.vhd
@@ -19,3 +14,10 @@ synth_files =
test_bench_files =
src/vhdl/system_ext_TB.vhd
+
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+
diff --git a/applications/dig_receiver/designs/dig_receiver_bn/hdllib.cfg b/applications/dig_receiver/designs/dig_receiver_bn/hdllib.cfg
index 21b93ffb786cb2bcdf27f015bef51e9d56a498c5..0f10892983343a21b684c3c4d7dd3684a9dd919a 100644
--- a/applications/dig_receiver/designs/dig_receiver_bn/hdllib.cfg
+++ b/applications/dig_receiver/designs/dig_receiver_bn/hdllib.cfg
@@ -2,16 +2,8 @@ hdl_lib_name = dig_receiver_bn
hdl_library_clause_name = dig_receiver_bn_lib
hdl_lib_uses_synth = common mm dp unb1_board diag digital_receiver dr_mesh test_generator
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_stratixiv
-synth_top_level_entity = dig_receiver_bn
-
-quartus_copy_files =
- $RADIOHDL/applications/dig_receiver/designs/dig_receiver_bn/quartus/sopc_dig_receiver_bn.sopc .
-
-modelsim_copy_files =
-
synth_files =
$HDL_BUILD_DIR/unb1/quartus/dig_receiver_bn/sopc_dig_receiver_bn.vhd
$RADIOHDL/applications/dig_receiver/designs/dig_receiver_bn/src/vhdl/adc_lvds.vhd
@@ -21,6 +13,17 @@ synth_files =
test_bench_files =
+
+[modelsim_project_file]
+modelsim_copy_files =
+
+
+[quartus_project_file]
+synth_top_level_entity = dig_receiver_bn
+
+quartus_copy_files =
+ $RADIOHDL/applications/dig_receiver/designs/dig_receiver_bn/quartus/sopc_dig_receiver_bn.sopc .
+
quartus_qsf_files =
$RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
diff --git a/applications/dig_receiver/designs/dig_receiver_fn/hdllib.cfg b/applications/dig_receiver/designs/dig_receiver_fn/hdllib.cfg
index 9a2dece9f4eedaa7d3af7c368951b0231763ab5e..9d3d978741ce1918c7fb7ebb815908556f5f49c7 100644
--- a/applications/dig_receiver/designs/dig_receiver_fn/hdllib.cfg
+++ b/applications/dig_receiver/designs/dig_receiver_fn/hdllib.cfg
@@ -2,16 +2,8 @@ hdl_lib_name = dig_receiver_fn
hdl_library_clause_name = dig_receiver_fn_lib
hdl_lib_uses_synth = common mm dp unb1_board diag digital_receiver dr_mesh tr_10GbE dr_udp_packetizer
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_stratixiv
-synth_top_level_entity = dig_receiver_fn
-
-quartus_copy_files =
- $RADIOHDL/applications/dig_receiver/designs/dig_receiver_fn/quartus/sopc_dig_receiver_fn.sopc .
-
-modelsim_copy_files =
-
synth_files =
$HDL_BUILD_DIR/unb1/quartus/dig_receiver_fn/sopc_dig_receiver_fn.vhd
$RADIOHDL/applications/dig_receiver/designs/dig_receiver_fn/src/vhdl/dig_receiver_mm.vhd
@@ -20,6 +12,17 @@ synth_files =
test_bench_files =
+
+[modelsim_project_file]
+modelsim_copy_files =
+
+
+[quartus_project_file]
+synth_top_level_entity = dig_receiver_fn
+
+quartus_copy_files =
+ $RADIOHDL/applications/dig_receiver/designs/dig_receiver_fn/quartus/sopc_dig_receiver_fn.sopc .
+
quartus_qsf_files =
$RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
diff --git a/applications/dig_receiver/libraries/common_OA/hdllib.cfg b/applications/dig_receiver/libraries/common_OA/hdllib.cfg
index 5121fe88afd9cf591571294f53ce6f174bafc906..77e6522acd013ac54cc4b957fcecedae4cc08931 100644
--- a/applications/dig_receiver/libraries/common_OA/hdllib.cfg
+++ b/applications/dig_receiver/libraries/common_OA/hdllib.cfg
@@ -2,12 +2,8 @@ hdl_lib_name = common_OA
hdl_library_clause_name = common_OA_lib
hdl_lib_uses_synth = technology common
hdl_lib_uses_sim =
-
hdl_lib_technology =
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
-
synth_files =
$SVN/Digital_Receiver/trunk/Firmware/modules_HDL/common_OA/src/vhdl/common_ram_wsrs.vhd
$SVN/Digital_Receiver/trunk/Firmware/modules_HDL/common_OA/src/vhdl/common_pulse_delay.vhd
@@ -24,3 +20,9 @@ synth_files =
test_bench_files =
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+
diff --git a/applications/dig_receiver/libraries/dbbc/hdllib.cfg b/applications/dig_receiver/libraries/dbbc/hdllib.cfg
index f609d66d89e0582b73554f3fba9dca2a71e91448..5415750a0ff3d0b37cbece971ee7004f203e13e0 100644
--- a/applications/dig_receiver/libraries/dbbc/hdllib.cfg
+++ b/applications/dig_receiver/libraries/dbbc/hdllib.cfg
@@ -2,11 +2,8 @@ hdl_lib_name = dbbc
hdl_library_clause_name = dbbc_lib
hdl_lib_uses_synth = common mm dp common_OA
hdl_lib_uses_sim =
-
hdl_lib_technology =
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
synth_files =
$SVN/Digital_Receiver/trunk/Firmware/modules_HDL/dbbc/src/vhdl/dBBC_pkg.vhd
@@ -25,3 +22,9 @@ synth_files =
test_bench_files =
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+
diff --git a/applications/dig_receiver/libraries/digital_receiver/hdllib.cfg b/applications/dig_receiver/libraries/digital_receiver/hdllib.cfg
index ff870d0d484e22c9d4deb2c703e3db2b9a3c9dbe..8c4c60e7334d673780c93b81a5086aba3b6b3c59 100644
--- a/applications/dig_receiver/libraries/digital_receiver/hdllib.cfg
+++ b/applications/dig_receiver/libraries/digital_receiver/hdllib.cfg
@@ -2,12 +2,8 @@ hdl_lib_name = digital_receiver
hdl_library_clause_name = digital_receiver_lib
hdl_lib_uses_synth = common mm dp common_OA dbbc fft_module_n vdif_formatter
hdl_lib_uses_sim =
-
hdl_lib_technology =
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
-
synth_files =
$SVN/Digital_Receiver/trunk/Firmware/modules_HDL/DigitalReceiver/src/vhdl/digrec_pkg.vhd
$SVN/Digital_Receiver/trunk/Firmware/modules_HDL/DigitalReceiver/src/vhdl/realign_data.vhd
@@ -44,3 +40,10 @@ synth_files =
test_bench_files =
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+
+
diff --git a/applications/dig_receiver/libraries/dr_mesh/hdllib.cfg b/applications/dig_receiver/libraries/dr_mesh/hdllib.cfg
index 0fe39f460f26eb7e8f1b4f87ccf209ade5d55049..975bf15e87c2143e3bb34a58d6e01673390f2039 100644
--- a/applications/dig_receiver/libraries/dr_mesh/hdllib.cfg
+++ b/applications/dig_receiver/libraries/dr_mesh/hdllib.cfg
@@ -2,12 +2,8 @@ hdl_lib_name = dr_mesh
hdl_library_clause_name = dr_mesh_lib
hdl_lib_uses_synth = common mm dp diag tr_nonbonded
hdl_lib_uses_sim =
-
hdl_lib_technology =
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
-
synth_files =
$SVN/Digital_Receiver/trunk/Firmware/modules_HDL/dr_mesh/src/vhdl/mesh_pkg.vhd
$SVN/Digital_Receiver/trunk/Firmware/modules_HDL/dr_mesh/src/vhdl/mesh_resample_47.vhd
@@ -27,3 +23,9 @@ synth_files =
test_bench_files =
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+
diff --git a/applications/dig_receiver/libraries/fft_module_n/hdllib.cfg b/applications/dig_receiver/libraries/fft_module_n/hdllib.cfg
index 7a3f5e139619ae91dbe49fb91710541ec5643b50..8f04b48ea708e8e99afee0911485c4616f45d1fd 100644
--- a/applications/dig_receiver/libraries/fft_module_n/hdllib.cfg
+++ b/applications/dig_receiver/libraries/fft_module_n/hdllib.cfg
@@ -2,12 +2,8 @@ hdl_lib_name = fft_module_n
hdl_library_clause_name = fft_module_n_lib
hdl_lib_uses_synth = technology common common_OA
hdl_lib_uses_sim =
-
hdl_lib_technology =
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
-
synth_files =
$SVN/Digital_Receiver/trunk/Firmware/modules_HDL/fft/src/vhdl/fft_pkg.vhd
$SVN/Digital_Receiver/trunk/Firmware/modules_HDL/fft/src/vhdl/multadd.vhd
@@ -50,3 +46,9 @@ test_bench_files =
$SVN/Digital_Receiver/trunk/Firmware/modules_HDL/fft/src/vhdl/sims/tb_fftmod4_dav.vhd
$SVN/Digital_Receiver/trunk/Firmware/modules_HDL/fft/src/vhdl/sims/tb_real_fft.vhd
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+
diff --git a/applications/dig_receiver/libraries/polyfilt/hdllib.cfg b/applications/dig_receiver/libraries/polyfilt/hdllib.cfg
index 6cf92e38c3ec147135e75d3f78842a7ead59afab..17d3b4a2d94bcb38d4c834f401f7db4ef39c8722 100644
--- a/applications/dig_receiver/libraries/polyfilt/hdllib.cfg
+++ b/applications/dig_receiver/libraries/polyfilt/hdllib.cfg
@@ -2,12 +2,8 @@ hdl_lib_name = polyfilt
hdl_library_clause_name = polyfilt_lib
hdl_lib_uses_synth = technology common common_OA fft_module_n
hdl_lib_uses_sim =
-
hdl_lib_technology =
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
-
synth_files =
$SVN/Digital_Receiver/trunk/Firmware/modules_HDL/polyfilt/src/vhdl/channelizer_pfb_4.vhd
$SVN/Digital_Receiver/trunk/Firmware/modules_HDL/polyfilt/src/vhdl/poly_filter_main.vhd
@@ -25,3 +21,9 @@ synth_files =
test_bench_files =
$SVN/Digital_Receiver/trunk/Firmware/modules_HDL/polyfilt/src/vhdl/poly_filt_tb.vhd
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+
diff --git a/applications/dig_receiver/libraries/test_generator/hdllib.cfg b/applications/dig_receiver/libraries/test_generator/hdllib.cfg
index ea9fd7c0620c1a6e956beb98305da422a4acd650..913d052d6dca92f2f395aaa7628b9851e66bcf17 100644
--- a/applications/dig_receiver/libraries/test_generator/hdllib.cfg
+++ b/applications/dig_receiver/libraries/test_generator/hdllib.cfg
@@ -2,12 +2,8 @@ hdl_lib_name = test_generator
hdl_library_clause_name = test_generator_lib
hdl_lib_uses_synth = common mm dp diag axi4
hdl_lib_uses_sim =
-
hdl_lib_technology =
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
-
synth_files =
$SVN/Digital_Receiver/trunk/Firmware/modules_HDL/test_generator/src/vhdl/cal_pulse.vhd
$SVN/Digital_Receiver/trunk/Firmware/modules_HDL/test_generator/src/vhdl/xorshift_RNG.vhd
@@ -20,3 +16,11 @@ synth_files =
test_bench_files =
$SVN/Digital_Receiver/trunk/Firmware/modules_HDL/test_generator/src/vhdl/tb_test_generator.vhd
+
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+
+
diff --git a/applications/dig_receiver/libraries/udp_packetizer/hdllib.cfg b/applications/dig_receiver/libraries/udp_packetizer/hdllib.cfg
index 92fb3ae730c31629f82e5760a00a4d8d2d4b84a0..6918d4a1953fd6ba6d027a14cea3b4f7ade51a4f 100644
--- a/applications/dig_receiver/libraries/udp_packetizer/hdllib.cfg
+++ b/applications/dig_receiver/libraries/udp_packetizer/hdllib.cfg
@@ -2,12 +2,8 @@ hdl_lib_name = dr_udp_packetizer
hdl_library_clause_name = dr_udp_packetizer_lib
hdl_lib_uses_synth = common mm dp technology_lib tr_10GbE_lib tech_mac_10g tech_eth_10g tr_xaui
hdl_lib_uses_sim =
-
hdl_lib_technology =
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
-
synth_files =
$SVN/Digital_Receiver/trunk/Firmware/modules_HDL/udp_packetizer/src/vhdl/udp_packetizer_pkg.vhd
$SVN/Digital_Receiver/trunk/Firmware/modules_HDL/udp_packetizer/src/vhdl/udp_packetizer_st.vhd
@@ -16,3 +12,9 @@ synth_files =
test_bench_files =
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+
diff --git a/applications/dig_receiver/libraries/vdif_formatter/hdllib.cfg b/applications/dig_receiver/libraries/vdif_formatter/hdllib.cfg
index 53af6f3871de4c42dd53f85d34841eaa831019c2..be0a31eb1e04e61f5a83b648bc33841bc155cdab 100644
--- a/applications/dig_receiver/libraries/vdif_formatter/hdllib.cfg
+++ b/applications/dig_receiver/libraries/vdif_formatter/hdllib.cfg
@@ -2,12 +2,8 @@ hdl_lib_name = vdif_formatter
hdl_library_clause_name = vdif_formatter_lib
hdl_lib_uses_synth = common mm dp common_OA
hdl_lib_uses_sim =
-
hdl_lib_technology =
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
-
synth_files =
$SVN/Digital_Receiver/trunk/Firmware/modules_HDL/formatter/src/vhdl/format_header.vhd
$SVN/Digital_Receiver/trunk/Firmware/modules_HDL/formatter/src/vhdl/formatter.vhd
@@ -19,3 +15,9 @@ synth_files =
test_bench_files =
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+
diff --git a/applications/rfidb/designs/rfidb/hdllib.cfg b/applications/rfidb/designs/rfidb/hdllib.cfg
index f84012fe01746dc4bce3ea37c8efc72f466c3bd0..6c2dd63869b3c741a646b79912b8bebde296e575 100644
--- a/applications/rfidb/designs/rfidb/hdllib.cfg
+++ b/applications/rfidb/designs/rfidb/hdllib.cfg
@@ -2,20 +2,8 @@ hdl_lib_name = unb1_rfidb
hdl_library_clause_name = unb1_rfidb_lib
hdl_lib_uses_synth = common dp unb1_board diag eth detector tech_tse
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_stratixiv
-synth_top_level_entity =
-
-quartus_copy_files =
- quartus/qsys_unb1_rfidb.qsys .
- $RADIOHDL/libraries/base/dp/designs/unb1_dp_offload/src/hex hex
-
-modelsim_copy_files =
- $RADIOHDL/libraries/base/dp/designs/unb1_dp_offload/src/hex hex
- tb/data data
- modelsim .
-
synth_files =
src/vhdl/rfidb_constants_pkg.vhd
src/vhdl/qsys_unb1_rfidb_pkg.vhd
@@ -25,6 +13,21 @@ synth_files =
test_bench_files =
tb/vhdl/tb_unb1_rfidb.vhd
+
+[modelsim_project_file]
+modelsim_copy_files =
+ $RADIOHDL/libraries/base/dp/designs/unb1_dp_offload/src/hex hex
+ tb/data data
+ modelsim .
+
+
+[quartus_project_file]
+synth_top_level_entity =
+
+quartus_copy_files =
+ quartus/qsys_unb1_rfidb.qsys .
+ $RADIOHDL/libraries/base/dp/designs/unb1_dp_offload/src/hex hex
+
quartus_qsf_files =
$RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
diff --git a/applications/rfidb/librairies/detector/hdllib.cfg b/applications/rfidb/librairies/detector/hdllib.cfg
index 308f73de608c97b05e743385b1997d818f3a4734..063eedd992bb8454199323f469c429b0abe5bef4 100644
--- a/applications/rfidb/librairies/detector/hdllib.cfg
+++ b/applications/rfidb/librairies/detector/hdllib.cfg
@@ -1,7 +1,6 @@
hdl_lib_name = detector
hdl_library_clause_name = detector_lib
hdl_lib_uses_synth = common technology mm ip_arria10_fifo ip_stratixiv_fifo tech_fifo dp ip_stratixiv_ram ip_arria10_ram tech_memory
-
hdl_lib_technology =
synth_files =
@@ -14,7 +13,6 @@ synth_files =
src/vhdl/detector.vhd
src/vhdl/write_rfi_db.vhd
-
test_bench_files =
tb/vhdl/tb_universal_shift_reg.vhd
tb/vhdl/tb_robust_mean.vhd
@@ -23,5 +21,10 @@ test_bench_files =
tb/vhdl/tb_detector.vhd
tb/vhdl/tb_write_rfi_db.vhd
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
quartus_qip_files =
$RADIOHDL/applications/rfidb/designs/rfidb/quartus/alt_probe.qip
diff --git a/applications/stagiair/designs/stagiair_unb1_wave_gen/hdllib.cfg b/applications/stagiair/designs/stagiair_unb1_wave_gen/hdllib.cfg
index b55ed95039fa363d02e8c9b25e01f7d3740bd59a..4dda433d6c6d48b4e3a9925debba0780832b28cd 100644
--- a/applications/stagiair/designs/stagiair_unb1_wave_gen/hdllib.cfg
+++ b/applications/stagiair/designs/stagiair_unb1_wave_gen/hdllib.cfg
@@ -2,7 +2,6 @@ hdl_lib_name = stagiair_unb1_wave_gen
hdl_library_clause_name = stagiair_unb1_wave_gen_lib
hdl_lib_uses_synth = common mm unb1_board wave_gen
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_stratixiv
synth_files =
@@ -14,6 +13,11 @@ synth_files =
test_bench_files =
tb/vhdl/tb_stagiair_unb1_wave_gen.vhd
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
synth_top_level_entity =
quartus_copy_files =
diff --git a/applications/stagiair/libraries/wave_gen/hdllib.cfg b/applications/stagiair/libraries/wave_gen/hdllib.cfg
index b5891f574ef5316b700eefcd66837c9e36724785..14cd0615128ee800df440c944de6a284ebdfcb90 100644
--- a/applications/stagiair/libraries/wave_gen/hdllib.cfg
+++ b/applications/stagiair/libraries/wave_gen/hdllib.cfg
@@ -2,7 +2,6 @@ hdl_lib_name = wave_gen
hdl_library_clause_name = wave_gen_lib
hdl_lib_uses_synth = common_mult common dp mm diag
hdl_lib_uses_sim =
-
hdl_lib_technology =
synth_files =
@@ -14,3 +13,8 @@ test_bench_files =
tb/vhdl/tb_sine_gen.vhd
tb/vhdl/tb_wave_gen.vhd
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
diff --git a/boards/uniboard1/designs/unb1_bn_capture/hdllib.cfg b/boards/uniboard1/designs/unb1_bn_capture/hdllib.cfg
index 007320343ed543aeee89155757970dedbb40928f..b6e76a12701cc4c151ad88069b535b236a2d0628 100644
--- a/boards/uniboard1/designs/unb1_bn_capture/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_bn_capture/hdllib.cfg
@@ -3,11 +3,6 @@ hdl_library_clause_name = unb1_bn_capture_lib
hdl_lib_uses_synth = common unb1_board dp eth tech_tse diag aduh
hdl_lib_technology = ip_stratixiv
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
-
-synth_top_level_entity =
-
synth_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_bn_capture/sopc_unb1_bn_capture.vhd
src/vhdl/unb1_bn_capture_pkg.vhd
@@ -19,13 +14,19 @@ test_bench_files =
tb/vhdl/tb_unb1_bn_capture.vhd
tb/vhdl/tb_node_unb1_bn_capture.vhd
-quartus_copy_files = quartus/sopc_unb1_bn_capture.sopc .
- $RADIOHDL/libraries/io/i2c/tb/data data
- $RADIOHDL/libraries/base/diag/src/data data
+[modelsim_project_file]
modelsim_copy_files = $RADIOHDL/libraries/io/i2c/tb/data data
$RADIOHDL/libraries/base/diag/src/data data
+
+[quartus_project_file]
+synth_top_level_entity =
+
+quartus_copy_files = quartus/sopc_unb1_bn_capture.sopc .
+ $RADIOHDL/libraries/io/i2c/tb/data data
+ $RADIOHDL/libraries/base/diag/src/data data
+
quartus_qsf_files =
$RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
diff --git a/boards/uniboard1/designs/unb1_bn_terminal_bg/hdllib.cfg b/boards/uniboard1/designs/unb1_bn_terminal_bg/hdllib.cfg
index 81ccf6d574a4ab43e2c19c0b3c31ee43fe208766..327cfda99ab7d337308e07d095629bd4696a73e0 100644
--- a/boards/uniboard1/designs/unb1_bn_terminal_bg/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_bn_terminal_bg/hdllib.cfg
@@ -3,11 +3,6 @@ hdl_library_clause_name = unb1_bn_terminal_bg_lib
hdl_lib_uses_synth = common unb1_board dp eth tech_tse diag bf
hdl_lib_technology = ip_stratixiv
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
-
-synth_top_level_entity =
-
synth_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_bn_terminal_bg/sopc_unb1_bn_terminal_bg.vhd
src/vhdl/node_unb1_bn_terminal_bg.vhd
@@ -17,8 +12,14 @@ test_bench_files =
tb/vhdl/tb_node_unb1_bn_terminal_bg.vhd
tb/vhdl/tb_tb_node_unb1_bn_terminal_bg.vhd
+
+[modelsim_project_file]
modelsim_copy_files = $RADIOHDL/libraries/base/diag/src/data data
+
+[quartus_project_file]
+synth_top_level_entity =
+
quartus_copy_files = quartus/sopc_unb1_bn_terminal_bg.sopc .
$RADIOHDL/libraries/base/diag/src/data data
@@ -32,7 +33,3 @@ quartus_qip_files = $HDL_BUILD_DIR/unb1/quartus/unb1_bn_terminal_bg/sopc_unb1_bn
quartus_sdc_files =
$RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
-
-
-
-
diff --git a/boards/uniboard1/designs/unb1_ddr3/hdllib.cfg b/boards/uniboard1/designs/unb1_ddr3/hdllib.cfg
index 9d5067b941d8310d62b57b22a60098648ee9072f..5c7bc018d7b9c72a00c35cf3425bd4f271b248fe 100644
--- a/boards/uniboard1/designs/unb1_ddr3/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_ddr3/hdllib.cfg
@@ -16,9 +16,13 @@ synth_files =
test_bench_files =
tb/vhdl/tb_unb1_ddr3.vhd
+
+[modelsim_project_file]
modelsim_compile_ip_files =
$RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
+
+[quartus_project_file]
synth_top_level_entity =
quartus_copy_files =
diff --git a/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/hdllib.cfg b/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/hdllib.cfg
index 3f5a3a121c6ffb579997cc6aa5146342ab004b32..a788059ab4272716edf1f8bce56dfdb2c3fbe114 100644
--- a/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/hdllib.cfg
@@ -3,7 +3,6 @@ hdl_library_clause_name = unb1_ddr3_reorder_dual_rank_lib
hdl_lib_uses_synth = common technology mm i2c unb1_board dp eth tech_tse diag io_ddr reorder
hdl_lib_uses_sim =
hdl_lib_technology = ip_stratixiv
-
hdl_lib_excludes = ip_stratixiv_ddr3_uphy_4g_800_slave
ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave
ip_stratixiv_ddr3_uphy_4g_single_rank_800_master
@@ -20,15 +19,22 @@ test_bench_files =
../../tb/vhdl/tb_unb1_ddr3_reorder.vhd
tb_unb1_ddr3_reorder_dual_rank.vhd
+
+[modelsim_project_file]
+modelsim_copy_files =
+ ../../src/hex hex
+
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
+
+
+[quartus_project_file]
synth_top_level_entity =
quartus_copy_files =
../../quartus/sopc_unb1_ddr3_reorder.sopc .
../../src/hex hex
-modelsim_copy_files =
- ../../src/hex hex
-
quartus_qsf_files =
$RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
@@ -42,6 +48,3 @@ quartus_qip_files =
$RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master.qip
$RADIOHDL/build/unb1/quartus/unb1_ddr3_reorder_dual_rank/sopc_unb1_ddr3_reorder.qip
-modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
-
diff --git a/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_single_rank/hdllib.cfg b/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_single_rank/hdllib.cfg
index 4cd2921d16d73116b7816c3ef2f96fe07e641fce..ab76e6abc4b0772bae353b2895e5927e873f5622 100644
--- a/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_single_rank/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_single_rank/hdllib.cfg
@@ -19,15 +19,22 @@ test_bench_files =
../../tb/vhdl/tb_unb1_ddr3_reorder.vhd
tb_unb1_ddr3_reorder_single_rank.vhd
+
+[modelsim_project_file]
+modelsim_copy_files =
+ ../../src/hex hex
+
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
+
+
+[quartus_project_file]
synth_top_level_entity =
quartus_copy_files =
../../quartus/sopc_unb1_ddr3_reorder.sopc .
../../src/hex hex
-modelsim_copy_files =
- ../../src/hex hex
-
quartus_qsf_files =
$RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
@@ -41,6 +48,3 @@ quartus_qip_files =
$RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
$RADIOHDL/build/unb1/quartus/unb1_ddr3_reorder_single_rank/sopc_unb1_ddr3_reorder.qip
-modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
-
diff --git a/boards/uniboard1/designs/unb1_ddr3_transpose/hdllib.cfg b/boards/uniboard1/designs/unb1_ddr3_transpose/hdllib.cfg
index 75e963d7fd53af5e27477935f4cf6701608d2e43..3d329712469c43eeaf81adb6a9f96397a6e26e22 100644
--- a/boards/uniboard1/designs/unb1_ddr3_transpose/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_ddr3_transpose/hdllib.cfg
@@ -2,9 +2,8 @@ hdl_lib_name = unb1_ddr3_transpose
hdl_library_clause_name = unb1_ddr3_transpose_lib
hdl_lib_uses_synth = common mm i2c unb1_board dp eth diagnostics ddr3
hdl_lib_uses_sim =
-hdl_lib_excludes = ip_stratixiv_ddr3_uphy_4g_800_slave
-
hdl_lib_technology = ip_stratixiv
+hdl_lib_excludes = ip_stratixiv_ddr3_uphy_4g_800_slave
synth_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_ddr3_transpose/sopc_unb_ddr3_transpose.vhd
@@ -14,6 +13,13 @@ synth_files =
test_bench_files =
tb/vhdl/tb_unb1_ddr3_transpose.vhd
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
+
+
+[quartus_project_file]
synth_top_level_entity =
quartus_copy_files =
@@ -32,7 +38,3 @@ quartus_qip_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_ddr3_transpose/sopc_unb_ddr3_transpose.qip
$RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master.qip
-modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
-
-
diff --git a/boards/uniboard1/designs/unb1_fn_terminal_db/hdllib.cfg b/boards/uniboard1/designs/unb1_fn_terminal_db/hdllib.cfg
index 2addfe97825857bf2fc28bebb314c3b3d313aff7..fb01a093b4dbd40fb89d9e0697df7daa480788a0 100644
--- a/boards/uniboard1/designs/unb1_fn_terminal_db/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_fn_terminal_db/hdllib.cfg
@@ -3,8 +3,6 @@ hdl_library_clause_name = unb1_fn_terminal_db_lib
hdl_lib_uses_synth = common technology mm i2c unb1_board diag
hdl_lib_technology = ip_stratixiv
-synth_top_level_entity =
-
synth_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_fn_terminal_db/sopc_unb1_fn_terminal_db.vhd
src/vhdl/mmm_unb1_fn_terminal_db.vhd
@@ -13,8 +11,14 @@ synth_files =
test_bench_files =
tb/vhdl/tb_unb1_fn_terminal_db.vhd
+
+[modelsim_project_file]
#modelsim_copy_files = src/hex hex
+
+[quartus_project_file]
+synth_top_level_entity =
+
quartus_copy_files = quartus/sopc_unb1_fn_terminal_db.sopc .
quartus_qsf_files =
diff --git a/boards/uniboard1/designs/unb1_minimal/hdllib.cfg b/boards/uniboard1/designs/unb1_minimal/hdllib.cfg
index 503fcc021261d01a2bb8a703bfd9b5ebd9ea7f37..19bf76180a3ed0353fb6c00ce5ec6d1e0a7a1422 100644
--- a/boards/uniboard1/designs/unb1_minimal/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_minimal/hdllib.cfg
@@ -2,7 +2,6 @@ hdl_lib_name = unb1_minimal
hdl_library_clause_name = unb1_minimal_lib
hdl_lib_uses_synth = common mm unb1_board
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_stratixiv
synth_files =
@@ -14,3 +13,9 @@ synth_files =
test_bench_files =
tb/vhdl/tb_unb1_minimal.vhd
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_mm_arbiter/hdllib.cfg b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_mm_arbiter/hdllib.cfg
index 6bc51c9a80e1a91e3bde4fb523b295d02eac8d91..573fbd31dea7767c20f4375c1c4e4f7f70b68718 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_mm_arbiter/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_mm_arbiter/hdllib.cfg
@@ -2,7 +2,6 @@ hdl_lib_name = unb1_minimal_mm_arbiter
hdl_library_clause_name = unb1_minimal_mm_arbiter_lib
hdl_lib_uses_synth = unb1_board unb1_minimal
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_stratixiv
synth_files =
@@ -11,6 +10,11 @@ synth_files =
test_bench_files =
tb_unb1_minimal_mm_arbiter.vhd
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
synth_top_level_entity =
quartus_copy_files =
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/hdllib.cfg b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/hdllib.cfg
index 29572a52c1245fcb26e5c57b62d49d62f7ec9798..8ce77c6be85a1c99ba0d33d3583f20ad64433006 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/hdllib.cfg
@@ -2,7 +2,6 @@ hdl_lib_name = unb1_minimal_qsys
hdl_library_clause_name = unb1_minimal_qsys_lib
hdl_lib_uses_synth = unb1_board unb1_minimal
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_stratixiv
synth_files =
@@ -11,8 +10,10 @@ synth_files =
test_bench_files =
tb_unb1_minimal_qsys.vhd
+
[modelsim_project_file]
+
[quartus_project_file]
synth_top_level_entity =
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/hdllib.cfg b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/hdllib.cfg
index 2550cc33cc8e3d7d9a9578691b55e734d9861770..47ab642c8394e1eb706502d7f2c6863ccf585d51 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/hdllib.cfg
@@ -2,7 +2,6 @@ hdl_lib_name = unb1_minimal_qsys_wo_pll
hdl_library_clause_name = unb1_minimal_qsys_wo_pll_lib
hdl_lib_uses_synth = unb1_board common mm
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_stratixiv
synth_files =
@@ -13,6 +12,11 @@ synth_files =
test_bench_files =
tb_unb1_minimal_qsys_wo_pll.vhd
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
synth_top_level_entity =
quartus_copy_files =
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/hdllib.cfg b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/hdllib.cfg
index 70882470378190f22286c0fad26dd3788c94e4b3..b533e42f3610a06f7be124169a844cdb0b0d44f1 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/hdllib.cfg
@@ -2,7 +2,6 @@ hdl_lib_name = unb1_minimal_sopc
hdl_library_clause_name = unb1_minimal_sopc_lib
hdl_lib_uses_synth = unb1_board unb1_minimal
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_stratixiv
synth_files =
@@ -11,6 +10,11 @@ synth_files =
test_bench_files =
tb_unb1_minimal_sopc.vhd
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
synth_top_level_entity =
quartus_copy_files =
diff --git a/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/hdllib.cfg b/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/hdllib.cfg
index a1d0c7c506b24e1ad3e48b9551f868af4a31c280..f687fcbc733d138a4bc19915cb7a3377ae417679 100644
--- a/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/hdllib.cfg
@@ -3,8 +3,6 @@ hdl_library_clause_name = unb1_terminal_bg_mesh_db_lib
hdl_lib_uses_synth = common technology mm i2c unb1_board diag eth tech_tse
hdl_lib_technology = ip_stratixiv
-synth_top_level_entity =
-
synth_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_terminal_bg_mesh_db/qsys_unb1_terminal_bg_mesh_db/synthesis/qsys_unb1_terminal_bg_mesh_db.v
src/vhdl/mmm_unb1_terminal_bg_mesh_db.vhd
@@ -14,8 +12,14 @@ synth_files =
test_bench_files =
tb/vhdl/tb_unb1_terminal_bg_mesh_db.vhd
+
+[modelsim_project_file]
modelsim_copy_files = src/hex hex
+
+[quartus_project_file]
+synth_top_level_entity =
+
quartus_copy_files = quartus/qsys_unb1_terminal_bg_mesh_db.qsys .
src/hex hex
quartus_qsf_files =
diff --git a/boards/uniboard1/designs/unb1_test/hdllib.cfg b/boards/uniboard1/designs/unb1_test/hdllib.cfg
index e1997ac46d13b2d1ea8814734e0599498c9bfe9c..5fe53f6bc36cb5e72fe68fa79c3d2b23e4abff95 100644
--- a/boards/uniboard1/designs/unb1_test/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/hdllib.cfg
@@ -2,7 +2,6 @@ hdl_lib_name = unb1_test
hdl_library_clause_name = unb1_test_lib
hdl_lib_uses_synth = common technology mm unb1_board dp eth tech_tse tr_10GbE mdio diagnostics diag io_ddr tech_ddr
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_stratixiv
synth_files =
@@ -15,3 +14,9 @@ synth_files =
test_bench_files =
tb/vhdl/tb_unb1_test.vhd
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/hdllib.cfg
index 4f3efa6d0fbc2722973063fbf9d6fee95eb0eefd..114de1021230dceebb022d52ff69ec22ce67e89b 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/hdllib.cfg
@@ -2,9 +2,11 @@ hdl_lib_name = unb1_test_10GbE
hdl_library_clause_name = unb1_test_10GbE_lib
hdl_lib_uses_synth = unb1_board unb1_test
hdl_lib_uses_sim =
-hdl_lib_excludes = ip_stratixiv_ddr3_uphy_4g_800_master ip_stratixiv_ddr3_uphy_4g_800_slave ip_stratixiv_ddr3_uphy_4g_single_rank_800_master ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave
-
hdl_lib_technology = ip_stratixiv
+hdl_lib_excludes = ip_stratixiv_ddr3_uphy_4g_800_master
+ ip_stratixiv_ddr3_uphy_4g_800_slave
+ ip_stratixiv_ddr3_uphy_4g_single_rank_800_master
+ ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave
synth_files =
unb1_test_10GbE.vhd
@@ -12,9 +14,13 @@ synth_files =
test_bench_files =
tb_unb1_test_10GbE.vhd
+
+[modelsim_project_file]
modelsim_copy_files =
../../src/hex hex
+
+[quartus_project_file]
synth_top_level_entity =
quartus_copy_files =
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE_tx_only/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE_tx_only/hdllib.cfg
index 633c042366234c5c6e2b57822ae231418a5b2e74..5f2928ba59ef8a5163047783b2271c00b6ec3d32 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE_tx_only/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE_tx_only/hdllib.cfg
@@ -2,9 +2,11 @@ hdl_lib_name = unb1_test_10GbE_tx_only
hdl_library_clause_name = unb1_test_10GbE_tx_only_lib
hdl_lib_uses_synth = unb1_board unb1_test
hdl_lib_uses_sim =
-hdl_lib_excludes = ip_stratixiv_ddr3_uphy_4g_800_master ip_stratixiv_ddr3_uphy_4g_800_slave ip_stratixiv_ddr3_uphy_4g_single_rank_800_master ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave
-
hdl_lib_technology = ip_stratixiv
+hdl_lib_excludes = ip_stratixiv_ddr3_uphy_4g_800_master
+ ip_stratixiv_ddr3_uphy_4g_800_slave
+ ip_stratixiv_ddr3_uphy_4g_single_rank_800_master
+ ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave
synth_files =
unb1_test_10GbE_tx_only.vhd
@@ -12,9 +14,13 @@ synth_files =
test_bench_files =
tb_unb1_test_10GbE_tx_only.vhd
+
+[modelsim_project_file]
modelsim_copy_files =
../../src/hex hex
+
+[quartus_project_file]
synth_top_level_entity =
quartus_copy_files =
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/hdllib.cfg
index a2620cc92ceb1578ce9b5c94ec7699f17b6725a3..e7eae92f05ef62d0c11a201673793f75cdd12e79 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/hdllib.cfg
@@ -2,9 +2,11 @@ hdl_lib_name = unb1_test_1GbE
hdl_library_clause_name = unb1_test_1GbE_lib
hdl_lib_uses_synth = unb1_board unb1_test
hdl_lib_uses_sim =
-hdl_lib_excludes = ip_stratixiv_ddr3_uphy_4g_800_master ip_stratixiv_ddr3_uphy_4g_800_slave ip_stratixiv_ddr3_uphy_4g_single_rank_800_master ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave
-
hdl_lib_technology = ip_stratixiv
+hdl_lib_excludes = ip_stratixiv_ddr3_uphy_4g_800_master
+ ip_stratixiv_ddr3_uphy_4g_800_slave
+ ip_stratixiv_ddr3_uphy_4g_single_rank_800_master
+ ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave
synth_files =
unb1_test_1GbE.vhd
@@ -12,9 +14,13 @@ synth_files =
test_bench_files =
tb_unb1_test_1GbE.vhd
+
+[modelsim_project_file]
modelsim_copy_files =
../../src/hex hex
+
+[quartus_project_file]
synth_top_level_entity =
quartus_copy_files =
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/hdllib.cfg
index 72bd3170f6514a9b5c09c7ee4639fef082c222e5..309f8c6efc8fe4123a75ffc29b8eb005dce9cb71 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/hdllib.cfg
@@ -2,9 +2,10 @@ hdl_lib_name = unb1_test_all
hdl_library_clause_name = unb1_test_all_lib
hdl_lib_uses_synth = unb1_board unb1_test
hdl_lib_uses_sim =
-hdl_lib_excludes = ip_stratixiv_ddr3_uphy_4g_800_slave ip_stratixiv_ddr3_uphy_4g_single_rank_800_master ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave
-
hdl_lib_technology = ip_stratixiv
+hdl_lib_excludes = ip_stratixiv_ddr3_uphy_4g_800_slave
+ ip_stratixiv_ddr3_uphy_4g_single_rank_800_master
+ ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave
synth_files =
unb1_test_all.vhd
@@ -12,9 +13,16 @@ synth_files =
test_bench_files =
tb_unb1_test_all.vhd
+
+[modelsim_project_file]
modelsim_copy_files =
../../src/hex hex
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
+
+
+[quartus_project_file]
synth_top_level_entity =
quartus_copy_files =
@@ -38,6 +46,3 @@ quartus_qip_files =
$RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master.qip
#$RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/generated/ip_stratixiv_ddr3_uphy_4g_800_slave.qip
-modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
-
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/hdllib.cfg
index 6471298ee8288aa0f014cd1150359e94d112ebbb..6603d3c12547de32ef7bc72530b553b60a6dce9c 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/hdllib.cfg
@@ -2,9 +2,10 @@ hdl_lib_name = unb1_test_ddr
hdl_library_clause_name = unb1_test_ddr_lib
hdl_lib_uses_synth = unb1_board unb1_test
hdl_lib_uses_sim =
-hdl_lib_excludes = ip_stratixiv_ddr3_uphy_4g_800_slave ip_stratixiv_ddr3_uphy_4g_single_rank_800_master ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave
-
hdl_lib_technology = ip_stratixiv
+hdl_lib_excludes = ip_stratixiv_ddr3_uphy_4g_800_slave
+ ip_stratixiv_ddr3_uphy_4g_single_rank_800_master
+ ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave
synth_files =
unb1_test_ddr.vhd
@@ -12,9 +13,16 @@ synth_files =
test_bench_files =
tb_unb1_test_ddr.vhd
+
+[modelsim_project_file]
modelsim_copy_files =
../../src/hex hex
+
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
+
+[quartus_project_file]
synth_top_level_entity =
quartus_copy_files =
@@ -38,6 +46,3 @@ quartus_qip_files =
$RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master.qip
#$RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/generated/ip_stratixiv_ddr3_uphy_4g_800_slave.qip
-modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
-
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/hdllib.cfg
index a0af4901a7fc6e15e7a5a95f315c1bc250630681..1cc1ad308b46b928c62f8af48e2e07a27443b352 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/hdllib.cfg
@@ -2,9 +2,12 @@ hdl_lib_name = unb1_test_ddr_16g_MB_I
hdl_library_clause_name = unb1_test_ddr_16g_MB_I_lib
hdl_lib_uses_synth = unb1_board unb1_test
hdl_lib_uses_sim =
-hdl_lib_excludes = ip_stratixiv_ddr3_uphy_4g_800_master ip_stratixiv_ddr3_uphy_4g_800_slave ip_stratixiv_ddr3_uphy_4g_single_rank_800_master ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave
-
hdl_lib_technology = ip_stratixiv
+hdl_lib_excludes = ip_stratixiv_ddr3_uphy_4g_800_master
+ ip_stratixiv_ddr3_uphy_4g_800_slave
+ ip_stratixiv_ddr3_uphy_4g_single_rank_800_master
+ ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave
+
synth_files =
unb1_test_ddr_16g_MB_I.vhd
@@ -12,9 +15,16 @@ synth_files =
test_bench_files =
tb_unb1_test_ddr_16g_MB_I.vhd
+
+[modelsim_project_file]
modelsim_copy_files =
../../src/hex hex
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/copy_hex_files.tcl
+
+
+[quartus_project_file]
synth_top_level_entity =
quartus_copy_files =
@@ -37,6 +47,3 @@ quartus_qip_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_16g_MB_I/qsys_unb1_test/synthesis/qsys_unb1_test.qip
$RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/generated/ip_stratixiv_ddr3_uphy_16g_dual_rank_800.qip
-modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/copy_hex_files.tcl
-
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/hdllib.cfg
index b92e6f5e2fd444acc6c843a11c22e5b5661dc503..3e8133c285274fc29733f6bf7f1f1ae9068ccf8e 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/hdllib.cfg
@@ -2,9 +2,11 @@ hdl_lib_name = unb1_test_ddr_16g_MB_II
hdl_library_clause_name = unb1_test_ddr_16g_MB_II_lib
hdl_lib_uses_synth = unb1_board unb1_test
hdl_lib_uses_sim =
-hdl_lib_excludes = ip_stratixiv_ddr3_uphy_4g_800_master ip_stratixiv_ddr3_uphy_4g_800_slave ip_stratixiv_ddr3_uphy_4g_single_rank_800_master ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave
-
hdl_lib_technology = ip_stratixiv
+hdl_lib_excludes = ip_stratixiv_ddr3_uphy_4g_800_master
+ ip_stratixiv_ddr3_uphy_4g_800_slave
+ ip_stratixiv_ddr3_uphy_4g_single_rank_800_master
+ ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave
synth_files =
unb1_test_ddr_16g_MB_II.vhd
@@ -12,9 +14,16 @@ synth_files =
test_bench_files =
tb_unb1_test_ddr_16g_MB_II.vhd
+
+[modelsim_project_file]
modelsim_copy_files =
../../src/hex hex
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/copy_hex_files.tcl
+
+
+[quartus_project_file]
synth_top_level_entity =
quartus_copy_files =
@@ -37,6 +46,3 @@ quartus_qip_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_16g_MB_II/qsys_unb1_test/synthesis/qsys_unb1_test.qip
$RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/generated/ip_stratixiv_ddr3_uphy_16g_dual_rank_800.qip
-modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/copy_hex_files.tcl
-
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/hdllib.cfg
index 6931d7ff370b1a4ff004fe26a8184af799781f5a..6cd6991ddd6ff9b7f903e6303e4dac80121e1c89 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/hdllib.cfg
@@ -2,22 +2,28 @@ hdl_lib_name = unb1_test_ddr_16g_MB_I_II
hdl_library_clause_name = unb1_test_ddr_16g_MB_I_II_lib
hdl_lib_uses_synth = unb1_board unb1_test
hdl_lib_uses_sim =
+hdl_lib_technology = ip_stratixiv
hdl_lib_excludes = ip_stratixiv_ddr3_uphy_4g_single_rank_800_master
ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave
ip_stratixiv_ddr3_uphy_4g_800_master
ip_stratixiv_ddr3_uphy_4g_800_slave
-hdl_lib_technology = ip_stratixiv
-
synth_files =
unb1_test_ddr_16g_MB_I_II.vhd
test_bench_files =
tb_unb1_test_ddr_16g_MB_I_II.vhd
+
+[modelsim_project_file]
modelsim_copy_files =
../../src/hex hex
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/copy_hex_files.tcl
+
+
+[quartus_project_file]
synth_top_level_entity =
quartus_copy_files =
@@ -40,6 +46,3 @@ quartus_qip_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_16g_MB_I_II/qsys_unb1_test/synthesis/qsys_unb1_test.qip
$RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/generated/ip_stratixiv_ddr3_uphy_16g_dual_rank_800.qip
-modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/copy_hex_files.tcl
-
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I/hdllib.cfg
index 9d9761cddb783918ee65f4c7201e112d110c0d6f..01a53de499df6d9b5c0192dba5330fc83b963041 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I/hdllib.cfg
@@ -2,9 +2,11 @@ hdl_lib_name = unb1_test_ddr_MB_I
hdl_library_clause_name = unb1_test_ddr_MB_I_lib
hdl_lib_uses_synth = unb1_board unb1_test
hdl_lib_uses_sim =
-hdl_lib_excludes = ip_stratixiv_ddr3_uphy_16g_dual_rank_800 ip_stratixiv_ddr3_uphy_4g_800_slave ip_stratixiv_ddr3_uphy_4g_800_master ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave
-
hdl_lib_technology = ip_stratixiv
+hdl_lib_excludes = ip_stratixiv_ddr3_uphy_16g_dual_rank_800
+ ip_stratixiv_ddr3_uphy_4g_800_slave
+ ip_stratixiv_ddr3_uphy_4g_800_master
+ ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave
synth_files =
unb1_test_ddr_MB_I.vhd
@@ -12,9 +14,16 @@ synth_files =
test_bench_files =
tb_unb1_test_ddr_MB_I.vhd
+
+[modelsim_project_file]
modelsim_copy_files =
../../src/hex hex
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
+
+
+[quartus_project_file]
synth_top_level_entity =
quartus_copy_files =
@@ -37,6 +46,3 @@ quartus_qip_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_MB_I/qsys_unb1_test/synthesis/qsys_unb1_test.qip
$RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
-modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
-
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_II/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_II/hdllib.cfg
index 569fa8f3606dca02303835c8d10587e009c54388..999ef9629c1145a1bc76e613676c2a39bcb00ef2 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_II/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_II/hdllib.cfg
@@ -2,9 +2,12 @@ hdl_lib_name = unb1_test_ddr_MB_II
hdl_library_clause_name = unb1_test_ddr_MB_II_lib
hdl_lib_uses_synth = unb1_board unb1_test
hdl_lib_uses_sim =
-hdl_lib_excludes = ip_stratixiv_ddr3_uphy_16g_dual_rank_800 ip_stratixiv_ddr3_uphy_4g_800_slave ip_stratixiv_ddr3_uphy_4g_800_master ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave
-
hdl_lib_technology = ip_stratixiv
+hdl_lib_excludes = ip_stratixiv_ddr3_uphy_16g_dual_rank_800
+ ip_stratixiv_ddr3_uphy_4g_800_slave
+ ip_stratixiv_ddr3_uphy_4g_800_master
+ ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave
+
synth_files =
unb1_test_ddr_MB_II.vhd
@@ -12,9 +15,16 @@ synth_files =
test_bench_files =
tb_unb1_test_ddr_MB_II.vhd
+
+[modelsim_project_file]
modelsim_copy_files =
../../src/hex hex
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
+
+
+[quartus_project_file]
synth_top_level_entity =
quartus_copy_files =
@@ -37,6 +47,3 @@ quartus_qip_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_MB_II/qsys_unb1_test/synthesis/qsys_unb1_test.qip
$RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
-modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
-
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/hdllib.cfg
index 6e0d0d2402b88a0310cbec0d4d1da55ea57392f8..2ff1c3c08f9dc115d19a130cd5d62b4abf07b509 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/hdllib.cfg
@@ -2,22 +2,27 @@ hdl_lib_name = unb1_test_ddr_MB_I_II
hdl_library_clause_name = unb1_test_ddr_MB_I_II_lib
hdl_lib_uses_synth = unb1_board unb1_test
hdl_lib_uses_sim =
+hdl_lib_technology = ip_stratixiv
hdl_lib_excludes = ip_stratixiv_ddr3_uphy_16g_dual_rank_800
ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave
ip_stratixiv_ddr3_uphy_4g_800_master
ip_stratixiv_ddr3_uphy_4g_800_slave
-hdl_lib_technology = ip_stratixiv
-
synth_files =
unb1_test_ddr_MB_I_II.vhd
test_bench_files =
tb_unb1_test_ddr_MB_I_II.vhd
+[modelsim_project_file]
modelsim_copy_files =
../../src/hex hex
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
+
+
+[quartus_project_file]
synth_top_level_entity =
quartus_copy_files =
@@ -40,6 +45,3 @@ quartus_qip_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_MB_I_II/qsys_unb1_test/synthesis/qsys_unb1_test.qip
$RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
-modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
-
diff --git a/boards/uniboard1/designs/unb1_tr_10GbE/hdllib.cfg b/boards/uniboard1/designs/unb1_tr_10GbE/hdllib.cfg
index 8ff59c1f1a717d916e760e8fc7996dd7f4501138..3ef8d196d4e38ef189c34edcc39585eff7151142 100644
--- a/boards/uniboard1/designs/unb1_tr_10GbE/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_tr_10GbE/hdllib.cfg
@@ -2,18 +2,8 @@ hdl_lib_name = unb1_tr_10GbE
hdl_library_clause_name = unb1_tr_10GbE_lib
hdl_lib_uses_synth = common mm dp i2c unb1_board tr_10GbE diag
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_stratixiv
-synth_top_level_entity =
-
-quartus_copy_files =
- quartus/qsys_unb1_tr_10GbE.qsys .
-# src/hex/ hex
-
-modelsim_copy_files =
-# src/hex hex
-
synth_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_tr_10GbE/qsys_unb1_tr_10GbE/synthesis/qsys_unb1_tr_10GbE.v
src/vhdl/mmm_unb1_tr_10GbE.vhd
@@ -22,6 +12,19 @@ synth_files =
test_bench_files =
tb/vhdl/tb_unb1_tr_10GbE.vhd
+
+[modelsim_project_file]
+modelsim_copy_files =
+# src/hex hex
+
+
+[quartus_project_file]
+synth_top_level_entity =
+
+quartus_copy_files =
+ quartus/qsys_unb1_tr_10GbE.qsys .
+# src/hex/ hex
+
quartus_qsf_files =
$RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
diff --git a/boards/uniboard1/libraries/unb1_board/hdllib.cfg b/boards/uniboard1/libraries/unb1_board/hdllib.cfg
index a047b9247c98ce02d042a61205be3e938d037e0e..bce15bdfb32a1a78c1190f55dc3140c82018c31f 100644
--- a/boards/uniboard1/libraries/unb1_board/hdllib.cfg
+++ b/boards/uniboard1/libraries/unb1_board/hdllib.cfg
@@ -2,7 +2,6 @@ hdl_lib_name = unb1_board
hdl_library_clause_name = unb1_board_lib
hdl_lib_uses_synth = common dp diag uth ppsh i2c tr_nonbonded eth remu technology tech_pll epcs
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_stratixiv
synth_files =
@@ -59,3 +58,10 @@ test_bench_files =
tb/vhdl/tb_unb1_board_mesh_reorder_bidir.vhd
tb/vhdl/tb_tb_tb_unb1_board_regression.vhd
+
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+
diff --git a/boards/uniboard2/designs/unb2_led/hdllib.cfg b/boards/uniboard2/designs/unb2_led/hdllib.cfg
index 674b89da0f420e4375f623e4ed76ec54e5595dc3..b827bc6b809c0afd8cb8cd88e474a3fb45aee3b4 100644
--- a/boards/uniboard2/designs/unb2_led/hdllib.cfg
+++ b/boards/uniboard2/designs/unb2_led/hdllib.cfg
@@ -2,7 +2,6 @@ hdl_lib_name = unb2_led
hdl_library_clause_name = unb2_led_lib
hdl_lib_uses_synth = common technology unb2_board
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_arria10
synth_files =
@@ -11,6 +10,11 @@ synth_files =
test_bench_files =
tb/vhdl/tb_unb2_led.vhd
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
synth_top_level_entity =
quartus_copy_files =
diff --git a/boards/uniboard2/designs/unb2_minimal/hdllib.cfg b/boards/uniboard2/designs/unb2_minimal/hdllib.cfg
index f0eaef9977010323c627832f26c8cd1b486bf12a..1f74d99516bc01e435cf047152032752a16ec5f4 100644
--- a/boards/uniboard2/designs/unb2_minimal/hdllib.cfg
+++ b/boards/uniboard2/designs/unb2_minimal/hdllib.cfg
@@ -2,9 +2,8 @@ hdl_lib_name = unb2_minimal
hdl_library_clause_name = unb2_minimal_lib
hdl_lib_uses_synth = common technology mm unb2_board
hdl_lib_uses_sim =
-hdl_lib_excludes = ip_arria10_mac_10g
-
hdl_lib_technology = ip_arria10
+hdl_lib_excludes = ip_arria10_mac_10g
synth_files =
src/vhdl/qsys_unb2_minimal_pkg.vhd
@@ -14,6 +13,11 @@ synth_files =
test_bench_files =
tb/vhdl/tb_unb2_minimal.vhd
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
synth_top_level_entity =
quartus_copy_files =
diff --git a/boards/uniboard2/designs/unb2_test/hdllib.cfg b/boards/uniboard2/designs/unb2_test/hdllib.cfg
index 6bb91f9b1b8967a6a705f61d841bb669d03d8c59..22b2ff95256e1b9e731438ed49f5c6ac95c251e1 100644
--- a/boards/uniboard2/designs/unb2_test/hdllib.cfg
+++ b/boards/uniboard2/designs/unb2_test/hdllib.cfg
@@ -2,7 +2,6 @@ hdl_lib_name = unb2_test
hdl_library_clause_name = unb2_test_lib
hdl_lib_uses_synth = common technology mm unb2_board unb2_board_10gbe dp eth tech_tse tr_10GbE diagnostics diag tech_mac_10g io_ddr tech_ddr
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_arria10
synth_files =
@@ -15,3 +14,9 @@ synth_files =
test_bench_files =
tb/vhdl/tb_unb2_test.vhd
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/hdllib.cfg b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/hdllib.cfg
index 86cd5c864bae11956880c80d28f3be47ad002d44..adbdf99c917fb0d2e5417f16b63661f1ffd76dad 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/hdllib.cfg
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/hdllib.cfg
@@ -2,9 +2,12 @@ hdl_lib_name = unb2_test_10GbE
hdl_library_clause_name = unb2_test_10GbE_lib
hdl_lib_uses_synth = common mm technology unb2_board unb2_test
hdl_lib_uses_sim =
-hdl_lib_excludes = ip_arria10_ddr4_4g_1600 ip_arria10_ddr4_8g_2400 ip_arria10_ddr4_4g_2000 ip_arria10_phy_10gbase_r ip_arria10_transceiver_reset_controller_1
-
hdl_lib_technology = ip_arria10
+hdl_lib_excludes = ip_arria10_ddr4_4g_1600
+ ip_arria10_ddr4_8g_2400
+ ip_arria10_ddr4_4g_2000
+ ip_arria10_phy_10gbase_r
+ ip_arria10_transceiver_reset_controller_1
synth_files =
unb2_test_10GbE.vhd
@@ -12,9 +15,13 @@ synth_files =
test_bench_files =
tb_unb2_test_10GbE.vhd
+
+[modelsim_project_file]
modelsim_copy_files =
../../src/hex hex
+
+[quartus_project_file]
synth_top_level_entity =
quartus_copy_files =
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/hdllib.cfg b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/hdllib.cfg
index 6af51957556857667eefbc656b5fd58a46ce00e6..2479dbcda31bee34431be7bd172edb478672be91 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/hdllib.cfg
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/hdllib.cfg
@@ -2,9 +2,11 @@ hdl_lib_name = unb2_test_1GbE
hdl_library_clause_name = unb2_test_1GbE_lib
hdl_lib_uses_synth = common mm technology unb2_board unb2_test
hdl_lib_uses_sim =
-hdl_lib_excludes = ip_arria10_ddr4_4g_1600 ip_arria10_ddr4_8g_2400 ip_arria10_ddr4_4g_2000 ip_arria10_mac_10g
-
hdl_lib_technology = ip_arria10
+hdl_lib_excludes = ip_arria10_ddr4_4g_1600
+ ip_arria10_ddr4_8g_2400
+ ip_arria10_ddr4_4g_2000
+ ip_arria10_mac_10g
synth_files =
unb2_test_1GbE.vhd
@@ -12,9 +14,13 @@ synth_files =
test_bench_files =
tb_unb2_test_1GbE.vhd
+
+[modelsim_project_file]
modelsim_copy_files =
../../src/hex hex
+
+[quartus_project_file]
synth_top_level_entity =
quartus_copy_files =
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/hdllib.cfg b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/hdllib.cfg
index afb79d2f088474b413b82e72220a957fee372bdf..65eca953849b7b45dff9fdcb03652cf38f10819d 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/hdllib.cfg
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/hdllib.cfg
@@ -2,8 +2,11 @@ hdl_lib_name = unb2_test_all
hdl_library_clause_name = unb2_test_all_lib
hdl_lib_uses_synth = common mm technology unb2_board unb2_test
hdl_lib_uses_sim =
-hdl_lib_excludes = ip_arria10_ddr4_8g_2400 ip_arria10_ddr4_4g_2000 ip_arria10_phy_10gbase_r ip_arria10_transceiver_reset_controller_1
hdl_lib_technology = ip_arria10
+hdl_lib_excludes = ip_arria10_ddr4_8g_2400
+ ip_arria10_ddr4_4g_2000
+ ip_arria10_phy_10gbase_r
+ ip_arria10_transceiver_reset_controller_1
synth_files =
unb2_test_all.vhd
@@ -11,9 +14,13 @@ synth_files =
test_bench_files =
tb_unb2_test_all.vhd
+
+[modelsim_project_file]
modelsim_copy_files =
../../src/hex hex
+
+[quartus_project_file]
synth_top_level_entity =
quartus_copy_files =
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/hdllib.cfg b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/hdllib.cfg
index b48fb0e7044e46b433a8197f7a2c39bcee7f13e8..e16917e8fc4450540ea88d996a51a2bd035e2b27 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/hdllib.cfg
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/hdllib.cfg
@@ -20,12 +20,16 @@ synth_files =
test_bench_files =
tb_unb2_test_ddr_MB_I.vhd
-modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10/ddr4_4g_1600/copy_hex_files.tcl
-
+
+[modelsim_project_file]
modelsim_copy_files =
../../src/hex hex
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10/ddr4_4g_1600/copy_hex_files.tcl
+
+
+[quartus_project_file]
synth_top_level_entity =
quartus_copy_files =
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/hdllib.cfg b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/hdllib.cfg
index a097f6e1c5385b6d99dfc8166f68f4c497346b3f..fd8757b6464767b2257e4ba16364140f098d379e 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/hdllib.cfg
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/hdllib.cfg
@@ -20,12 +20,16 @@ synth_files =
test_bench_files =
tb_unb2_test_ddr_MB_II.vhd
+
+[modelsim_project_file]
+modelsim_copy_files =
+ ../../src/hex hex
+
modelsim_compile_ip_files =
$RADIOHDL/libraries/technology/ip_arria10/ddr4_4g_1600/copy_hex_files.tcl
-modelsim_copy_files =
- ../../src/hex hex
+[quartus_project_file]
synth_top_level_entity =
quartus_copy_files =
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/hdllib.cfg b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/hdllib.cfg
index 4c50965953c432608bc6680027831f16d35c9a3b..f3a98983f91dc1d79e892d1022380ef564823ea1 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/hdllib.cfg
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/hdllib.cfg
@@ -20,12 +20,16 @@ synth_files =
test_bench_files =
tb_unb2_test_ddr_MB_I_II.vhd
+
+[modelsim_project_file]
+modelsim_copy_files =
+ ../../src/hex hex
+
modelsim_compile_ip_files =
$RADIOHDL/libraries/technology/ip_arria10/ddr4_4g_1600/copy_hex_files.tcl
-modelsim_copy_files =
- ../../src/hex hex
+[quartus_project_file]
synth_top_level_entity =
quartus_copy_files =
diff --git a/boards/uniboard2/libraries/unb2_board/hdllib.cfg b/boards/uniboard2/libraries/unb2_board/hdllib.cfg
index 9fac903d505aa953968fcf86cd7a1cde1e7c99a5..30ff80632cd79885d2d1ac6d5f0918ff574d6303 100644
--- a/boards/uniboard2/libraries/unb2_board/hdllib.cfg
+++ b/boards/uniboard2/libraries/unb2_board/hdllib.cfg
@@ -2,7 +2,6 @@ hdl_lib_name = unb2_board
hdl_library_clause_name = unb2_board_lib
hdl_lib_uses_synth = common dp ppsh i2c eth remu technology tech_clkbuf tech_pll tech_fractional_pll epcs fpga_sense
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_arria10
synth_files =
@@ -38,3 +37,9 @@ test_bench_files =
tb/vhdl/tb_unb2_board_node_ctrl.vhd
tb/vhdl/tb_unb2_board_qsfp_leds.vhd
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+
diff --git a/boards/uniboard2/libraries/unb2_board_10gbe/hdllib.cfg b/boards/uniboard2/libraries/unb2_board_10gbe/hdllib.cfg
index da343c764dd5fd4e2085defb61e305f89054016f..5e59d9e1c98b45ae36f6862320b8386c2300c110 100644
--- a/boards/uniboard2/libraries/unb2_board_10gbe/hdllib.cfg
+++ b/boards/uniboard2/libraries/unb2_board_10gbe/hdllib.cfg
@@ -2,7 +2,6 @@ hdl_lib_name = unb2_board_10gbe
hdl_library_clause_name = unb2_board_10gbe_lib
hdl_lib_uses_synth = common dp technology tech_pll tr_10GbE
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_arria10
synth_files =
@@ -10,3 +9,9 @@ synth_files =
test_bench_files =
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+
diff --git a/boards/uniboard2a/designs/unb2a_heater/hdllib.cfg b/boards/uniboard2a/designs/unb2a_heater/hdllib.cfg
index 8d7359470c38191840fb69f430ded4ae2d2f3378..db1ae4630939bbb8d8b9cc0bd17407eac1733471 100644
--- a/boards/uniboard2a/designs/unb2a_heater/hdllib.cfg
+++ b/boards/uniboard2a/designs/unb2a_heater/hdllib.cfg
@@ -2,6 +2,7 @@ hdl_lib_name = unb2a_heater
hdl_library_clause_name = unb2a_heater_lib
hdl_lib_uses_synth = common technology mm unb2a_board util
hdl_lib_uses_sim =
+hdl_lib_technology = ip_arria10_e3sge3
hdl_lib_excludes = ip_arria10_e3sge3_mac_10g
ip_arria10_e3sge3_pll_xgmii_mac_clocks
ip_arria10_e3sge3_pll_clk25
@@ -9,8 +10,6 @@ hdl_lib_excludes = ip_arria10_e3sge3_mac_10g
ip_arria10_e3sge3_pll_clk200
ip_arria10_e3sge3_tse_sgmii_gx
-hdl_lib_technology = ip_arria10_e3sge3
-
synth_files =
src/vhdl/qsys_unb2a_heater_pkg.vhd
src/vhdl/mmm_unb2a_heater.vhd
@@ -19,6 +18,11 @@ synth_files =
test_bench_files =
tb/vhdl/tb_unb2a_heater.vhd
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
synth_top_level_entity =
quartus_copy_files =
diff --git a/boards/uniboard2a/designs/unb2a_minimal/hdllib.cfg b/boards/uniboard2a/designs/unb2a_minimal/hdllib.cfg
index fe768029493e6e2b38eb64749f0414ddfe9bf8cb..06105d861ed6268617d8017d8e20891471dd0a56 100644
--- a/boards/uniboard2a/designs/unb2a_minimal/hdllib.cfg
+++ b/boards/uniboard2a/designs/unb2a_minimal/hdllib.cfg
@@ -2,6 +2,7 @@ hdl_lib_name = unb2a_minimal
hdl_library_clause_name = unb2a_minimal_lib
hdl_lib_uses_synth = common technology mm unb2a_board
hdl_lib_uses_sim =
+hdl_lib_technology = ip_arria10_e3sge3
hdl_lib_excludes = ip_arria10_e3sge3_mac_10g
ip_arria10_e3sge3_pll_xgmii_mac_clocks
ip_arria10_e3sge3_pll_clk25
@@ -9,8 +10,6 @@ hdl_lib_excludes = ip_arria10_e3sge3_mac_10g
ip_arria10_e3sge3_pll_clk200
ip_arria10_e3sge3_tse_sgmii_gx
-hdl_lib_technology = ip_arria10_e3sge3
-
synth_files =
src/vhdl/qsys_unb2a_minimal_pkg.vhd
src/vhdl/mmm_unb2a_minimal.vhd
@@ -19,6 +18,11 @@ synth_files =
test_bench_files =
tb/vhdl/tb_unb2a_minimal.vhd
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
synth_top_level_entity =
quartus_copy_files =
diff --git a/boards/uniboard2a/designs/unb2a_test/hdllib.cfg b/boards/uniboard2a/designs/unb2a_test/hdllib.cfg
index fad4c3599a231f5b300a0c3e39ce7e374b8755b1..a25ee649325f95a3134969b1636f954a7ae3de38 100644
--- a/boards/uniboard2a/designs/unb2a_test/hdllib.cfg
+++ b/boards/uniboard2a/designs/unb2a_test/hdllib.cfg
@@ -2,7 +2,6 @@ hdl_lib_name = unb2a_test
hdl_library_clause_name = unb2a_test_lib
hdl_lib_uses_synth = common technology mm unb2a_board unb2a_board_10gbe dp eth tech_tse tr_10GbE diagnostics diag tech_mac_10g io_ddr tech_ddr
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_arria10_e3sge3
synth_files =
@@ -15,3 +14,9 @@ synth_files =
test_bench_files =
tb/vhdl/tb_unb2a_test.vhd
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/hdllib.cfg b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/hdllib.cfg
index f887ae0e7b71f9085b1ff57ae5814174a9d4edab..2dc9b1464a36d1fdca0d647ccfd607cb18a22a45 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/hdllib.cfg
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/hdllib.cfg
@@ -2,6 +2,7 @@ hdl_lib_name = unb2a_test_10GbE
hdl_library_clause_name = unb2a_test_10GbE_lib
hdl_lib_uses_synth = common mm technology unb2a_board unb2a_test
hdl_lib_uses_sim =
+hdl_lib_technology = ip_arria10_e3sge3
hdl_lib_excludes = ip_arria10_e3sge3_ddr4_4g_1600
ip_arria10_e3sge3_ddr4_4g_2000
ip_arria10_e3sge3_ddr4_8g_1600
@@ -9,17 +10,19 @@ hdl_lib_excludes = ip_arria10_e3sge3_ddr4_4g_1600
ip_arria10_e3sge3_phy_10gbase_r
ip_arria10_e3sge3_transceiver_reset_controller_1
-hdl_lib_technology = ip_arria10_e3sge3
-
synth_files =
unb2a_test_10GbE.vhd
test_bench_files =
tb_unb2a_test_10GbE.vhd
+
+[modelsim_project_file]
modelsim_copy_files =
../../src/hex hex
+
+[quartus_project_file]
synth_top_level_entity =
quartus_copy_files =
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/hdllib.cfg b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/hdllib.cfg
index c0fbe15c895e66b55634a8780f10519571872447..b01a7885c3dfc5c9b3c1969c4a48f5202f43d260 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/hdllib.cfg
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/hdllib.cfg
@@ -2,9 +2,11 @@ hdl_lib_name = unb2a_test_1GbE
hdl_library_clause_name = unb2a_test_1GbE_lib
hdl_lib_uses_synth = common mm technology unb2a_board unb2a_test
hdl_lib_uses_sim =
-hdl_lib_excludes = ip_arria10_e3sge3_ddr4_4g_1600 ip_arria10_e3sge3_ddr4_8g_2400 ip_arria10_e3sge3_ddr4_4g_2000 ip_arria10_e3sge3_mac_10g
-
hdl_lib_technology = ip_arria10_e3sge3
+hdl_lib_excludes = ip_arria10_e3sge3_ddr4_4g_1600
+ ip_arria10_e3sge3_ddr4_8g_2400
+ ip_arria10_e3sge3_ddr4_4g_2000
+ ip_arria10_e3sge3_mac_10g
synth_files =
unb2a_test_1GbE.vhd
@@ -12,9 +14,13 @@ synth_files =
test_bench_files =
tb_unb2a_test_1GbE.vhd
+
+[modelsim_project_file]
modelsim_copy_files =
../../src/hex hex
+
+[quartus_project_file]
synth_top_level_entity =
quartus_copy_files =
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/hdllib.cfg b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/hdllib.cfg
index 838bd77316ae18011aab1b21a545c285e73abaf5..59aacc877c9f2262f9b8397ae5e99983daa299d6 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/hdllib.cfg
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/hdllib.cfg
@@ -2,18 +2,25 @@ hdl_lib_name = unb2a_test_all
hdl_library_clause_name = unb2a_test_all_lib
hdl_lib_uses_synth = common mm technology unb2a_board unb2a_test
hdl_lib_uses_sim =
-hdl_lib_excludes = ip_arria10_e3sge3_ddr4_8g_2400 ip_arria10_e3sge3_ddr4_4g_2000 ip_arria10_e3sge3_phy_10gbase_r ip_arria10_e3sge3_transceiver_reset_controller_1
hdl_lib_technology = ip_arria10_e3sge3
-
+hdl_lib_excludes = ip_arria10_e3sge3_ddr4_8g_2400
+ ip_arria10_e3sge3_ddr4_4g_2000
+ ip_arria10_e3sge3_phy_10gbase_r
+ ip_arria10_e3sge3_transceiver_reset_controller_1
+
synth_files =
unb2a_test_all.vhd
test_bench_files =
tb_unb2a_test_all.vhd
+
+[modelsim_project_file]
modelsim_copy_files =
../../src/hex hex
+
+[quartus_project_file]
synth_top_level_entity =
quartus_copy_files =
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/hdllib.cfg b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/hdllib.cfg
index aa25d3e9e1915fb1ee93027e8877f73a861a26b1..ef6693b1732734da279eb7aee98f8ed6454559ed 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/hdllib.cfg
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/hdllib.cfg
@@ -21,12 +21,16 @@ synth_files =
test_bench_files =
tb_unb2a_test_ddr_MB_I.vhd
-modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/copy_hex_files.tcl
-
+
+[modelsim_project_file]
modelsim_copy_files =
../../src/hex hex
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/copy_hex_files.tcl
+
+
+[quartus_project_file]
synth_top_level_entity =
quartus_copy_files =
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/hdllib.cfg b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/hdllib.cfg
index 68aeacf304b38e6e240b2f98c90d126295dc9d4a..847a9e97223913155468fe4e07093642f8a76da6 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/hdllib.cfg
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/hdllib.cfg
@@ -21,12 +21,16 @@ synth_files =
test_bench_files =
tb_unb2a_test_ddr_MB_II.vhd
+
+[modelsim_project_file]
+modelsim_copy_files =
+ ../../src/hex hex
+
modelsim_compile_ip_files =
$RADIOHDL/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/copy_hex_files.tcl
-modelsim_copy_files =
- ../../src/hex hex
+[quartus_project_file]
synth_top_level_entity =
quartus_copy_files =
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/hdllib.cfg b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/hdllib.cfg
index 70c3cca8aff110b3aeb582785b7cbf0e4619af70..985265b3e9c65defd39da2d205784042ce36769c 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/hdllib.cfg
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/hdllib.cfg
@@ -21,12 +21,16 @@ synth_files =
test_bench_files =
tb_unb2a_test_ddr_MB_I_II.vhd
+
+[modelsim_project_file]
+modelsim_copy_files =
+ ../../src/hex hex
+
modelsim_compile_ip_files =
$RADIOHDL/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/copy_hex_files.tcl
-modelsim_copy_files =
- ../../src/hex hex
+[quartus_project_file]
synth_top_level_entity =
quartus_copy_files =
diff --git a/boards/uniboard2a/libraries/unb2a_board/hdllib.cfg b/boards/uniboard2a/libraries/unb2a_board/hdllib.cfg
index 9ff804ab5255880366d9eee24e04325a5fcd13c2..cb14fa462fd740642a9b60ccf88bda923002b333 100644
--- a/boards/uniboard2a/libraries/unb2a_board/hdllib.cfg
+++ b/boards/uniboard2a/libraries/unb2a_board/hdllib.cfg
@@ -2,7 +2,6 @@ hdl_lib_name = unb2a_board
hdl_library_clause_name = unb2a_board_lib
hdl_lib_uses_synth = common dp ppsh i2c eth remu technology tech_clkbuf tech_pll tech_fractional_pll epcs fpga_sense
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_arria10_e3sge3
synth_files =
@@ -38,3 +37,9 @@ test_bench_files =
tb/vhdl/tb_unb2_board_node_ctrl.vhd
tb/vhdl/tb_unb2_board_qsfp_leds.vhd
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+
diff --git a/boards/uniboard2a/libraries/unb2a_board_10gbe/hdllib.cfg b/boards/uniboard2a/libraries/unb2a_board_10gbe/hdllib.cfg
index 5ec5ad52e49361cf1926c5e244e000a679820080..23ae0d618e022d6eb2acc9184b6d088ddb9dbe11 100644
--- a/boards/uniboard2a/libraries/unb2a_board_10gbe/hdllib.cfg
+++ b/boards/uniboard2a/libraries/unb2a_board_10gbe/hdllib.cfg
@@ -2,7 +2,6 @@ hdl_lib_name = unb2a_board_10gbe
hdl_library_clause_name = unb2a_board_10gbe_lib
hdl_lib_uses_synth = common dp technology tech_pll tr_10GbE
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_arria10_e3sge3
synth_files =
@@ -10,3 +9,9 @@ synth_files =
test_bench_files =
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+
diff --git a/libraries/base/common/hdllib.cfg b/libraries/base/common/hdllib.cfg
index 3a903aa000953ab388e33704a18d0a8fb901d90c..bb6293abc4b63ea0f62dab99a475d159c537362f 100644
--- a/libraries/base/common/hdllib.cfg
+++ b/libraries/base/common/hdllib.cfg
@@ -2,7 +2,6 @@ hdl_lib_name = common
hdl_library_clause_name = common_lib
hdl_lib_uses_synth = technology tech_memory tech_fifo tech_iobuf tst
hdl_lib_uses_sim =
-
hdl_lib_technology =
synth_files =
@@ -194,3 +193,10 @@ test_bench_files =
tb/vhdl/tb_tb_common_rl.vhd
tb/vhdl/tb_tb_common_rl_register.vhd
tb/vhdl/tb_tb_common_transpose.vhd
+
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+
diff --git a/libraries/base/common_mult/hdllib.cfg b/libraries/base/common_mult/hdllib.cfg
index 75d8b3889b9d483de2bfb6fc7c3e7785386df06b..df4cdb0d9d0e8d7ddbb1eeecf2a26caacab8f86a 100644
--- a/libraries/base/common_mult/hdllib.cfg
+++ b/libraries/base/common_mult/hdllib.cfg
@@ -2,7 +2,6 @@ hdl_lib_name = common_mult
hdl_library_clause_name = common_mult_lib
hdl_lib_uses_synth = common technology tech_mult
hdl_lib_uses_sim =
-
hdl_lib_technology =
synth_files =
@@ -18,3 +17,10 @@ test_bench_files =
tb/vhdl/tb_common_complex_mult.vhd
tb/vhdl/tb_tb_common_mult.vhd
+
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+
diff --git a/libraries/base/diag/hdllib.cfg b/libraries/base/diag/hdllib.cfg
index afb94b13ad4e99c04a10019bb6fe942bc0e028a9..d3ab815ac0b476efe7d2efb32be5133f9ab5c4bc 100644
--- a/libraries/base/diag/hdllib.cfg
+++ b/libraries/base/diag/hdllib.cfg
@@ -2,7 +2,6 @@ hdl_lib_name = diag
hdl_library_clause_name = diag_lib
hdl_lib_uses_synth = dp common common_mult technology
hdl_lib_uses_sim =
-
hdl_lib_technology =
synth_files =
@@ -42,6 +41,12 @@ test_bench_files =
tb/vhdl/tb_tb_mms_diag_block_gen.vhd
tb/vhdl/tb_diag_regression.vhd
+
+[modelsim_project_file]
modelsim_copy_files =
src/data data
+
+
+[quartus_project_file]
+
\ No newline at end of file
diff --git a/libraries/base/diagnostics/hdllib.cfg b/libraries/base/diagnostics/hdllib.cfg
index dfab915a221e3f3d4b25e38b8e8f42c3a5ac50b2..cb89f13910512fa37f0e33af4cb3d8e7617649d6 100644
--- a/libraries/base/diagnostics/hdllib.cfg
+++ b/libraries/base/diagnostics/hdllib.cfg
@@ -2,7 +2,6 @@ hdl_lib_name = diagnostics
hdl_library_clause_name = diagnostics_lib
hdl_lib_uses_synth = common dp diag
hdl_lib_uses_sim =
-
hdl_lib_technology =
synth_files =
@@ -19,3 +18,10 @@ test_bench_files =
tb/vhdl/tb_diagnostics_trnb_pkg.vhd
tb/vhdl/tb_diagnostics.vhd
tb/vhdl/tb_mm_tx_framer.vhd
+
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+
diff --git a/libraries/base/dp/designs/unb1_dp_offload/hdllib.cfg b/libraries/base/dp/designs/unb1_dp_offload/hdllib.cfg
index f46a5d0d55192f9e06e39b77e48dd6e983953769..4e1c6925aba277145ea4c6d426fef5903d2a73b9 100644
--- a/libraries/base/dp/designs/unb1_dp_offload/hdllib.cfg
+++ b/libraries/base/dp/designs/unb1_dp_offload/hdllib.cfg
@@ -2,18 +2,8 @@ hdl_lib_name = unb1_dp_offload
hdl_library_clause_name = unb1_dp_offload_lib
hdl_lib_uses_synth = common dp unb1_board diag
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_stratixiv
-synth_top_level_entity =
-
-quartus_copy_files =
- quartus/sopc_unb1_dp_offload.sopc .
- src/hex hex
-
-modelsim_copy_files =
- src/hex hex
-
synth_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_dp_offload/sopc_unb1_dp_offload.vhd
src/vhdl/mmm_unb1_dp_offload.vhd
@@ -22,6 +12,19 @@ synth_files =
test_bench_files =
tb/vhdl/tb_unb1_dp_offload.vhd
+
+[modelsim_project_file]
+modelsim_copy_files =
+ src/hex hex
+
+
+[quartus_project_file]
+synth_top_level_entity =
+
+quartus_copy_files =
+ quartus/sopc_unb1_dp_offload.sopc .
+ src/hex hex
+
quartus_qsf_files =
$RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board_head.qsf
$RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board_tail.qsf
diff --git a/libraries/base/dp/hdllib.cfg b/libraries/base/dp/hdllib.cfg
index 5045c7571d8e61ef85b6de631feecae73c9b7206..553a94ac8ce782d52d3fa484aa9d1c12387372c0 100644
--- a/libraries/base/dp/hdllib.cfg
+++ b/libraries/base/dp/hdllib.cfg
@@ -2,7 +2,6 @@ hdl_lib_name = dp
hdl_library_clause_name = dp_lib
hdl_lib_uses_synth = mm common common_mult easics
hdl_lib_uses_sim =
-
hdl_lib_technology =
synth_files =
@@ -205,8 +204,6 @@ test_bench_files =
tb/vhdl/tb_tb_dp_pad_insert_remove.vhd
tb/vhdl/tb_tb_dp_packetizing.vhd
tb/vhdl/tb_tb_dp_packet.vhd
-
-
tb/vhdl/tb_tb_dp_packet_merge.vhd
tb/vhdl/tb_tb_dp_pipeline.vhd
tb/vhdl/tb_tb_dp_pipeline_ready.vhd
@@ -215,3 +212,9 @@ test_bench_files =
tb/vhdl/tb_tb_dp_sync_checker.vhd
tb/vhdl/tb_tb_tb_dp_backpressure.vhd
+
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
diff --git a/libraries/base/mm/hdllib.cfg b/libraries/base/mm/hdllib.cfg
index 14cd3a1a9dd08215039dd375ef55217347d50d1f..454828faabcb826934694f454cdfce727610547c 100644
--- a/libraries/base/mm/hdllib.cfg
+++ b/libraries/base/mm/hdllib.cfg
@@ -2,7 +2,6 @@ hdl_lib_name = mm
hdl_library_clause_name = mm_lib
hdl_lib_uses_synth = common
hdl_lib_uses_sim =
-
hdl_lib_technology =
synth_files =
@@ -17,3 +16,10 @@ test_bench_files =
tb/vhdl/mm_file.vhd
tb/vhdl/dummy_reg.vhd
tb/vhdl/tb_mm_file.vhd
+
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+
diff --git a/libraries/base/reorder/hdllib.cfg b/libraries/base/reorder/hdllib.cfg
index 6f2bd62554558481ee2562d085cf98b3a48dd1ed..0c87da8ed1ab6e745fd18e2ef75aba62aa56246d 100644
--- a/libraries/base/reorder/hdllib.cfg
+++ b/libraries/base/reorder/hdllib.cfg
@@ -2,13 +2,8 @@ hdl_lib_name = reorder
hdl_library_clause_name = reorder_lib
hdl_lib_uses_synth = common dp
hdl_lib_uses_sim = io_ddr tech_ddr
-
hdl_lib_technology =
-modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
-
-
synth_files =
src/vhdl/reorder_pkg.vhd
src/vhdl/reorder_retreive.vhd
@@ -37,7 +32,15 @@ test_bench_files =
tb/vhdl/tb_mmf_reorder_matrix.vhd
tb/vhdl/tb_mmf_reorder_row.vhd
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
+
modelsim_search_libraries =
altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver stratixiv_ver stratixiv_hssi_ver stratixiv_pcie_hip_ver
altera lpm sgate altera_mf altera_lnsim stratixiv stratixiv_hssi stratixiv_pcie_hip
+
+
+[quartus_project_file]
diff --git a/libraries/base/sens/hdllib.cfg b/libraries/base/sens/hdllib.cfg
index 773ff211ebbb22f593c8d765741be9fdde5d5b2f..fabc9009b10925c5c411ed7abc08bf2b14e6638a 100644
--- a/libraries/base/sens/hdllib.cfg
+++ b/libraries/base/sens/hdllib.cfg
@@ -2,7 +2,6 @@ hdl_lib_name = sens
hdl_library_clause_name = sens_lib
hdl_lib_uses_synth = common i2c
hdl_lib_uses_sim =
-
hdl_lib_technology =
synth_files =
@@ -12,3 +11,9 @@ synth_files =
test_bench_files =
tb/vhdl/tb_sens.vhd
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+
diff --git a/libraries/base/ss/hdllib.cfg b/libraries/base/ss/hdllib.cfg
index 3034a4bca1f56b2d565ab8b0b56b839911d68ffc..68aed757d36af830aee8f06ed47957aa1a9e8400 100644
--- a/libraries/base/ss/hdllib.cfg
+++ b/libraries/base/ss/hdllib.cfg
@@ -2,7 +2,6 @@ hdl_lib_name = ss
hdl_library_clause_name = ss_lib
hdl_lib_uses_synth = diag dp mm common
hdl_lib_uses_sim =
-
hdl_lib_technology =
synth_files =
@@ -19,3 +18,10 @@ test_bench_files =
tb/vhdl/tb_ss.vhd
tb/vhdl/tb_ss_wide.vhd
tb/vhdl/tb_tb_ss.vhd
+
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+
diff --git a/libraries/base/tst/hdllib.cfg b/libraries/base/tst/hdllib.cfg
index 8ade1d63d4b0be1906e9c17a444bdafb7a3ffaee..d043c47a1f8c7bfdd763aa3d176e4a49e115e158 100644
--- a/libraries/base/tst/hdllib.cfg
+++ b/libraries/base/tst/hdllib.cfg
@@ -2,7 +2,6 @@ hdl_lib_name = tst
hdl_library_clause_name = tst_lib
hdl_lib_uses_synth =
hdl_lib_uses_sim =
-
hdl_lib_technology =
synth_files =
@@ -10,3 +9,10 @@ synth_files =
src/vhdl/tst_input.vhd
test_bench_files =
+
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+
diff --git a/libraries/base/uth/hdllib.cfg b/libraries/base/uth/hdllib.cfg
index ac04bcfaeaf7221e16cd93fd6d3f3c7081de6ad7..3a67124dbbe63849370f96c57f0c964e94850248 100644
--- a/libraries/base/uth/hdllib.cfg
+++ b/libraries/base/uth/hdllib.cfg
@@ -2,7 +2,6 @@ hdl_lib_name = uth
hdl_library_clause_name = uth_lib
hdl_lib_uses_synth = common dp easics
hdl_lib_uses_sim =
-
hdl_lib_technology =
synth_files =
@@ -22,3 +21,10 @@ test_bench_files =
tb/vhdl/tb_tb_uth_dp_packet.vhd
tb/vhdl/tb_tb_uth_terminals.vhd
tb/vhdl/tb_tb_tb_uth_regression.vhd
+
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+
diff --git a/libraries/base/util/hdllib.cfg b/libraries/base/util/hdllib.cfg
index 6894bcbde3d90688b9d277d235b46abcc65cd37b..c998ad98bb894b09497687c22c1894255161e3fd 100644
--- a/libraries/base/util/hdllib.cfg
+++ b/libraries/base/util/hdllib.cfg
@@ -2,7 +2,6 @@ hdl_lib_name = util
hdl_library_clause_name = util_lib
hdl_lib_uses_synth = mm common common_mult technology
hdl_lib_uses_sim =
-
hdl_lib_technology =
synth_files =
@@ -12,3 +11,10 @@ synth_files =
test_bench_files =
tb/vhdl/tb_util_heater.vhd
+
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+
diff --git a/libraries/dsp/bf/designs/unb1_fn_bf/hdllib.cfg b/libraries/dsp/bf/designs/unb1_fn_bf/hdllib.cfg
index c165af84a0228139e3927c1fc1664cdc13e060f4..3e3089912f52d14e61f45f8acf5a1b7312e2c9a9 100644
--- a/libraries/dsp/bf/designs/unb1_fn_bf/hdllib.cfg
+++ b/libraries/dsp/bf/designs/unb1_fn_bf/hdllib.cfg
@@ -2,11 +2,8 @@ hdl_lib_name = unb1_fn_bf
hdl_library_clause_name = unb1_fn_bf_lib
hdl_lib_uses_synth = common technology mm i2c bf diag eth tech_tse unb1_board
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_stratixiv
-synth_top_level_entity =
-
synth_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_fn_bf/sopc_unb1_fn_bf.vhd
src/vhdl/mmm_unb1_fn_bf.vhd
@@ -16,8 +13,14 @@ synth_files =
test_bench_files =
tb/vhdl/tb_unb1_fn_bf.vhd
+
+[modelsim_project_file]
modelsim_copy_files = src/hex hex
+
+[quartus_project_file]
+synth_top_level_entity =
+
quartus_copy_files = quartus/sopc_unb1_fn_bf.sopc .
quartus_qsf_files =
diff --git a/libraries/dsp/bf/hdllib.cfg b/libraries/dsp/bf/hdllib.cfg
index 64c8a2e1d4a5ffb33fdc4ff6cbdba783cf0640a8..e971c985d7457e94e8fbc0374b99c099ffdb1f16 100644
--- a/libraries/dsp/bf/hdllib.cfg
+++ b/libraries/dsp/bf/hdllib.cfg
@@ -2,7 +2,6 @@ hdl_lib_name = bf
hdl_library_clause_name = bf_lib
hdl_lib_uses_synth = common common_mult technology mm dp st reorder
hdl_lib_uses_sim =
-
hdl_lib_technology =
synth_files =
@@ -13,3 +12,10 @@ synth_files =
test_bench_files =
tb/vhdl/tb_bf_unit.vhd
tb/vhdl/tb_bf.vhd
+
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+
diff --git a/libraries/dsp/correlator/designs/unb1_correlator/hdllib.cfg b/libraries/dsp/correlator/designs/unb1_correlator/hdllib.cfg
index 9e915ac1b2f4172b5288033f28ef95293a658105..b59f6067a5c293c60423f22128db77e1fa2a6e9a 100644
--- a/libraries/dsp/correlator/designs/unb1_correlator/hdllib.cfg
+++ b/libraries/dsp/correlator/designs/unb1_correlator/hdllib.cfg
@@ -2,14 +2,8 @@ hdl_lib_name = unb1_correlator
hdl_library_clause_name = unb1_correlator_lib
hdl_lib_uses_synth = common mm i2c unb1_board correlator
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_stratixiv
-synth_top_level_entity =
-
-quartus_copy_files =
- quartus/qsys_unb1_correlator.qsys .
-
synth_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_correlator/qsys_unb1_correlator/synthesis/qsys_unb1_correlator.v
src/vhdl/mmm_unb1_correlator.vhd
@@ -18,6 +12,16 @@ synth_files =
test_bench_files =
tb/vhdl/tb_unb1_correlator.vhd
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+synth_top_level_entity =
+
+quartus_copy_files =
+ quartus/qsys_unb1_correlator.qsys .
+
quartus_qsf_files =
$RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
diff --git a/libraries/dsp/correlator/hdllib.cfg b/libraries/dsp/correlator/hdllib.cfg
index 26c9466d5dba0b591740938d099433dd5528b0d4..62898ea521c9cee01dfdc63d58b6cccd08fc31d8 100644
--- a/libraries/dsp/correlator/hdllib.cfg
+++ b/libraries/dsp/correlator/hdllib.cfg
@@ -2,12 +2,8 @@ hdl_lib_name = correlator
hdl_library_clause_name = correlator_lib
hdl_lib_uses_synth = common common_mult technology dp diag
hdl_lib_uses_sim =
-
hdl_lib_technology =
-modelsim_copy_files =
- src/hex hex
-
synth_files =
src/vhdl/corr_carousel.vhd
src/vhdl/corr_unfolder.vhd
@@ -30,3 +26,10 @@ test_bench_files =
tb/vhdl/tb_correlator.vhd
+[modelsim_project_file]
+modelsim_copy_files =
+ src/hex hex
+
+
+[quartus_project_file]
+
diff --git a/libraries/dsp/fft/hdllib.cfg b/libraries/dsp/fft/hdllib.cfg
index 1679ba7306065400165d288672ecd99e5ce253fb..07f1da5f9f706fbbfa5c7667bfaeccf6937b689c 100644
--- a/libraries/dsp/fft/hdllib.cfg
+++ b/libraries/dsp/fft/hdllib.cfg
@@ -2,7 +2,6 @@ hdl_lib_name = fft
hdl_library_clause_name = fft_lib
hdl_lib_uses_synth = common mm dp diag rTwoSDF st
hdl_lib_uses_sim =
-
hdl_lib_technology =
synth_files =
@@ -29,3 +28,10 @@ test_bench_files =
tb/vhdl/tb_fft_wide_unit.vhd
tb/vhdl/tb_mmf_fft_r2.vhd
tb/vhdl/tb_mmf_fft_wide_unit.vhd
+
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+
diff --git a/libraries/dsp/filter/hdllib.cfg b/libraries/dsp/filter/hdllib.cfg
index 3d7b1bc16381c317c2e315798a3b53f8bab84895..05f00bc1701b13a85c41f0b619412314f66846ef 100644
--- a/libraries/dsp/filter/hdllib.cfg
+++ b/libraries/dsp/filter/hdllib.cfg
@@ -2,7 +2,6 @@ hdl_lib_name = filter
hdl_library_clause_name = filter_lib
hdl_lib_uses_synth = common common_mult technology dp diag
hdl_lib_uses_sim =
-
hdl_lib_technology =
synth_files =
@@ -16,4 +15,10 @@ test_bench_files =
tb/vhdl/tb_fil_ppf_single.vhd
tb/vhdl/tb_fil_ppf_wide.vhd
+
+[modelsim_project_file]
modelsim_copy_files = src/hex hex
+
+
+[quartus_project_file]
+
diff --git a/libraries/dsp/rTwoSDF/hdllib.cfg b/libraries/dsp/rTwoSDF/hdllib.cfg
index a53a8a882458d31ef0ff2488531e9edfb5d2b7aa..e8c3fbef0bbd907d59314e1483aa0876acdd0cf9 100644
--- a/libraries/dsp/rTwoSDF/hdllib.cfg
+++ b/libraries/dsp/rTwoSDF/hdllib.cfg
@@ -2,7 +2,6 @@ hdl_lib_name = rTwoSDF
hdl_library_clause_name = rTwoSDF_lib
hdl_lib_uses_synth = common common_mult technology
hdl_lib_uses_sim =
-
hdl_lib_technology =
synth_files =
@@ -21,12 +20,9 @@ test_bench_files =
tb/vhdl/tb_tb_rTwoSDF.vhd
tb/vhdl/tb_rTwoOrder.vhd
-modelsim_copy_files = tb/data data
-
-
-
-
-
+[modelsim_project_file]
+modelsim_copy_files = tb/data data
+[quartus_project_file]
diff --git a/libraries/dsp/st/hdllib.cfg b/libraries/dsp/st/hdllib.cfg
index 2bc22dbf0518f3318ea4ec26eb99e011cdfe88c7..da029b594799a82d0751b9f92c07c7aff3eab9a0 100644
--- a/libraries/dsp/st/hdllib.cfg
+++ b/libraries/dsp/st/hdllib.cfg
@@ -2,7 +2,6 @@ hdl_lib_name = st
hdl_library_clause_name = st_lib
hdl_lib_uses_synth = common common_mult technology mm dp diag
hdl_lib_uses_sim =
-
hdl_lib_technology =
synth_files =
@@ -17,3 +16,9 @@ test_bench_files =
tb/vhdl/tb_st_calc.vhd
tb/vhdl/tb_mmf_st_sst.vhd
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+
diff --git a/libraries/dsp/wpfb/hdllib.cfg b/libraries/dsp/wpfb/hdllib.cfg
index 5eccb67244b03c7192cab7c54c46d082742ac00a..5ea9f5187b23eebf64b0be0185ebd8bcd4ae35d1 100644
--- a/libraries/dsp/wpfb/hdllib.cfg
+++ b/libraries/dsp/wpfb/hdllib.cfg
@@ -2,7 +2,6 @@ hdl_lib_name = wpfb
hdl_library_clause_name = wpfb_lib
hdl_lib_uses_synth = common mm diag dp rTwoSDF st fft filter
hdl_lib_uses_sim =
-
hdl_lib_technology =
synth_files =
@@ -13,6 +12,12 @@ test_bench_files =
tb/vhdl/tb_wpfb_unit.vhd
tb/vhdl/tb_mmf_wpfb_unit.vhd
+
+[modelsim_project_file]
modelsim_copy_files =
modelsim/wave_tb_mmf_wpfb_unit.do .
../filter/src/hex data
+
+
+[quartus_project_file]
+
diff --git a/libraries/external/easics/hdllib.cfg b/libraries/external/easics/hdllib.cfg
index 397ef56c6f0f7bb2f53361553938adb14bc1d94b..1ced0072362a76e678e06116e4d046867965d226 100644
--- a/libraries/external/easics/hdllib.cfg
+++ b/libraries/external/easics/hdllib.cfg
@@ -2,7 +2,6 @@ hdl_lib_name = easics
hdl_library_clause_name = easics_lib
hdl_lib_uses_synth =
hdl_lib_uses_sim =
-
hdl_lib_technology =
synth_files =
@@ -62,4 +61,12 @@ synth_files =
src/vhdl/RAD_CRC20_D20.vhd
src/vhdl/RAD_CRC16_D16.vhd
src/vhdl/RAD_CRC18_D18.vhd
+
test_bench_files =
+
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+
diff --git a/libraries/external/numonyx_m25p128/hdllib.cfg b/libraries/external/numonyx_m25p128/hdllib.cfg
index 3a9dc46d77de521706d806c43614d0eb2f76ccc2..2f27bb34e17350980919b8388501b81c463ee506 100644
--- a/libraries/external/numonyx_m25p128/hdllib.cfg
+++ b/libraries/external/numonyx_m25p128/hdllib.cfg
@@ -2,7 +2,6 @@ hdl_lib_name = numonyx_m25p128
hdl_library_clause_name = numonyx_m25p128_lib
hdl_lib_uses_synth =
hdl_lib_uses_sim =
-
hdl_lib_technology =
synth_files =
@@ -16,3 +15,10 @@ test_bench_files =
NU_M25P128_V10/lib/TimingData.vhd
NU_M25P128_V10/lib/MemoryLib.vhd
NU_M25P128_V10/code/M25P128.vhd
+
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+
diff --git a/libraries/io/aduh/hdllib.cfg b/libraries/io/aduh/hdllib.cfg
index 334d608df22313cbbb6c05bfd05545a05e2ca215..d2e7e76aea5adf01c94f1c28d09c484fa7419f49 100644
--- a/libraries/io/aduh/hdllib.cfg
+++ b/libraries/io/aduh/hdllib.cfg
@@ -2,7 +2,6 @@ hdl_lib_name = aduh
hdl_library_clause_name = aduh_lib
hdl_lib_uses_synth = common common_mult dp diag i2c technology
hdl_lib_uses_sim =
-
hdl_lib_technology =
synth_files =
@@ -38,3 +37,9 @@ test_bench_files =
tb/vhdl/tb_tb_lvdsh_dd_phs4.vhd
tb/vhdl/tb_tb_lvdsh_dd_wb4.vhd
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+
diff --git a/libraries/io/ddr/hdllib.cfg b/libraries/io/ddr/hdllib.cfg
index 888053760366fd20386062fb93a968d311a4e2f3..398a370c753f6ab4486a6c4e8fc35c08ac48f93a 100644
--- a/libraries/io/ddr/hdllib.cfg
+++ b/libraries/io/ddr/hdllib.cfg
@@ -2,13 +2,8 @@ hdl_lib_name = io_ddr
hdl_library_clause_name = io_ddr_lib
hdl_lib_uses_synth = technology tech_ddr tech_ddr3 common dp diag diagnostics
hdl_lib_uses_sim =
-
hdl_lib_technology =
-modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
- $RADIOHDL/libraries/technology/ip_arria10/ddr4_4g_1600/copy_hex_files.tcl
-
synth_files =
src/vhdl/io_ddr_driver_flush_ctrl.vhd
src/vhdl/io_ddr_driver.vhd
@@ -22,3 +17,11 @@ test_bench_files =
tb/vhdl/tb_io_ddr.vhd
tb/vhdl/tb_tb_io_ddr.vhd
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
+ $RADIOHDL/libraries/technology/ip_arria10/ddr4_4g_1600/copy_hex_files.tcl
+
+
+[quartus_project_file]
diff --git a/libraries/io/ddr3/hdllib.cfg b/libraries/io/ddr3/hdllib.cfg
index 63d4550dd689cf3c9132aa163e4199440db1ba3f..5c8f38d2de5d777906cffdb76ff5eae9b4e8caa8 100644
--- a/libraries/io/ddr3/hdllib.cfg
+++ b/libraries/io/ddr3/hdllib.cfg
@@ -2,13 +2,8 @@ hdl_lib_name = ddr3
hdl_library_clause_name = ddr3_lib
hdl_lib_uses_synth = common dp diag diagnostics ss tech_ddr
hdl_lib_uses_sim =
-
hdl_lib_technology =
-modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
- #$RADIOHDL/libraries/io/ddr3/src/tcl/compile_ip.tcl
-
synth_files =
src/vhdl/ddr3_pkg.vhd
src/vhdl/ddr3_reg.vhd
@@ -27,8 +22,17 @@ test_bench_files =
tb/vhdl/tb_seq_ddr3.vhd
tb/vhdl/tb_ddr3_transpose.vhd
+
+[modelsim_project_file]
modelsim_copy_files =
$RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master/ip_stratixiv_ddr3_uphy_4g_800_master_s0_AC_ROM.hex .
$RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master/ip_stratixiv_ddr3_uphy_4g_800_master_s0_inst_ROM.hex .
$RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master/ip_stratixiv_ddr3_uphy_4g_800_master_s0_sequencer_mem.hex .
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
+ #$RADIOHDL/libraries/io/ddr3/src/tcl/compile_ip.tcl
+
+
+[quartus_project_file]
+
diff --git a/libraries/io/epcs/hdllib.cfg b/libraries/io/epcs/hdllib.cfg
index ba8f956303805601ad86e407ffef5155f13c1022..d493969fba56264cd7c3886cea886661ee0b2a39 100644
--- a/libraries/io/epcs/hdllib.cfg
+++ b/libraries/io/epcs/hdllib.cfg
@@ -2,7 +2,6 @@ hdl_lib_name = epcs
hdl_library_clause_name = epcs_lib
hdl_lib_uses_synth = common dp tech_flash
hdl_lib_uses_sim =
-
hdl_lib_technology =
synth_files =
@@ -11,3 +10,10 @@ synth_files =
test_bench_files =
tb/vhdl/tb_mms_epcs.vhd
+
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+
diff --git a/libraries/io/eth/hdllib.cfg b/libraries/io/eth/hdllib.cfg
index 5945c7cf470c3713e55da6af12b0b87d7a379421..b363c0a31a2bf780c579cec2081824db01c2cd9b 100644
--- a/libraries/io/eth/hdllib.cfg
+++ b/libraries/io/eth/hdllib.cfg
@@ -2,7 +2,6 @@ hdl_lib_name = eth
hdl_library_clause_name = eth_lib
hdl_lib_uses_synth = dp common tech_tse
hdl_lib_uses_sim =
-
hdl_lib_technology =
synth_files =
@@ -33,3 +32,8 @@ test_bench_files =
tb/vhdl/tb_eth_ihl_to_20.vhd
tb/vhdl/tb_tb_tb_eth_regression.vhd
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
diff --git a/libraries/io/fpga_sense/hdllib.cfg b/libraries/io/fpga_sense/hdllib.cfg
index c40c0ac1e105d3688b808cc981820c35840cf2b8..f922790204903e075514d83bb6823b9dd04e0cba 100644
--- a/libraries/io/fpga_sense/hdllib.cfg
+++ b/libraries/io/fpga_sense/hdllib.cfg
@@ -2,7 +2,6 @@ hdl_lib_name = fpga_sense
hdl_library_clause_name = fpga_sense_lib
hdl_lib_uses_synth = common technology tech_fpga_temp_sens tech_fpga_voltage_sens
hdl_lib_uses_sim =
-
hdl_lib_technology =
synth_files =
@@ -10,3 +9,9 @@ synth_files =
test_bench_files =
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+
diff --git a/libraries/io/i2c/hdllib.cfg b/libraries/io/i2c/hdllib.cfg
index 9c55ec5d8022d676b5f1a9daefcfddf79da73c9e..b48f36ef81747a103b9276e4e5671c55e9e3853d 100644
--- a/libraries/io/i2c/hdllib.cfg
+++ b/libraries/io/i2c/hdllib.cfg
@@ -2,7 +2,6 @@ hdl_lib_name = i2c
hdl_library_clause_name = i2c_lib
hdl_lib_uses_synth = common
hdl_lib_uses_sim =
-
hdl_lib_technology =
synth_files =
@@ -45,5 +44,10 @@ test_bench_files =
tb/vhdl/tb_i2c_commander.vhd
tb/vhdl/tb_tb_i2c_commander.vhd
+
+[modelsim_project_file]
modelsim_copy_files =
tb/data data
+
+
+[quartus_project_file]
diff --git a/libraries/io/mac_10g/hdllib.cfg b/libraries/io/mac_10g/hdllib.cfg
index 7b180d825bcd3b41b488532e44bfd738f5f2afa8..0ab81e2fc0659150f0468ef7bc8c3828b6188669 100644
--- a/libraries/io/mac_10g/hdllib.cfg
+++ b/libraries/io/mac_10g/hdllib.cfg
@@ -2,10 +2,16 @@ hdl_lib_name = io_mac_10g
hdl_library_clause_name = io_mac_10g_lib
hdl_lib_uses_synth = technology tech_mac_10g common dp
hdl_lib_uses_sim =
-
hdl_lib_technology =
synth_files =
io_mac_10g.vhd
test_bench_files =
+
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+
diff --git a/libraries/io/mdio/hdllib.cfg b/libraries/io/mdio/hdllib.cfg
index d3f07f82bca5a04f30cc9ad79caf494d08bbb778..378f3569b4467b4ebec8da18f955e31b8e9cc164 100644
--- a/libraries/io/mdio/hdllib.cfg
+++ b/libraries/io/mdio/hdllib.cfg
@@ -2,7 +2,6 @@ hdl_lib_name = mdio
hdl_library_clause_name = mdio_lib
hdl_lib_uses_synth = common mm
hdl_lib_uses_sim =
-
hdl_lib_technology =
synth_files =
@@ -21,3 +20,10 @@ test_bench_files =
tb/vhdl/tb_mdio_phy.vhd
tb/vhdl/tb_mdio_phy_reg.vhd
tb/vhdl/tb_mdio_phy_ctlr.vhd
+
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+
diff --git a/libraries/io/ppsh/hdllib.cfg b/libraries/io/ppsh/hdllib.cfg
index 2c71bdfe5d4384c4be3bca5173b1578e2cea34b7..6ce56a78ff699532e333fd06e2382e653a681533 100644
--- a/libraries/io/ppsh/hdllib.cfg
+++ b/libraries/io/ppsh/hdllib.cfg
@@ -2,7 +2,6 @@ hdl_lib_name = ppsh
hdl_library_clause_name = ppsh_lib
hdl_lib_uses_synth = common
hdl_lib_uses_sim =
-
hdl_lib_technology =
synth_files =
@@ -14,3 +13,10 @@ synth_files =
test_bench_files =
tb/vhdl/tb_ppsh.vhd
tb/vhdl/tb_mms_ppsh.vhd
+
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+
diff --git a/libraries/io/remu/hdllib.cfg b/libraries/io/remu/hdllib.cfg
index f498233824edc7a9080dd9a195c1b92a1b517385..213f6331ae8c26d1c08a6490812f0ca07b2004bf 100644
--- a/libraries/io/remu/hdllib.cfg
+++ b/libraries/io/remu/hdllib.cfg
@@ -2,7 +2,6 @@ hdl_lib_name = remu
hdl_library_clause_name = remu_lib
hdl_lib_uses_synth = common tech_flash
hdl_lib_uses_sim =
-
hdl_lib_technology =
synth_files =
@@ -10,3 +9,10 @@ synth_files =
src/vhdl/mms_remu.vhd
test_bench_files =
+
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+
diff --git a/libraries/io/tr_10GbE/hdllib.cfg b/libraries/io/tr_10GbE/hdllib.cfg
index 6ca11e99543d18bfc16e9ee8b0b5dac0f6add2a2..7ec28c31fd53e7de737459c82cbac598e256b3c6 100644
--- a/libraries/io/tr_10GbE/hdllib.cfg
+++ b/libraries/io/tr_10GbE/hdllib.cfg
@@ -2,7 +2,6 @@ hdl_lib_name = tr_10GbE
hdl_library_clause_name = tr_10GbE_lib
hdl_lib_uses_synth = common technology tech_mac_10g tech_eth_10g tr_xaui dp diag diagnostics
hdl_lib_uses_sim =
-
hdl_lib_technology =
synth_files =
@@ -12,3 +11,9 @@ test_bench_files =
tb/vhdl/tb_tr_10GbE.vhd
tb/vhdl/tb_tb_tr_10GbE.vhd
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+
diff --git a/libraries/io/tr_nonbonded/hdllib.cfg b/libraries/io/tr_nonbonded/hdllib.cfg
index f7ae0a2638ec5d207c5da38f174dbd7b4bf9b3fc..d04f8a3bb4f35dbed52213eb9baeac73b87d1df4 100644
--- a/libraries/io/tr_nonbonded/hdllib.cfg
+++ b/libraries/io/tr_nonbonded/hdllib.cfg
@@ -2,7 +2,6 @@ hdl_lib_name = tr_nonbonded
hdl_library_clause_name = tr_nonbonded_lib
hdl_lib_uses_synth = common dp diag diagnostics tech_transceiver
hdl_lib_uses_sim =
-
hdl_lib_technology =
synth_files =
@@ -13,3 +12,10 @@ synth_files =
test_bench_files =
tb/vhdl/tb_tr_nonbonded.vhd
tb/vhdl/tb_tb_tr_nonbonded.vhd
+
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+
diff --git a/libraries/io/tr_xaui/hdllib.cfg b/libraries/io/tr_xaui/hdllib.cfg
index bc11236d475a3e6ddc1632d7ff12e09d1ab58a7f..7377a503ee80ccef1ab786bc1243144576089431 100644
--- a/libraries/io/tr_xaui/hdllib.cfg
+++ b/libraries/io/tr_xaui/hdllib.cfg
@@ -2,14 +2,12 @@ hdl_lib_name = tr_xaui
hdl_library_clause_name = tr_xaui_lib
hdl_lib_uses_synth = common dp mdio diagnostics tech_xaui
hdl_lib_uses_sim =
-
hdl_lib_technology =
synth_files =
src/vhdl/tr_xaui_deframer.vhd
src/vhdl/tr_xaui_framer.vhd
src/vhdl/tr_xaui_mdio.vhd
-
src/vhdl/tr_xaui.vhd
src/vhdl/mms_tr_xaui.vhd
@@ -18,3 +16,10 @@ test_bench_files =
tb/vhdl/tb_tr_xaui_framer.vhd
tb/vhdl/tb_tr_xaui.vhd
tb/vhdl/tb_tb_tr_xaui.vhd
+
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+
diff --git a/libraries/technology/10gbase_r/hdllib.cfg b/libraries/technology/10gbase_r/hdllib.cfg
index 56fd81f75bc62f5fcc746f9405670191c919b5f9..9d9de8bd731653332d672145d1b8dc9ae219c70f 100644
--- a/libraries/technology/10gbase_r/hdllib.cfg
+++ b/libraries/technology/10gbase_r/hdllib.cfg
@@ -1,33 +1,32 @@
hdl_lib_name = tech_10gbase_r
hdl_library_clause_name = tech_10gbase_r_lib
hdl_lib_uses_synth = technology
- tech_pll
- ip_arria10_phy_10gbase_r
- ip_arria10_phy_10gbase_r_4
- ip_arria10_phy_10gbase_r_12
- ip_arria10_phy_10gbase_r_24
- ip_arria10_phy_10gbase_r_48
- ip_arria10_transceiver_pll_10g
- ip_arria10_transceiver_reset_controller_1
- ip_arria10_transceiver_reset_controller_4
- ip_arria10_transceiver_reset_controller_12
- ip_arria10_transceiver_reset_controller_24
- ip_arria10_transceiver_reset_controller_48
- ip_arria10_e3sge3_phy_10gbase_r
- ip_arria10_e3sge3_phy_10gbase_r_4
- ip_arria10_e3sge3_phy_10gbase_r_12
- ip_arria10_e3sge3_phy_10gbase_r_24
- ip_arria10_e3sge3_phy_10gbase_r_48
- ip_arria10_e3sge3_transceiver_pll_10g
- ip_arria10_e3sge3_transceiver_reset_controller_1
- ip_arria10_e3sge3_transceiver_reset_controller_4
- ip_arria10_e3sge3_transceiver_reset_controller_12
- ip_arria10_e3sge3_transceiver_reset_controller_24
- ip_arria10_e3sge3_transceiver_reset_controller_48
- tech_transceiver
- common
+ tech_pll
+ ip_arria10_phy_10gbase_r
+ ip_arria10_phy_10gbase_r_4
+ ip_arria10_phy_10gbase_r_12
+ ip_arria10_phy_10gbase_r_24
+ ip_arria10_phy_10gbase_r_48
+ ip_arria10_transceiver_pll_10g
+ ip_arria10_transceiver_reset_controller_1
+ ip_arria10_transceiver_reset_controller_4
+ ip_arria10_transceiver_reset_controller_12
+ ip_arria10_transceiver_reset_controller_24
+ ip_arria10_transceiver_reset_controller_48
+ ip_arria10_e3sge3_phy_10gbase_r
+ ip_arria10_e3sge3_phy_10gbase_r_4
+ ip_arria10_e3sge3_phy_10gbase_r_12
+ ip_arria10_e3sge3_phy_10gbase_r_24
+ ip_arria10_e3sge3_phy_10gbase_r_48
+ ip_arria10_e3sge3_transceiver_pll_10g
+ ip_arria10_e3sge3_transceiver_reset_controller_1
+ ip_arria10_e3sge3_transceiver_reset_controller_4
+ ip_arria10_e3sge3_transceiver_reset_controller_12
+ ip_arria10_e3sge3_transceiver_reset_controller_24
+ ip_arria10_e3sge3_transceiver_reset_controller_48
+ tech_transceiver
+ common
hdl_lib_uses_sim =
-
hdl_lib_technology =
synth_files =
@@ -40,3 +39,9 @@ synth_files =
test_bench_files =
tb_tech_10gbase_r.vhd
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+
diff --git a/libraries/technology/clkbuf/hdllib.cfg b/libraries/technology/clkbuf/hdllib.cfg
index e576fef06a3b61e05ac86203bd58783e500c5287..eb6cccdd3dd9361bef0e719fdfa02c682994d06a 100644
--- a/libraries/technology/clkbuf/hdllib.cfg
+++ b/libraries/technology/clkbuf/hdllib.cfg
@@ -2,7 +2,6 @@ hdl_lib_name = tech_clkbuf
hdl_library_clause_name = tech_clkbuf_lib
hdl_lib_uses_synth = technology ip_arria10_clkbuf_global ip_arria10_e3sge3_clkbuf_global common
hdl_lib_uses_sim =
-
hdl_lib_technology =
synth_files =
@@ -10,3 +9,10 @@ synth_files =
tech_clkbuf.vhd
test_bench_files =
+
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+
diff --git a/libraries/technology/ddr/hdllib.cfg b/libraries/technology/ddr/hdllib.cfg
index 511b86ec53236b8c3db67408b2cd0c86aa3d4443..7823158935fe8f62fa6ba91d4eb200e99bcc5d3f 100644
--- a/libraries/technology/ddr/hdllib.cfg
+++ b/libraries/technology/ddr/hdllib.cfg
@@ -15,7 +15,6 @@ hdl_lib_uses_synth = ip_stratixiv_ddr3_uphy_4g_800_master
common
hdl_lib_uses_sim = ip_stratixiv_ddr3_mem_model
ip_arria10_ddr4_mem_model_141
-
hdl_lib_technology =
synth_files =
@@ -31,3 +30,9 @@ test_bench_files =
tech_ddr_mem_model_component_pkg.vhd
tech_ddr_mem_model.vhd
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+
diff --git a/libraries/technology/eth_10g/hdllib.cfg b/libraries/technology/eth_10g/hdllib.cfg
index 998ad42426a8610271c784d59950f11eb4878f19..4097bc27e211f816ff1ac9223551b0b6438c2ea8 100644
--- a/libraries/technology/eth_10g/hdllib.cfg
+++ b/libraries/technology/eth_10g/hdllib.cfg
@@ -2,7 +2,6 @@ hdl_lib_name = tech_eth_10g
hdl_library_clause_name = tech_eth_10g_lib
hdl_lib_uses_synth = technology tech_pll tech_mac_10g tech_10gbase_r tech_xaui common dp
hdl_lib_uses_sim =
-
hdl_lib_technology =
synth_files =
@@ -17,3 +16,9 @@ test_bench_files =
tb_tech_eth_10g_ppm.vhd
tb_tb_tech_eth_10g.vhd
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+
diff --git a/libraries/technology/fifo/hdllib.cfg b/libraries/technology/fifo/hdllib.cfg
index 358adc9cdaed0f6cde6810976d824d212e812f59..cd2f4e75a38d18a87eacc1984842991506a351b4 100644
--- a/libraries/technology/fifo/hdllib.cfg
+++ b/libraries/technology/fifo/hdllib.cfg
@@ -2,7 +2,6 @@ hdl_lib_name = tech_fifo
hdl_library_clause_name = tech_fifo_lib
hdl_lib_uses_synth = technology ip_stratixiv_fifo ip_arria10_fifo ip_arria10_e3sge3_fifo
hdl_lib_uses_sim =
-
hdl_lib_technology =
synth_files =
@@ -12,3 +11,9 @@ synth_files =
tech_fifo_dc_mixed_widths.vhd
test_bench_files =
+
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
diff --git a/libraries/technology/flash/hdllib.cfg b/libraries/technology/flash/hdllib.cfg
index 7f549d0a61ec5dad2c28e3074d918c8bff080138..3d9f76f1bc3f9453d57e6ea64a4b9bb4eb1d7abc 100644
--- a/libraries/technology/flash/hdllib.cfg
+++ b/libraries/technology/flash/hdllib.cfg
@@ -7,7 +7,6 @@ hdl_lib_uses_synth = technology
ip_arria10_e3sge3_asmi_parallel
ip_arria10_e3sge3_remote_update
hdl_lib_uses_sim =
-
hdl_lib_technology =
synth_files =
@@ -16,3 +15,10 @@ synth_files =
tech_flash_remote_update.vhd
test_bench_files =
+
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+
diff --git a/libraries/technology/fpga_temp_sens/hdllib.cfg b/libraries/technology/fpga_temp_sens/hdllib.cfg
index f52490785a5fa46e87aa0916183876de838cd47e..cbb8929e5c291c36c7b18974303ca59a16255f28 100644
--- a/libraries/technology/fpga_temp_sens/hdllib.cfg
+++ b/libraries/technology/fpga_temp_sens/hdllib.cfg
@@ -2,7 +2,6 @@ hdl_lib_name = tech_fpga_temp_sens
hdl_library_clause_name = tech_fpga_temp_sens_lib
hdl_lib_uses_synth = technology common ip_arria10_temp_sense ip_arria10_e3sge3_temp_sense
hdl_lib_uses_sim =
-
hdl_lib_technology =
synth_files =
@@ -10,3 +9,10 @@ synth_files =
tech_fpga_temp_sens.vhd
test_bench_files =
+
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+
diff --git a/libraries/technology/fpga_voltage_sens/hdllib.cfg b/libraries/technology/fpga_voltage_sens/hdllib.cfg
index 9793a24998340a3fc3c873b9dfcc4a568c0ae05f..08112f7364deee4ad91b5dcb54482b0ca36e1fae 100644
--- a/libraries/technology/fpga_voltage_sens/hdllib.cfg
+++ b/libraries/technology/fpga_voltage_sens/hdllib.cfg
@@ -2,7 +2,6 @@ hdl_lib_name = tech_fpga_voltage_sens
hdl_library_clause_name = tech_fpga_voltage_sens_lib
hdl_lib_uses_synth = technology common ip_arria10_voltage_sense ip_arria10_e3sge3_voltage_sense
hdl_lib_uses_sim =
-
hdl_lib_technology =
synth_files =
@@ -10,3 +9,10 @@ synth_files =
tech_fpga_voltage_sens.vhd
test_bench_files =
+
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+
diff --git a/libraries/technology/fractional_pll/hdllib.cfg b/libraries/technology/fractional_pll/hdllib.cfg
index c5e72e6023d8e2bcb81e8903ea97dde9ec1cf302..e9cc301c1728e388933cc770a199ea29bcd21b54 100644
--- a/libraries/technology/fractional_pll/hdllib.cfg
+++ b/libraries/technology/fractional_pll/hdllib.cfg
@@ -2,7 +2,6 @@ hdl_lib_name = tech_fractional_pll
hdl_library_clause_name = tech_fractional_pll_lib
hdl_lib_uses_synth = technology ip_arria10_fractional_pll_clk200 ip_arria10_fractional_pll_clk125 ip_arria10_e3sge3_fractional_pll_clk200 ip_arria10_e3sge3_fractional_pll_clk125 common
hdl_lib_uses_sim =
-
hdl_lib_technology =
synth_files =
@@ -11,3 +10,10 @@ synth_files =
tech_fractional_pll_clk125.vhd
test_bench_files =
+
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+
diff --git a/libraries/technology/hdllib.cfg b/libraries/technology/hdllib.cfg
index 98623b6f429630a13376fd5552e8d6e6623801f7..b63e66f46f390914f6e2808640c76a737d92a7c5 100644
--- a/libraries/technology/hdllib.cfg
+++ b/libraries/technology/hdllib.cfg
@@ -2,7 +2,6 @@ hdl_lib_name = technology
hdl_library_clause_name = technology_lib
hdl_lib_uses_synth =
hdl_lib_uses_sim =
-
hdl_lib_technology =
synth_files =
@@ -10,3 +9,10 @@ synth_files =
technology_select_pkg.vhd
test_bench_files =
+
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+
diff --git a/libraries/technology/iobuf/hdllib.cfg b/libraries/technology/iobuf/hdllib.cfg
index 410b543a388dad6bf907c9311e56660e6442096d..53d656dc9d56ae42ae6b22c7d976ad221f860631 100644
--- a/libraries/technology/iobuf/hdllib.cfg
+++ b/libraries/technology/iobuf/hdllib.cfg
@@ -2,7 +2,6 @@ hdl_lib_name = tech_iobuf
hdl_library_clause_name = tech_iobuf_lib
hdl_lib_uses_synth = technology ip_stratixiv_ddio ip_arria10_ddio ip_arria10_e3sge3_ddio
hdl_lib_uses_sim =
-
hdl_lib_technology =
synth_files =
@@ -11,3 +10,10 @@ synth_files =
tech_iobuf_ddio_out.vhd
test_bench_files =
+
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+
diff --git a/libraries/technology/ip_arria10/clkbuf_global/hdllib.cfg b/libraries/technology/ip_arria10/clkbuf_global/hdllib.cfg
index 0d8942d691bdff740df8f7f2a8c1613a7a4aa0ce..dab29a0357d53ad33059e86077df9dfb345b093e 100644
--- a/libraries/technology/ip_arria10/clkbuf_global/hdllib.cfg
+++ b/libraries/technology/ip_arria10/clkbuf_global/hdllib.cfg
@@ -2,15 +2,18 @@ hdl_lib_name = ip_arria10_clkbuf_global
hdl_library_clause_name = ip_arria10_clkbuf_global_altclkctrl_150
hdl_lib_uses_synth =
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_arria10
-modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10/clkbuf_global/compile_ip.tcl
-
synth_files =
test_bench_files =
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10/clkbuf_global/compile_ip.tcl
+
+
+[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_clkbuf_global.qip
diff --git a/libraries/technology/ip_arria10/complex_mult/hdllib.cfg b/libraries/technology/ip_arria10/complex_mult/hdllib.cfg
index d6aaa13158b29a774e47bf257b8efffcc7e8d5a3..8e7b0c0c0b6d2db8a63cabb5fd9b856198f82366 100644
--- a/libraries/technology/ip_arria10/complex_mult/hdllib.cfg
+++ b/libraries/technology/ip_arria10/complex_mult/hdllib.cfg
@@ -2,15 +2,18 @@ hdl_lib_name = ip_arria10_complex_mult
hdl_library_clause_name = ip_arria10_complex_mult_altmult_complex_150
hdl_lib_uses_synth =
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_arria10
-modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10/complex_mult/compile_ip.tcl
-
synth_files =
test_bench_files =
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10/complex_mult/compile_ip.tcl
+
+
+[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_complex_mult.qip
diff --git a/libraries/technology/ip_arria10/complex_mult_rtl/hdllib.cfg b/libraries/technology/ip_arria10/complex_mult_rtl/hdllib.cfg
index e001e9caee5365c4b340ed56e617043bae7005f8..4e99d3d331f7840ac00ea149f7d3f4461afc5cc9 100644
--- a/libraries/technology/ip_arria10/complex_mult_rtl/hdllib.cfg
+++ b/libraries/technology/ip_arria10/complex_mult_rtl/hdllib.cfg
@@ -2,10 +2,16 @@ hdl_lib_name = ip_arria10_complex_mult_rtl
hdl_library_clause_name = ip_arria10_complex_mult_rtl_lib
hdl_lib_uses_synth =
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_arria10
synth_files =
ip_arria10_complex_mult_rtl.vhd
test_bench_files =
+
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+
diff --git a/libraries/technology/ip_arria10/ddio/hdllib.cfg b/libraries/technology/ip_arria10/ddio/hdllib.cfg
index 3e0dcb7f17bc45bd3862a5ecce57ba70e53cd541..f3881529baccfb2ae8dd6fca916d93d8f0816464 100644
--- a/libraries/technology/ip_arria10/ddio/hdllib.cfg
+++ b/libraries/technology/ip_arria10/ddio/hdllib.cfg
@@ -2,18 +2,21 @@ hdl_lib_name = ip_arria10_ddio
hdl_library_clause_name = ip_arria10_ddio_lib
hdl_lib_uses_synth = technology
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_arria10
-modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10/ddio/compile_ip.tcl
-
synth_files =
ip_arria10_ddio_in.vhd
ip_arria10_ddio_out.vhd
test_bench_files =
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10/ddio/compile_ip.tcl
+
+
+[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_ddio_in_1.qip
generated/ip_arria10_ddio_out_1.qip
diff --git a/libraries/technology/ip_arria10/ddr4_4g_1600/hdllib.cfg b/libraries/technology/ip_arria10/ddr4_4g_1600/hdllib.cfg
index bbd11c76bd3ae99be2a01e533595eadfc1051dc4..df28a123cd9738269d9269e6a85ba0bbaf8ca98e 100644
--- a/libraries/technology/ip_arria10/ddr4_4g_1600/hdllib.cfg
+++ b/libraries/technology/ip_arria10/ddr4_4g_1600/hdllib.cfg
@@ -2,15 +2,18 @@ hdl_lib_name = ip_arria10_ddr4_4g_1600
hdl_library_clause_name = ip_arria10_ddr4_4g_1600_altera_emif_150
hdl_lib_uses_synth =
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_arria10
-modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10/ddr4_4g_1600/compile_ip.tcl
-
synth_files =
test_bench_files =
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10/ddr4_4g_1600/compile_ip.tcl
+
+
+[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_ddr4_4g_1600.qip
diff --git a/libraries/technology/ip_arria10/ddr4_4g_2000/hdllib.cfg b/libraries/technology/ip_arria10/ddr4_4g_2000/hdllib.cfg
index c9c12814e63d7b9e334d62da04e703eb47aa929d..b11af9b2177265a5a6f99679b205428d9b5eb2e2 100644
--- a/libraries/technology/ip_arria10/ddr4_4g_2000/hdllib.cfg
+++ b/libraries/technology/ip_arria10/ddr4_4g_2000/hdllib.cfg
@@ -2,15 +2,18 @@ hdl_lib_name = ip_arria10_ddr4_4g_2000
hdl_library_clause_name = ip_arria10_ddr4_4g_2000_altera_emif_150
hdl_lib_uses_synth =
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_arria10
-modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10/ddr4_4g_2000/compile_ip.tcl
-
synth_files =
test_bench_files =
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10/ddr4_4g_2000/compile_ip.tcl
+
+
+[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_ddr4_4g_2000.qip
diff --git a/libraries/technology/ip_arria10/ddr4_8g_2400/hdllib.cfg b/libraries/technology/ip_arria10/ddr4_8g_2400/hdllib.cfg
index 1853b8c23f2f08808de6a65f0f14b64da3921e52..9a802df0eebc0d0a45854ed9c157a6a8be9d28b1 100644
--- a/libraries/technology/ip_arria10/ddr4_8g_2400/hdllib.cfg
+++ b/libraries/technology/ip_arria10/ddr4_8g_2400/hdllib.cfg
@@ -2,15 +2,18 @@ hdl_lib_name = ip_arria10_ddr4_8g_2400
hdl_library_clause_name = ip_arria10_ddr4_8g_2400_altera_emif_150
hdl_lib_uses_synth =
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_arria10
-modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10/ddr4_8g_2400/compile_ip.tcl
-
synth_files =
test_bench_files =
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10/ddr4_8g_2400/compile_ip.tcl
+
+
+[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_ddr4_8g_2400.qip
diff --git a/libraries/technology/ip_arria10/ddr4_mem_model_141/hdllib.cfg b/libraries/technology/ip_arria10/ddr4_mem_model_141/hdllib.cfg
index 5bc56a3815ac0104e3599c6bb8001b157f130836..f1011b2cc602bfe449c7918c929c023720526394 100644
--- a/libraries/technology/ip_arria10/ddr4_mem_model_141/hdllib.cfg
+++ b/libraries/technology/ip_arria10/ddr4_mem_model_141/hdllib.cfg
@@ -2,12 +2,16 @@ hdl_lib_name = ip_arria10_ddr4_mem_model_141
hdl_library_clause_name = ed_sim_altera_emif_mem_model_core_ddr4_141
hdl_lib_uses_synth =
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_arria10
-modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10/ddr4_mem_model_141/compile_ip.tcl
-
synth_files =
test_bench_files =
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10/ddr4_mem_model_141/compile_ip.tcl
+
+
+[quartus_project_file]
diff --git a/libraries/technology/ip_arria10/fifo/hdllib.cfg b/libraries/technology/ip_arria10/fifo/hdllib.cfg
index be81b20d07f1569f60c3c2e00b65586877af4071..12198c4f1cd7ab8e944cad3f4e3e9f2e27f5806c 100644
--- a/libraries/technology/ip_arria10/fifo/hdllib.cfg
+++ b/libraries/technology/ip_arria10/fifo/hdllib.cfg
@@ -2,7 +2,6 @@ hdl_lib_name = ip_arria10_fifo
hdl_library_clause_name = ip_arria10_fifo_lib
hdl_lib_uses_synth = technology
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_arria10
synth_files =
@@ -11,3 +10,10 @@ synth_files =
ip_arria10_fifo_dc_mixed_widths.vhd
test_bench_files =
+
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+
diff --git a/libraries/technology/ip_arria10/flash/asmi_parallel/hdllib.cfg b/libraries/technology/ip_arria10/flash/asmi_parallel/hdllib.cfg
index 1198f8980b11c83898eb4b97cb3e04ca9e87bfb2..ff92bbf78ccbd3d2818665be6fca15372785f11f 100644
--- a/libraries/technology/ip_arria10/flash/asmi_parallel/hdllib.cfg
+++ b/libraries/technology/ip_arria10/flash/asmi_parallel/hdllib.cfg
@@ -2,15 +2,18 @@ hdl_lib_name = ip_arria10_asmi_parallel
hdl_library_clause_name = ip_arria10_asmi_parallel_altera_asmi_parallel_150
hdl_lib_uses_synth =
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_arria10
-modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10/flash/asmi_parallel/compile_ip.tcl
-
synth_files =
test_bench_files =
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10/flash/asmi_parallel/compile_ip.tcl
+
+
+[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_asmi_parallel.qip
diff --git a/libraries/technology/ip_arria10/flash/remote_update/hdllib.cfg b/libraries/technology/ip_arria10/flash/remote_update/hdllib.cfg
index 35530b18725c200b4f5c98ea94e9084f31a754bb..a1da1edce33e8dd6bac0b2befbf005eeb11ffcfb 100644
--- a/libraries/technology/ip_arria10/flash/remote_update/hdllib.cfg
+++ b/libraries/technology/ip_arria10/flash/remote_update/hdllib.cfg
@@ -2,15 +2,18 @@ hdl_lib_name = ip_arria10_remote_update
hdl_library_clause_name = ip_arria10_remote_update_altera_remote_update_150
hdl_lib_uses_synth =
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_arria10
-modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10/flash/remote_update/compile_ip.tcl
-
synth_files =
test_bench_files =
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10/flash/remote_update/compile_ip.tcl
+
+
+[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_remote_update.qip
diff --git a/libraries/technology/ip_arria10/fractional_pll_clk125/hdllib.cfg b/libraries/technology/ip_arria10/fractional_pll_clk125/hdllib.cfg
index 67d512bd7a5f819ac88d927c9f2a878b3a0a2277..e3e1e4ab6952a4d1b6f514a1076932043c28fb56 100644
--- a/libraries/technology/ip_arria10/fractional_pll_clk125/hdllib.cfg
+++ b/libraries/technology/ip_arria10/fractional_pll_clk125/hdllib.cfg
@@ -2,15 +2,18 @@ hdl_lib_name = ip_arria10_fractional_pll_clk125
hdl_library_clause_name = ip_arria10_fractional_pll_clk125_altera_xcvr_fpll_a10_150
hdl_lib_uses_synth =
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_arria10
-modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10/fractional_pll_clk125/compile_ip.tcl
-
synth_files =
test_bench_files =
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10/fractional_pll_clk125/compile_ip.tcl
+
+
+[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_fractional_pll_clk125.qip
diff --git a/libraries/technology/ip_arria10/fractional_pll_clk200/hdllib.cfg b/libraries/technology/ip_arria10/fractional_pll_clk200/hdllib.cfg
index 5ff81486b47748672e7284d1c1956b716d5241be..9efe341b9cdd9407d62381dfb8f5a35788e607e3 100644
--- a/libraries/technology/ip_arria10/fractional_pll_clk200/hdllib.cfg
+++ b/libraries/technology/ip_arria10/fractional_pll_clk200/hdllib.cfg
@@ -2,15 +2,18 @@ hdl_lib_name = ip_arria10_fractional_pll_clk200
hdl_library_clause_name = ip_arria10_fractional_pll_clk200_altera_xcvr_fpll_a10_150
hdl_lib_uses_synth =
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_arria10
-modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10/fractional_pll_clk200/compile_ip.tcl
-
synth_files =
test_bench_files =
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10/fractional_pll_clk200/compile_ip.tcl
+
+
+[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_fractional_pll_clk200.qip
diff --git a/libraries/technology/ip_arria10/mac_10g/hdllib.cfg b/libraries/technology/ip_arria10/mac_10g/hdllib.cfg
index 337af9fd0eebfd6d224046b92397841d9f7bdc51..432addcdba34207a925193a706ec1575ad870875 100644
--- a/libraries/technology/ip_arria10/mac_10g/hdllib.cfg
+++ b/libraries/technology/ip_arria10/mac_10g/hdllib.cfg
@@ -2,12 +2,8 @@ hdl_lib_name = ip_arria10_mac_10g
hdl_library_clause_name = ip_arria10_mac_10g_alt_em10g32_150
hdl_lib_uses_synth =
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_arria10
-modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10/mac_10g/compile_ip.tcl
-
synth_files =
test_bench_files =
@@ -15,5 +11,12 @@ test_bench_files =
# the tb is commented because it is not useful, see generate_ip.sh.
#$RADIOHDL/libraries/technology/ip_arria10/mac_10g/generated_tb/generated/sim/ip_arria10_mac_10g_tb.vhd
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10/mac_10g/compile_ip.tcl
+
+
+[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_mac_10g.qip
diff --git a/libraries/technology/ip_arria10/mult/hdllib.cfg b/libraries/technology/ip_arria10/mult/hdllib.cfg
index d4b2970091bb9063dfcbbdea2973751de1f09d2c..e703feb5f3d9ccca8a85124e58015f3b00beb5fd 100644
--- a/libraries/technology/ip_arria10/mult/hdllib.cfg
+++ b/libraries/technology/ip_arria10/mult/hdllib.cfg
@@ -2,7 +2,6 @@ hdl_lib_name = ip_arria10_mult
hdl_library_clause_name = ip_arria10_mult_lib
hdl_lib_uses_synth =
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_arria10
synth_files =
@@ -10,3 +9,10 @@ synth_files =
ip_arria10_mult_rtl.vhd
test_bench_files =
+
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r/hdllib.cfg b/libraries/technology/ip_arria10/phy_10gbase_r/hdllib.cfg
index 480ecc91750fe5d26e534847e92070fd6418bdd1..a9da96f5ea9795f156168e4be17199426ef20f02 100644
--- a/libraries/technology/ip_arria10/phy_10gbase_r/hdllib.cfg
+++ b/libraries/technology/ip_arria10/phy_10gbase_r/hdllib.cfg
@@ -2,15 +2,18 @@ hdl_lib_name = ip_arria10_phy_10gbase_r
hdl_library_clause_name = ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_150
hdl_lib_uses_synth =
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_arria10
-modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10/phy_10gbase_r/compile_ip.tcl
-
synth_files =
test_bench_files =
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10/phy_10gbase_r/compile_ip.tcl
+
+
+[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_phy_10gbase_r.qip
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r_12/hdllib.cfg b/libraries/technology/ip_arria10/phy_10gbase_r_12/hdllib.cfg
index 58025b87713261112c4675ce662739ecc470b4d1..df2b66e38e77302107d81bfa4461335744ad63db 100644
--- a/libraries/technology/ip_arria10/phy_10gbase_r_12/hdllib.cfg
+++ b/libraries/technology/ip_arria10/phy_10gbase_r_12/hdllib.cfg
@@ -2,15 +2,18 @@ hdl_lib_name = ip_arria10_phy_10gbase_r_12
hdl_library_clause_name = ip_arria10_phy_10gbase_r_12_altera_xcvr_native_a10_150
hdl_lib_uses_synth =
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_arria10
-modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10/phy_10gbase_r_12/compile_ip.tcl
-
synth_files =
test_bench_files =
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10/phy_10gbase_r_12/compile_ip.tcl
+
+
+[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_phy_10gbase_r_12.qip
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r_24/hdllib.cfg b/libraries/technology/ip_arria10/phy_10gbase_r_24/hdllib.cfg
index 121778e15829651ba053616694c99a237e44c3a6..ca1857cf4427a2f62e177dc9c2f281df595a0998 100644
--- a/libraries/technology/ip_arria10/phy_10gbase_r_24/hdllib.cfg
+++ b/libraries/technology/ip_arria10/phy_10gbase_r_24/hdllib.cfg
@@ -2,15 +2,18 @@ hdl_lib_name = ip_arria10_phy_10gbase_r_24
hdl_library_clause_name = ip_arria10_phy_10gbase_r_24_altera_xcvr_native_a10_150
hdl_lib_uses_synth =
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_arria10
-modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10/phy_10gbase_r_24/compile_ip.tcl
-
synth_files =
test_bench_files =
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10/phy_10gbase_r_24/compile_ip.tcl
+
+
+[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_phy_10gbase_r_24.qip
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r_4/hdllib.cfg b/libraries/technology/ip_arria10/phy_10gbase_r_4/hdllib.cfg
index 81402c691599bfea004c94fc91beda050beb96e2..b41ddab9729d0531ab11a620f2ee470721ba2bb0 100644
--- a/libraries/technology/ip_arria10/phy_10gbase_r_4/hdllib.cfg
+++ b/libraries/technology/ip_arria10/phy_10gbase_r_4/hdllib.cfg
@@ -2,15 +2,18 @@ hdl_lib_name = ip_arria10_phy_10gbase_r_4
hdl_library_clause_name = ip_arria10_phy_10gbase_r_4_altera_xcvr_native_a10_150
hdl_lib_uses_synth =
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_arria10
-modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10/phy_10gbase_r_4/compile_ip.tcl
-
synth_files =
test_bench_files =
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10/phy_10gbase_r_4/compile_ip.tcl
+
+
+[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_phy_10gbase_r_4.qip
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r_48/hdllib.cfg b/libraries/technology/ip_arria10/phy_10gbase_r_48/hdllib.cfg
index 03e0ff49ad63d7b6a4647f39be78174805228d0f..0a0ae1bc3b39c41d94730c8cf001f35b5b93663d 100644
--- a/libraries/technology/ip_arria10/phy_10gbase_r_48/hdllib.cfg
+++ b/libraries/technology/ip_arria10/phy_10gbase_r_48/hdllib.cfg
@@ -2,15 +2,18 @@ hdl_lib_name = ip_arria10_phy_10gbase_r_48
hdl_library_clause_name = ip_arria10_phy_10gbase_r_48_altera_xcvr_native_a10_150
hdl_lib_uses_synth =
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_arria10
-modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10/phy_10gbase_r_48/compile_ip.tcl
-
synth_files =
test_bench_files =
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10/phy_10gbase_r_48/compile_ip.tcl
+
+
+[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_phy_10gbase_r_48.qip
diff --git a/libraries/technology/ip_arria10/pll_clk125/hdllib.cfg b/libraries/technology/ip_arria10/pll_clk125/hdllib.cfg
index 36c69cea1d0c56a30376ccab0f7a86b73ee8b7ea..fbef174b2a9c3b185cb16a44ae1e3548aac79646 100644
--- a/libraries/technology/ip_arria10/pll_clk125/hdllib.cfg
+++ b/libraries/technology/ip_arria10/pll_clk125/hdllib.cfg
@@ -2,15 +2,18 @@ hdl_lib_name = ip_arria10_pll_clk125
hdl_library_clause_name = ip_arria10_pll_clk125_altera_iopll_150
hdl_lib_uses_synth =
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_arria10
-modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10/pll_clk125/compile_ip.tcl
-
synth_files =
test_bench_files =
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10/pll_clk125/compile_ip.tcl
+
+
+[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_pll_clk125.qip
diff --git a/libraries/technology/ip_arria10/pll_clk200/hdllib.cfg b/libraries/technology/ip_arria10/pll_clk200/hdllib.cfg
index a407fab699b60c0d7dd4c5fc1a82756f03b873bf..03522a7e1e346152f097664fc4cdd1f995a895ed 100644
--- a/libraries/technology/ip_arria10/pll_clk200/hdllib.cfg
+++ b/libraries/technology/ip_arria10/pll_clk200/hdllib.cfg
@@ -2,15 +2,18 @@ hdl_lib_name = ip_arria10_pll_clk200
hdl_library_clause_name = ip_arria10_pll_clk200_altera_iopll_150
hdl_lib_uses_synth =
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_arria10
-modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10/pll_clk200/compile_ip.tcl
-
synth_files =
test_bench_files =
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10/pll_clk200/compile_ip.tcl
+
+
+[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_pll_clk200.qip
diff --git a/libraries/technology/ip_arria10/pll_clk25/hdllib.cfg b/libraries/technology/ip_arria10/pll_clk25/hdllib.cfg
index aff8909344f820cf2b6b05e7a48daf32cd2a7708..55e9e73b6a9383e02e1eef7d2dc48e419f273914 100644
--- a/libraries/technology/ip_arria10/pll_clk25/hdllib.cfg
+++ b/libraries/technology/ip_arria10/pll_clk25/hdllib.cfg
@@ -2,15 +2,18 @@ hdl_lib_name = ip_arria10_pll_clk25
hdl_library_clause_name = ip_arria10_pll_clk25_altera_iopll_150
hdl_lib_uses_synth =
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_arria10
-modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10/pll_clk25/compile_ip.tcl
-
synth_files =
test_bench_files =
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10/pll_clk25/compile_ip.tcl
+
+
+[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_pll_clk25.qip
diff --git a/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/hdllib.cfg b/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/hdllib.cfg
index 31d1464deb73c6e1eb61e4303187e555fc6667da..deacb41f9e273b0f249c15c52b3d0f112ea2916e 100644
--- a/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/hdllib.cfg
+++ b/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/hdllib.cfg
@@ -2,15 +2,18 @@ hdl_lib_name = ip_arria10_pll_xgmii_mac_clocks
hdl_library_clause_name = ip_arria10_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_150
hdl_lib_uses_synth =
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_arria10
-modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/compile_ip.tcl
-
synth_files =
test_bench_files =
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/compile_ip.tcl
+
+
+[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_pll_xgmii_mac_clocks.qip
diff --git a/libraries/technology/ip_arria10/ram/hdllib.cfg b/libraries/technology/ip_arria10/ram/hdllib.cfg
index a2a5329df401508647ad698fa95378af616e3226..c9553187161f8d2cbccec309578d070827c40a0c 100644
--- a/libraries/technology/ip_arria10/ram/hdllib.cfg
+++ b/libraries/technology/ip_arria10/ram/hdllib.cfg
@@ -2,7 +2,6 @@ hdl_lib_name = ip_arria10_ram
hdl_library_clause_name = ip_arria10_ram_lib
hdl_lib_uses_synth = technology
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_arria10
synth_files =
@@ -16,3 +15,10 @@ synth_files =
ip_arria10_ram_r_w.vhd
test_bench_files =
+
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+
diff --git a/libraries/technology/ip_arria10/temp_sense/hdllib.cfg b/libraries/technology/ip_arria10/temp_sense/hdllib.cfg
index 54e94a998f655012b84c6d23db56db9b38b6bab9..5266b8bcf507c411827d3305a781fd0523ddf391 100644
--- a/libraries/technology/ip_arria10/temp_sense/hdllib.cfg
+++ b/libraries/technology/ip_arria10/temp_sense/hdllib.cfg
@@ -2,14 +2,17 @@ hdl_lib_name = ip_arria10_temp_sense
hdl_library_clause_name = ip_arria10_temp_sense_altera_temp_sense_150
hdl_lib_uses_synth =
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_arria10
-#modelsim_compile_ip_files =
-# $RADIOHDL/libraries/technology/ip_arria10/temp_sense/compile_ip.tcl
-
synth_files =
test_bench_files =
+
+[modelsim_project_file]
+#modelsim_compile_ip_files =
+# $RADIOHDL/libraries/technology/ip_arria10/temp_sense/compile_ip.tcl
+
+
+[quartus_project_file]
quartus_qip_files = generated/ip_arria10_temp_sense.qip
diff --git a/libraries/technology/ip_arria10/transceiver_pll_10g/hdllib.cfg b/libraries/technology/ip_arria10/transceiver_pll_10g/hdllib.cfg
index 609fb99a54f1c9d5c3305c6e9df3bf2cb004fcd7..0858e529e88f7920f15a49c92012f6d6a04f4bd7 100644
--- a/libraries/technology/ip_arria10/transceiver_pll_10g/hdllib.cfg
+++ b/libraries/technology/ip_arria10/transceiver_pll_10g/hdllib.cfg
@@ -2,15 +2,18 @@ hdl_lib_name = ip_arria10_transceiver_pll_10g
hdl_library_clause_name = ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_150
hdl_lib_uses_synth =
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_arria10
-modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10/transceiver_pll_10g/compile_ip.tcl
-
synth_files =
test_bench_files =
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10/transceiver_pll_10g/compile_ip.tcl
+
+
+[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_transceiver_pll_10g.qip
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_1/hdllib.cfg b/libraries/technology/ip_arria10/transceiver_reset_controller_1/hdllib.cfg
index 7fd7792ec16990d7e96913a0bc226a477fac9fb8..180275109acb0b7f090d075b0ca2430f892e2097 100644
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_1/hdllib.cfg
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_1/hdllib.cfg
@@ -2,15 +2,18 @@ hdl_lib_name = ip_arria10_transceiver_reset_controller_1
hdl_library_clause_name = ip_arria10_transceiver_reset_controller_1_altera_xcvr_reset_control_150
hdl_lib_uses_synth =
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_arria10
-modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10/transceiver_reset_controller_1/compile_ip.tcl
-
synth_files =
test_bench_files =
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10/transceiver_reset_controller_1/compile_ip.tcl
+
+
+[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_transceiver_reset_controller_1.qip
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_12/hdllib.cfg b/libraries/technology/ip_arria10/transceiver_reset_controller_12/hdllib.cfg
index bc07a17a1fdbc6e35eb68788f597f97d63a63ae7..11b372a73fb6c239c89d5b23051b19376c908492 100644
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_12/hdllib.cfg
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_12/hdllib.cfg
@@ -2,15 +2,18 @@ hdl_lib_name = ip_arria10_transceiver_reset_controller_12
hdl_library_clause_name = ip_arria10_transceiver_reset_controller_12_altera_xcvr_reset_control_150
hdl_lib_uses_synth =
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_arria10
-modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10/transceiver_reset_controller_12/compile_ip.tcl
-
synth_files =
test_bench_files =
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10/transceiver_reset_controller_12/compile_ip.tcl
+
+
+[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_transceiver_reset_controller_12.qip
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_24/hdllib.cfg b/libraries/technology/ip_arria10/transceiver_reset_controller_24/hdllib.cfg
index 9fb365e9111ac97740c61e14bf2cc16247984791..bb7b3626ee122d11066bb07c0ca4f11c80659816 100644
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_24/hdllib.cfg
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_24/hdllib.cfg
@@ -2,15 +2,18 @@ hdl_lib_name = ip_arria10_transceiver_reset_controller_24
hdl_library_clause_name = ip_arria10_transceiver_reset_controller_24_altera_xcvr_reset_control_150
hdl_lib_uses_synth =
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_arria10
-modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10/transceiver_reset_controller_24/compile_ip.tcl
-
synth_files =
test_bench_files =
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10/transceiver_reset_controller_24/compile_ip.tcl
+
+
+[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_transceiver_reset_controller_24.qip
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_4/hdllib.cfg b/libraries/technology/ip_arria10/transceiver_reset_controller_4/hdllib.cfg
index 5ac10251a31eca34f51671694464c383928b8121..fa0c96d38c6a383b35284b4b00e8073e16a71ae4 100644
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_4/hdllib.cfg
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_4/hdllib.cfg
@@ -2,15 +2,18 @@ hdl_lib_name = ip_arria10_transceiver_reset_controller_4
hdl_library_clause_name = ip_arria10_transceiver_reset_controller_4_altera_xcvr_reset_control_150
hdl_lib_uses_synth =
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_arria10
-modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10/transceiver_reset_controller_4/compile_ip.tcl
-
synth_files =
test_bench_files =
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10/transceiver_reset_controller_4/compile_ip.tcl
+
+
+[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_transceiver_reset_controller_4.qip
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_48/hdllib.cfg b/libraries/technology/ip_arria10/transceiver_reset_controller_48/hdllib.cfg
index 36a3cea67968def1be66ca0c10b0b22747d078d6..0db9821b674a4b34d06cc83f433c63c960e01ebb 100644
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_48/hdllib.cfg
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_48/hdllib.cfg
@@ -2,15 +2,18 @@ hdl_lib_name = ip_arria10_transceiver_reset_controller_48
hdl_library_clause_name = ip_arria10_transceiver_reset_controller_48_altera_xcvr_reset_control_150
hdl_lib_uses_synth =
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_arria10
-modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10/transceiver_reset_controller_48/compile_ip.tcl
-
synth_files =
test_bench_files =
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10/transceiver_reset_controller_48/compile_ip.tcl
+
+
+[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_transceiver_reset_controller_48.qip
diff --git a/libraries/technology/ip_arria10/tse_sgmii_gx/hdllib.cfg b/libraries/technology/ip_arria10/tse_sgmii_gx/hdllib.cfg
index 3ef64426b97bfc40f5b1c9a4241e224033ced51d..aad3d57375cbecb35f6430da62c800625254a2b7 100644
--- a/libraries/technology/ip_arria10/tse_sgmii_gx/hdllib.cfg
+++ b/libraries/technology/ip_arria10/tse_sgmii_gx/hdllib.cfg
@@ -2,16 +2,19 @@ hdl_lib_name = ip_arria10_tse_sgmii_gx
hdl_library_clause_name = ip_arria10_tse_sgmii_gx_altera_eth_tse_150
hdl_lib_uses_synth = common
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_arria10
-modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10/tse_sgmii_gx/compile_ip.tcl
-
synth_files =
test_bench_files =
tb_ip_arria10_tse_sgmii_gx.vhd
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10/tse_sgmii_gx/compile_ip.tcl
+
+
+[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_tse_sgmii_gx.qip
diff --git a/libraries/technology/ip_arria10/tse_sgmii_lvds/hdllib.cfg b/libraries/technology/ip_arria10/tse_sgmii_lvds/hdllib.cfg
index fbf2daaa28e250d2566a86fafb1732c0c77c7b85..d8a27e38483ade4d553e8a88616a30334cc57f2d 100644
--- a/libraries/technology/ip_arria10/tse_sgmii_lvds/hdllib.cfg
+++ b/libraries/technology/ip_arria10/tse_sgmii_lvds/hdllib.cfg
@@ -2,17 +2,20 @@ hdl_lib_name = ip_arria10_tse_sgmii_lvds
hdl_library_clause_name = ip_arria10_tse_sgmii_lvds_altera_eth_tse_150
hdl_lib_uses_synth = common
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_arria10
-modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10/tse_sgmii_lvds/compile_ip.tcl
-
synth_files =
test_bench_files =
tb_ip_arria10_tse_sgmii_lvds.vhd
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10/tse_sgmii_lvds/compile_ip.tcl
+
+
+[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_tse_sgmii_lvds.qip
diff --git a/libraries/technology/ip_arria10/voltage_sense/hdllib.cfg b/libraries/technology/ip_arria10/voltage_sense/hdllib.cfg
index 1c0b337feb7bedd1c9eac6c898e1d344d8115af5..7268d16a041547fac9b27bf6dc3e2b21198223b8 100644
--- a/libraries/technology/ip_arria10/voltage_sense/hdllib.cfg
+++ b/libraries/technology/ip_arria10/voltage_sense/hdllib.cfg
@@ -2,15 +2,18 @@ hdl_lib_name = ip_arria10_voltage_sense
hdl_library_clause_name = ip_arria10_voltage_sense_altera_voltage_sense_150
hdl_lib_uses_synth =
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_arria10
+synth_files =
+
+test_bench_files =
+
+
+[modelsim_project_file]
# There is no simulation model for the FPGA voltage sensor IP
#modelsim_compile_ip_files =
# $RADIOHDL/libraries/technology/ip_arria10/voltage_sense/compile_ip.tcl
-synth_files =
-
-test_bench_files =
+[quartus_project_file]
quartus_qip_files = generated/ip_arria10_voltage_sense.qip
diff --git a/libraries/technology/ip_arria10_e3sge3/clkbuf_global/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/clkbuf_global/hdllib.cfg
index 2c7493ddd92ed637aa183164b3286f4c7e2b6e7b..d2f19999520dc452bdeb821a512638e3eb022026 100644
--- a/libraries/technology/ip_arria10_e3sge3/clkbuf_global/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/clkbuf_global/hdllib.cfg
@@ -2,15 +2,18 @@ hdl_lib_name = ip_arria10_e3sge3_clkbuf_global
hdl_library_clause_name = ip_arria10_e3sge3_clkbuf_global_altclkctrl_151
hdl_lib_uses_synth =
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_arria10_e3sge3
-modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e3sge3/clkbuf_global/compile_ip.tcl
-
synth_files =
test_bench_files =
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10_e3sge3/clkbuf_global/compile_ip.tcl
+
+
+[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_e3sge3_clkbuf_global.qip
diff --git a/libraries/technology/ip_arria10_e3sge3/complex_mult/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/complex_mult/hdllib.cfg
index 66728e9b19c45f9266c4da516f0296a74857f971..43be8eb9553a48ff1e001165b30948243e22ce02 100644
--- a/libraries/technology/ip_arria10_e3sge3/complex_mult/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/complex_mult/hdllib.cfg
@@ -2,15 +2,18 @@ hdl_lib_name = ip_arria10_e3sge3_complex_mult
hdl_library_clause_name = ip_arria10_e3sge3_complex_mult_altmult_complex_150
hdl_lib_uses_synth =
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_arria10_e3sge3
-modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e3sge3/complex_mult/compile_ip.tcl
-
synth_files =
test_bench_files =
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10_e3sge3/complex_mult/compile_ip.tcl
+
+
+[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_e3sge3_complex_mult.qip
diff --git a/libraries/technology/ip_arria10_e3sge3/ddio/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/ddio/hdllib.cfg
index fca92aa025adf0ebc562147f878146a745adfd64..32435e25bc26e332970cfb915287ef36fddc7f74 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddio/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/ddio/hdllib.cfg
@@ -2,18 +2,21 @@ hdl_lib_name = ip_arria10_e3sge3_ddio
hdl_library_clause_name = ip_arria10_e3sge3_ddio_lib
hdl_lib_uses_synth = technology
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_arria10_e3sge3
-modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e3sge3/ddio/compile_ip.tcl
-
synth_files =
ip_arria10_e3sge3_ddio_in.vhd
ip_arria10_e3sge3_ddio_out.vhd
test_bench_files =
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10_e3sge3/ddio/compile_ip.tcl
+
+
+[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_e3sge3_ddio_in_1.qip
generated/ip_arria10_e3sge3_ddio_out_1.qip
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/hdllib.cfg
index 53b1928aa2efe9020e6722cbc04cc880d3a7d757..99742d110b23bb96f98a6551be1f893296e72b33 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/hdllib.cfg
@@ -2,15 +2,18 @@ hdl_lib_name = ip_arria10_e3sge3_ddr4_4g_1600
hdl_library_clause_name = ip_arria10_e3sge3_ddr4_4g_1600_altera_emif_150
hdl_lib_uses_synth =
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_arria10_e3sge3
-modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/compile_ip.tcl
-
synth_files =
test_bench_files =
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/compile_ip.tcl
+
+
+[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_e3sge3_ddr4_4g_1600.qip
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/hdllib.cfg
index 2a19b4445780c31c6f675a6a3e5d708ce3009855..f45e4a918bee4bc0b7f969cd828c5ba134c2069d 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/hdllib.cfg
@@ -2,15 +2,18 @@ hdl_lib_name = ip_arria10_e3sge3_ddr4_4g_2000
hdl_library_clause_name = ip_arria10_e3sge3_ddr4_4g_2000_altera_emif_150
hdl_lib_uses_synth =
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_arria10_e3sge3
-modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/compile_ip.tcl
-
synth_files =
test_bench_files =
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/compile_ip.tcl
+
+
+[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_e3sge3_ddr4_4g_2000.qip
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/hdllib.cfg
index 3a9628acbbff602703ea35b9424f41b1e0175300..acd778d40914613d3e3019cdf381cdacf5c5686a 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/hdllib.cfg
@@ -2,15 +2,18 @@ hdl_lib_name = ip_arria10_e3sge3_ddr4_8g_1600
hdl_library_clause_name = ip_arria10_e3sge3_ddr4_8g_1600_altera_emif_150
hdl_lib_uses_synth =
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_arria10_e3sge3
-modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/compile_ip.tcl
-
synth_files =
test_bench_files =
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/compile_ip.tcl
+
+
+[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_e3sge3_ddr4_8g_1600.qip
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/hdllib.cfg
index 3db8c8f2ed277e2a334dcb04d407e272faed9388..8c19e34ac81049413b10f681af37de392951610f 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/hdllib.cfg
@@ -2,15 +2,18 @@ hdl_lib_name = ip_arria10_e3sge3_ddr4_8g_2400
hdl_library_clause_name = ip_arria10_e3sge3_ddr4_8g_2400_altera_emif_151
hdl_lib_uses_synth =
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_arria10_e3sge3
-modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/compile_ip.tcl
-
synth_files =
test_bench_files =
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/compile_ip.tcl
+
+
+[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_e3sge3_ddr4_8g_2400.qip
diff --git a/libraries/technology/ip_arria10_e3sge3/fifo/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/fifo/hdllib.cfg
index da7f0d8f514e74ce724b4505b6b4f14cb8da3997..779ccfcef22b9018a7f4de064fbeb7fd66f93d43 100644
--- a/libraries/technology/ip_arria10_e3sge3/fifo/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/fifo/hdllib.cfg
@@ -2,7 +2,6 @@ hdl_lib_name = ip_arria10_e3sge3_fifo
hdl_library_clause_name = ip_arria10_e3sge3_fifo_lib
hdl_lib_uses_synth = technology
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_arria10_e3sge3
synth_files =
@@ -11,3 +10,10 @@ synth_files =
ip_arria10_e3sge3_fifo_dc_mixed_widths.vhd
test_bench_files =
+
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+
diff --git a/libraries/technology/ip_arria10_e3sge3/flash/asmi_parallel/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/flash/asmi_parallel/hdllib.cfg
index 52a2a86a6bf1622cecd8579d816f9571eb685543..704be79dca133b41f8688315080bc76b94600247 100644
--- a/libraries/technology/ip_arria10_e3sge3/flash/asmi_parallel/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/flash/asmi_parallel/hdllib.cfg
@@ -2,15 +2,18 @@ hdl_lib_name = ip_arria10_e3sge3_asmi_parallel
hdl_library_clause_name = ip_arria10_e3sge3_asmi_parallel_altera_asmi_parallel_151
hdl_lib_uses_synth =
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_arria10_e3sge3
-modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e3sge3/flash/asmi_parallel/compile_ip.tcl
-
synth_files =
test_bench_files =
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10_e3sge3/flash/asmi_parallel/compile_ip.tcl
+
+
+[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_e3sge3_asmi_parallel.qip
diff --git a/libraries/technology/ip_arria10_e3sge3/flash/remote_update/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/flash/remote_update/hdllib.cfg
index 0f8147f4fb5f06882b966f0b313e1a246a771c3f..697564797b4002322a1faf433b42a5f14aa31b5f 100644
--- a/libraries/technology/ip_arria10_e3sge3/flash/remote_update/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/flash/remote_update/hdllib.cfg
@@ -2,15 +2,18 @@ hdl_lib_name = ip_arria10_e3sge3_remote_update
hdl_library_clause_name = ip_arria10_e3sge3_remote_update_altera_remote_update_151
hdl_lib_uses_synth =
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_arria10_e3sge3
-modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e3sge3/flash/remote_update/compile_ip.tcl
-
synth_files =
test_bench_files =
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10_e3sge3/flash/remote_update/compile_ip.tcl
+
+
+[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_e3sge3_remote_update.qip
diff --git a/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk125/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk125/hdllib.cfg
index 7caa46b9723490a7cc3d811c2e8db6be53b408b7..febed22b2c259ac19b713f3874b271ee8a6dd4f3 100644
--- a/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk125/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk125/hdllib.cfg
@@ -2,15 +2,18 @@ hdl_lib_name = ip_arria10_e3sge3_fractional_pll_clk125
hdl_library_clause_name = ip_arria10_e3sge3_fractional_pll_clk125_altera_xcvr_fpll_a10_151
hdl_lib_uses_synth =
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_arria10_e3sge3
-modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk125/compile_ip.tcl
-
synth_files =
test_bench_files =
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk125/compile_ip.tcl
+
+
+[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_e3sge3_fractional_pll_clk125.qip
diff --git a/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk200/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk200/hdllib.cfg
index 8050fce67ed8f8bceaf10b3fa83b6cab83a98f26..fd683a26a024e9bc05c6c5d1fdc8b92c431a725b 100644
--- a/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk200/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk200/hdllib.cfg
@@ -2,15 +2,18 @@ hdl_lib_name = ip_arria10_e3sge3_fractional_pll_clk200
hdl_library_clause_name = ip_arria10_e3sge3_fractional_pll_clk200_altera_xcvr_fpll_a10_151
hdl_lib_uses_synth =
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_arria10_e3sge3
-modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk200/compile_ip.tcl
-
synth_files =
test_bench_files =
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk200/compile_ip.tcl
+
+
+[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_e3sge3_fractional_pll_clk200.qip
diff --git a/libraries/technology/ip_arria10_e3sge3/mac_10g/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/mac_10g/hdllib.cfg
index b04b01e7676b3901d2fd8358099633cf4f19fe33..0363ce82a4481ee0d6a6bb496dc20ebd3d5e91e1 100644
--- a/libraries/technology/ip_arria10_e3sge3/mac_10g/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/mac_10g/hdllib.cfg
@@ -2,12 +2,8 @@ hdl_lib_name = ip_arria10_e3sge3_mac_10g
hdl_library_clause_name = ip_arria10_e3sge3_mac_10g_alt_em10g32_151
hdl_lib_uses_synth =
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_arria10_e3sge3
-modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e3sge3/mac_10g/compile_ip.tcl
-
synth_files =
test_bench_files =
@@ -15,5 +11,12 @@ test_bench_files =
# the tb is commented because it is not useful, see generate_ip.sh.
#$RADIOHDL/libraries/technology/ip_arria10_e3sge3/mac_10g/generated_tb/generated/sim/ip_arria10_e3sge3_mac_10g_tb.vhd
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10_e3sge3/mac_10g/compile_ip.tcl
+
+
+[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_e3sge3_mac_10g.qip
diff --git a/libraries/technology/ip_arria10_e3sge3/mult_add4/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/mult_add4/hdllib.cfg
index 91d152874f07bacf7a12a239a23119aa29ff4fb3..e1d3436d38b2a3da24295e1e9751710ff5b2c494 100644
--- a/libraries/technology/ip_arria10_e3sge3/mult_add4/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/mult_add4/hdllib.cfg
@@ -2,14 +2,17 @@ hdl_lib_name = ip_arria10_e3sge3_mult_add4_rtl
hdl_library_clause_name = ip_arria10_e3sge3_mult_add4_rtl_lib
hdl_lib_uses_synth =
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_arria10_e3sge3
-modelsim_compile_ip_files =
-
synth_files =
ip_arria10_e3sge3_mult_add4_rtl.vhd
test_bench_files =
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+
+
+[quartus_project_file]
quartus_qip_files =
diff --git a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r/hdllib.cfg
index 5719a49ff68b8e4dbcc619515bd228e180e61002..849af13e09f18579eae4a33eb5086f4e9d28a148 100644
--- a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r/hdllib.cfg
@@ -2,15 +2,18 @@ hdl_lib_name = ip_arria10_e3sge3_phy_10gbase_r
hdl_library_clause_name = ip_arria10_e3sge3_phy_10gbase_r_altera_xcvr_native_a10_151
hdl_lib_uses_synth =
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_arria10_e3sge3
-modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r/compile_ip.tcl
-
synth_files =
test_bench_files =
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r/compile_ip.tcl
+
+
+[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_e3sge3_phy_10gbase_r.qip
diff --git a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_12/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_12/hdllib.cfg
index 80d0680bce7abd7730dc8d60262320b1aa229ed5..fba55e697b907a8822fbf7cffe71d4723cebbe48 100644
--- a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_12/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_12/hdllib.cfg
@@ -2,15 +2,18 @@ hdl_lib_name = ip_arria10_e3sge3_phy_10gbase_r_12
hdl_library_clause_name = ip_arria10_e3sge3_phy_10gbase_r_12_altera_xcvr_native_a10_151
hdl_lib_uses_synth =
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_arria10_e3sge3
-modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_12/compile_ip.tcl
-
synth_files =
test_bench_files =
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_12/compile_ip.tcl
+
+
+[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_e3sge3_phy_10gbase_r_12.qip
diff --git a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_24/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_24/hdllib.cfg
index 06f79d93742eb1f78d6c8f31b23140e2ebe7a25f..b04864d239bafa6707b06f1f78ddec43241d1eff 100644
--- a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_24/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_24/hdllib.cfg
@@ -2,15 +2,18 @@ hdl_lib_name = ip_arria10_e3sge3_phy_10gbase_r_24
hdl_library_clause_name = ip_arria10_e3sge3_phy_10gbase_r_24_altera_xcvr_native_a10_151
hdl_lib_uses_synth =
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_arria10_e3sge3
-modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_24/compile_ip.tcl
-
synth_files =
test_bench_files =
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_24/compile_ip.tcl
+
+
+[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_e3sge3_phy_10gbase_r_24.qip
diff --git a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_4/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_4/hdllib.cfg
index 5955c388eee8aa214c33c15a51fef41b4e68ef2a..efb4fdc211d4635c5e4f6e5dfa308b47d4e99276 100644
--- a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_4/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_4/hdllib.cfg
@@ -2,15 +2,18 @@ hdl_lib_name = ip_arria10_e3sge3_phy_10gbase_r_4
hdl_library_clause_name = ip_arria10_e3sge3_phy_10gbase_r_4_altera_xcvr_native_a10_151
hdl_lib_uses_synth =
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_arria10_e3sge3
-modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_4/compile_ip.tcl
-
synth_files =
test_bench_files =
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_4/compile_ip.tcl
+
+
+[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_e3sge3_phy_10gbase_r_4.qip
diff --git a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_48/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_48/hdllib.cfg
index b25af53a70bbd2dcdb4a6a796f129f90d8063397..6182b3cd25fe0582b834dad1a514cd46b9cb8b62 100644
--- a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_48/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_48/hdllib.cfg
@@ -2,15 +2,18 @@ hdl_lib_name = ip_arria10_e3sge3_phy_10gbase_r_48
hdl_library_clause_name = ip_arria10_e3sge3_phy_10gbase_r_48_altera_xcvr_native_a10_151
hdl_lib_uses_synth =
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_arria10_e3sge3
-modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_48/compile_ip.tcl
-
synth_files =
test_bench_files =
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_48/compile_ip.tcl
+
+
+[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_e3sge3_phy_10gbase_r_48.qip
diff --git a/libraries/technology/ip_arria10_e3sge3/pll_clk125/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/pll_clk125/hdllib.cfg
index 6857212230fb708c72bd3195a0849e840dd4eef9..b87c3842cdb7540ebac76db78ccc61f7d82b03c2 100644
--- a/libraries/technology/ip_arria10_e3sge3/pll_clk125/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/pll_clk125/hdllib.cfg
@@ -2,15 +2,18 @@ hdl_lib_name = ip_arria10_e3sge3_pll_clk125
hdl_library_clause_name = ip_arria10_e3sge3_pll_clk125_altera_iopll_151
hdl_lib_uses_synth =
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_arria10_e3sge3
-modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e3sge3/pll_clk125/compile_ip.tcl
-
synth_files =
test_bench_files =
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10_e3sge3/pll_clk125/compile_ip.tcl
+
+
+[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_e3sge3_pll_clk125.qip
diff --git a/libraries/technology/ip_arria10_e3sge3/pll_clk200/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/pll_clk200/hdllib.cfg
index 26ec0a211e56f4b8d0bcf62edd2005686fae8c22..746b95e754a798341f3b9dfff9b4b07203952a97 100644
--- a/libraries/technology/ip_arria10_e3sge3/pll_clk200/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/pll_clk200/hdllib.cfg
@@ -2,15 +2,18 @@ hdl_lib_name = ip_arria10_e3sge3_pll_clk200
hdl_library_clause_name = ip_arria10_e3sge3_pll_clk200_altera_iopll_151
hdl_lib_uses_synth =
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_arria10_e3sge3
-modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e3sge3/pll_clk200/compile_ip.tcl
-
synth_files =
test_bench_files =
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10_e3sge3/pll_clk200/compile_ip.tcl
+
+
+[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_e3sge3_pll_clk200.qip
diff --git a/libraries/technology/ip_arria10_e3sge3/pll_clk25/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/pll_clk25/hdllib.cfg
index 37d30f2de3d79c4461ff846cd7206a1e7eb85292..d921f8ffc420e5162b586f88237f688baa7d80e1 100644
--- a/libraries/technology/ip_arria10_e3sge3/pll_clk25/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/pll_clk25/hdllib.cfg
@@ -2,15 +2,18 @@ hdl_lib_name = ip_arria10_e3sge3_pll_clk25
hdl_library_clause_name = ip_arria10_e3sge3_pll_clk25_altera_iopll_151
hdl_lib_uses_synth =
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_arria10_e3sge3
-modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e3sge3/pll_clk25/compile_ip.tcl
-
synth_files =
test_bench_files =
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10_e3sge3/pll_clk25/compile_ip.tcl
+
+
+[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_e3sge3_pll_clk25.qip
diff --git a/libraries/technology/ip_arria10_e3sge3/pll_xgmii_mac_clocks/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/pll_xgmii_mac_clocks/hdllib.cfg
index a0be0646ddc2fd3791495f077e410a90da37ee6c..163fd8ab186a0ac58977718a7d4ab3c11b9ebf2a 100644
--- a/libraries/technology/ip_arria10_e3sge3/pll_xgmii_mac_clocks/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/pll_xgmii_mac_clocks/hdllib.cfg
@@ -2,15 +2,18 @@ hdl_lib_name = ip_arria10_e3sge3_pll_xgmii_mac_clocks
hdl_library_clause_name = ip_arria10_e3sge3_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_151
hdl_lib_uses_synth =
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_arria10_e3sge3
-modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e3sge3/pll_xgmii_mac_clocks/compile_ip.tcl
-
synth_files =
test_bench_files =
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10_e3sge3/pll_xgmii_mac_clocks/compile_ip.tcl
+
+
+[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_e3sge3_pll_xgmii_mac_clocks.qip
diff --git a/libraries/technology/ip_arria10_e3sge3/ram/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/ram/hdllib.cfg
index 44aaf317ab474fbd634e48227d7ab92668499b82..993b503c63d7488a3ad2222fd688611549eba9c0 100644
--- a/libraries/technology/ip_arria10_e3sge3/ram/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/ram/hdllib.cfg
@@ -2,7 +2,6 @@ hdl_lib_name = ip_arria10_e3sge3_ram
hdl_library_clause_name = ip_arria10_e3sge3_ram_lib
hdl_lib_uses_synth = technology
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_arria10_e3sge3
synth_files =
@@ -16,3 +15,10 @@ synth_files =
ip_arria10_e3sge3_ram_r_w.vhd
test_bench_files =
+
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+
diff --git a/libraries/technology/ip_arria10_e3sge3/temp_sense/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/temp_sense/hdllib.cfg
index 63d27bbaeb1eea2dae8c971f9a4d278d3415a260..0f2bea029fb8fbcc842f6f1d297459dd9995648a 100644
--- a/libraries/technology/ip_arria10_e3sge3/temp_sense/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/temp_sense/hdllib.cfg
@@ -2,14 +2,17 @@ hdl_lib_name = ip_arria10_e3sge3_temp_sense
hdl_library_clause_name = ip_arria10_e3sge3_temp_sense_altera_temp_sense_151
hdl_lib_uses_synth =
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_arria10_e3sge3
-#modelsim_compile_ip_files =
-# $RADIOHDL/libraries/technology/ip_arria10_e3sge3/temp_sense/compile_ip.tcl
-
synth_files =
test_bench_files =
+
+[modelsim_project_file]
+#modelsim_compile_ip_files =
+# $RADIOHDL/libraries/technology/ip_arria10_e3sge3/temp_sense/compile_ip.tcl
+
+
+[quartus_project_file]
quartus_qip_files = generated/ip_arria10_e3sge3_temp_sense.qip
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/hdllib.cfg
index ca0096f0c4c5d65f32fe86f0f49de9511e49a15b..24cb2c48dae12ac23d8b262b9ee6ded525114af5 100644
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/hdllib.cfg
@@ -2,15 +2,18 @@ hdl_lib_name = ip_arria10_e3sge3_transceiver_pll_10g
hdl_library_clause_name = ip_arria10_e3sge3_transceiver_pll_10g_altera_xcvr_atx_pll_a10_151
hdl_lib_uses_synth =
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_arria10_e3sge3
-modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/compile_ip.tcl
-
synth_files =
test_bench_files =
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/compile_ip.tcl
+
+
+[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_e3sge3_transceiver_pll_10g.qip
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_1/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_1/hdllib.cfg
index fbb5c8d1a6ba64b0d9753a9edd3bfad46c3d32e1..38e2dc944a833fb93a89d97d8df765991ba0730e 100644
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_1/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_1/hdllib.cfg
@@ -2,15 +2,18 @@ hdl_lib_name = ip_arria10_e3sge3_transceiver_reset_controller_1
hdl_library_clause_name = ip_arria10_e3sge3_transceiver_reset_controller_1_altera_xcvr_reset_control_151
hdl_lib_uses_synth =
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_arria10_e3sge3
-modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_1/compile_ip.tcl
-
synth_files =
test_bench_files =
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_1/compile_ip.tcl
+
+
+[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_e3sge3_transceiver_reset_controller_1.qip
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/hdllib.cfg
index 90ac370efd1619feeac0d86266e2d26b339a6d82..491b15792b0284eb1e42a82634e76e797180e2a6 100644
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/hdllib.cfg
@@ -2,15 +2,18 @@ hdl_lib_name = ip_arria10_e3sge3_transceiver_reset_controller_12
hdl_library_clause_name = ip_arria10_e3sge3_transceiver_reset_controller_12_altera_xcvr_reset_control_151
hdl_lib_uses_synth =
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_arria10_e3sge3
-modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/compile_ip.tcl
-
synth_files =
test_bench_files =
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/compile_ip.tcl
+
+
+[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_e3sge3_transceiver_reset_controller_12.qip
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/hdllib.cfg
index 46a59f7ae1c748b427c4bbd2e649fa81e28c38a4..6eb1e1c0cab242ef642312c657d200c3a6e50656 100644
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/hdllib.cfg
@@ -2,15 +2,18 @@ hdl_lib_name = ip_arria10_e3sge3_transceiver_reset_controller_24
hdl_library_clause_name = ip_arria10_e3sge3_transceiver_reset_controller_24_altera_xcvr_reset_control_151
hdl_lib_uses_synth =
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_arria10_e3sge3
-modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/compile_ip.tcl
-
synth_files =
test_bench_files =
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/compile_ip.tcl
+
+
+[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_e3sge3_transceiver_reset_controller_24.qip
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_4/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_4/hdllib.cfg
index e4ca93899575afe2a1b933f2f1b52a244262b32a..0d46dbf1cfdd24d57dcd56b9f1410cd63a4f0339 100644
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_4/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_4/hdllib.cfg
@@ -2,15 +2,18 @@ hdl_lib_name = ip_arria10_e3sge3_transceiver_reset_controller_4
hdl_library_clause_name = ip_arria10_e3sge3_transceiver_reset_controller_4_altera_xcvr_reset_control_151
hdl_lib_uses_synth =
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_arria10_e3sge3
-modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_4/compile_ip.tcl
-
synth_files =
test_bench_files =
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_4/compile_ip.tcl
+
+
+[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_e3sge3_transceiver_reset_controller_4.qip
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/hdllib.cfg
index a677a2d9dfb1220cbe6e79273c3336414219856b..2598b18af3ee9843c8bd3cbcf8d9cd54c67bdecd 100644
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/hdllib.cfg
@@ -2,15 +2,18 @@ hdl_lib_name = ip_arria10_e3sge3_transceiver_reset_controller_48
hdl_library_clause_name = ip_arria10_e3sge3_transceiver_reset_controller_48_altera_xcvr_reset_control_151
hdl_lib_uses_synth =
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_arria10_e3sge3
-modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/compile_ip.tcl
-
synth_files =
test_bench_files =
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/compile_ip.tcl
+
+
+[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_e3sge3_transceiver_reset_controller_48.qip
diff --git a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/hdllib.cfg
index 08b93719dc0476c7c07404d2e49af4de685e5daf..931957a3a1ab079a3cac8bf191c2405e1b859643 100644
--- a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/hdllib.cfg
@@ -2,16 +2,19 @@ hdl_lib_name = ip_arria10_e3sge3_tse_sgmii_gx
hdl_library_clause_name = ip_arria10_e3sge3_tse_sgmii_gx_altera_eth_tse_151
hdl_lib_uses_synth = common
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_arria10_e3sge3
-modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/compile_ip.tcl
-
synth_files =
test_bench_files =
tb_ip_arria10_e3sge3_tse_sgmii_gx.vhd
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/compile_ip.tcl
+
+
+[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_e3sge3_tse_sgmii_gx.qip
diff --git a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/hdllib.cfg
index e8b3d4351add0c8fd7b030a896d9ee64a79eabdf..a99d870f4e48194cc5932d207d0636c8d5e97eee 100644
--- a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/hdllib.cfg
@@ -2,17 +2,20 @@ hdl_lib_name = ip_arria10_e3sge3_tse_sgmii_lvds
hdl_library_clause_name = ip_arria10_e3sge3_tse_sgmii_lvds_altera_eth_tse_151
hdl_lib_uses_synth = common
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_arria10_e3sge3
-modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10/tse_sgmii_lvds/compile_ip.tcl
-
synth_files =
test_bench_files =
tb_ip_arria10_e3sge3_tse_sgmii_lvds.vhd
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10/tse_sgmii_lvds/compile_ip.tcl
+
+
+[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_e3sge3_tse_sgmii_lvds.qip
diff --git a/libraries/technology/ip_arria10_e3sge3/voltage_sense/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/voltage_sense/hdllib.cfg
index 6f541b5a4624904a10c79605c297fcab0a4b6000..5c3a2a7bfe4b276f5f74182f7ef6f90a9617ef4b 100644
--- a/libraries/technology/ip_arria10_e3sge3/voltage_sense/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/voltage_sense/hdllib.cfg
@@ -2,15 +2,18 @@ hdl_lib_name = ip_arria10_e3sge3_voltage_sense
hdl_library_clause_name = ip_arria10_e3sge3_voltage_sense_altera_voltage_sense_151
hdl_lib_uses_synth =
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_arria10_e3sge3
+synth_files =
+
+test_bench_files =
+
+
+[modelsim_project_file]
# There is no simulation model for the FPGA voltage sensor IP
#modelsim_compile_ip_files =
# $RADIOHDL/libraries/technology/ip_arria10_e3sge3/voltage_sense/compile_ip.tcl
-synth_files =
-
-test_bench_files =
+[quartus_project_file]
quartus_qip_files = generated/ip_arria10_e3sge3_voltage_sense.qip
diff --git a/libraries/technology/ip_stratixiv/ddio/hdllib.cfg b/libraries/technology/ip_stratixiv/ddio/hdllib.cfg
index 64947cdaec41c6ed2b3e6984f33cbaa8dbb0f0d6..f997c9361bcf14c0fe36a525c6c2b924de3525b8 100644
--- a/libraries/technology/ip_stratixiv/ddio/hdllib.cfg
+++ b/libraries/technology/ip_stratixiv/ddio/hdllib.cfg
@@ -2,7 +2,6 @@ hdl_lib_name = ip_stratixiv_ddio
hdl_library_clause_name = ip_stratixiv_ddio_lib
hdl_lib_uses_synth = technology
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_stratixiv
synth_files =
@@ -10,3 +9,10 @@ synth_files =
ip_stratixiv_ddio_out.vhd
test_bench_files =
+
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+
diff --git a/libraries/technology/ip_stratixiv/ddr3_mem_model/hdllib.cfg b/libraries/technology/ip_stratixiv/ddr3_mem_model/hdllib.cfg
index a69f1eb2023f6b724d78561e817ea06532325d4d..54443d82bc8706cfabd8f161b798027f03eed36f 100644
--- a/libraries/technology/ip_stratixiv/ddr3_mem_model/hdllib.cfg
+++ b/libraries/technology/ip_stratixiv/ddr3_mem_model/hdllib.cfg
@@ -2,12 +2,16 @@ hdl_lib_name = ip_stratixiv_ddr3_mem_model
hdl_library_clause_name = ip_stratixiv_ddr3_mem_model_lib
hdl_lib_uses_synth = ip_stratixiv_ddr3_uphy_4g_800_master
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_stratixiv
-modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_mem_model/compile_ip.tcl
-
synth_files =
test_bench_files =
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_mem_model/compile_ip.tcl
+
+
+[quartus_project_file]
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/hdllib.cfg b/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/hdllib.cfg
index 8c7e30a9beabbeff86521480f20ebfb673e2c3ad..bd0c67d481a485039d38482e77af2999acff3191 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/hdllib.cfg
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/hdllib.cfg
@@ -2,16 +2,19 @@ hdl_lib_name = ip_stratixiv_ddr3_uphy_16g_dual_rank_800
hdl_library_clause_name = ip_stratixiv_ddr3_uphy_16g_dual_rank_800_lib
hdl_lib_uses_synth =
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_stratixiv
+synth_files =
+
+test_bench_files =
+
+
+[modelsim_project_file]
modelsim_compile_ip_files =
$RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/compile_ip.tcl
$RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/copy_hex_files.tcl
-synth_files =
-
-test_bench_files =
+[quartus_project_file]
quartus_qip_files =
generated/ip_stratixiv_ddr3_uphy_16g_dual_rank_800.qip
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/hdllib.cfg b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/hdllib.cfg
index 2710516aa8fa7a372f3f4d17f60f2f0592777dc6..1b11fbe2fac1ba9fb6f176c1c70b0e1b4bba16e9 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/hdllib.cfg
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/hdllib.cfg
@@ -2,16 +2,19 @@ hdl_lib_name = ip_stratixiv_ddr3_uphy_4g_800_master
hdl_library_clause_name = ip_stratixiv_ddr3_uphy_4g_800_master_lib
hdl_lib_uses_synth =
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_stratixiv
+synth_files =
+
+test_bench_files =
+
+
+[modelsim_project_file]
modelsim_compile_ip_files =
$RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/compile_ip.tcl
$RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
-synth_files =
-
-test_bench_files =
+[quartus_project_file]
quartus_qip_files =
generated/ip_stratixiv_ddr3_uphy_4g_800_master.qip
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/hdllib.cfg b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/hdllib.cfg
index 32d7619a5e99cf6f55b5b9844faba85f7fac9d9b..4d64d1ae14dc8c0c7025a745e7d9284fc46bccf2 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/hdllib.cfg
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/hdllib.cfg
@@ -2,15 +2,18 @@ hdl_lib_name = ip_stratixiv_ddr3_uphy_4g_800_slave
hdl_library_clause_name = ip_stratixiv_ddr3_uphy_4g_800_slave_lib
hdl_lib_uses_synth =
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_stratixiv
-modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/compile_ip.tcl
-
synth_files =
test_bench_files =
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/compile_ip.tcl
+
+
+[quartus_project_file]
quartus_qip_files =
generated/ip_stratixiv_ddr3_uphy_4g_800_slave.qip
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/hdllib.cfg b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/hdllib.cfg
index 4a77a9c54c247cccae3a5ef8be62de8fb1d7642f..5b71690a3af4b72c6ed67cb395d65c66cca3f8cc 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/hdllib.cfg
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/hdllib.cfg
@@ -2,16 +2,19 @@ hdl_lib_name = ip_stratixiv_ddr3_uphy_4g_single_rank_800_master
hdl_library_clause_name = ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_lib
hdl_lib_uses_synth =
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_stratixiv
+synth_files =
+
+test_bench_files =
+
+
+[modelsim_project_file]
modelsim_compile_ip_files =
$RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/compile_ip.tcl
$RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
-synth_files =
-
-test_bench_files =
+[quartus_project_file]
quartus_qip_files =
generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/hdllib.cfg b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/hdllib.cfg
index 74afd000ad04bdbabf8a58285dbf2a150391814d..09191b848f0cce35af586d655fcc8efd3ac75afe 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/hdllib.cfg
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/hdllib.cfg
@@ -2,16 +2,19 @@ hdl_lib_name = ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave
hdl_library_clause_name = ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave_lib
hdl_lib_uses_synth =
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_stratixiv
+synth_files =
+
+test_bench_files =
+
+
+[modelsim_project_file]
modelsim_compile_ip_files =
$RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/compile_ip.tcl
$RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/copy_hex_files.tcl
-synth_files =
-
-test_bench_files =
+[quartus_project_file]
quartus_qip_files =
generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave.qip
diff --git a/libraries/technology/ip_stratixiv/fifo/hdllib.cfg b/libraries/technology/ip_stratixiv/fifo/hdllib.cfg
index e709650d93e82b0a0d870555670d3766e3af213b..67c34076a981e5504f4ac0b5f3c993712a88d744 100644
--- a/libraries/technology/ip_stratixiv/fifo/hdllib.cfg
+++ b/libraries/technology/ip_stratixiv/fifo/hdllib.cfg
@@ -2,7 +2,6 @@ hdl_lib_name = ip_stratixiv_fifo
hdl_library_clause_name = ip_stratixiv_fifo_lib
hdl_lib_uses_synth = technology
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_stratixiv
synth_files =
@@ -11,3 +10,10 @@ synth_files =
ip_stratixiv_fifo_sc.vhd
test_bench_files =
+
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+
diff --git a/libraries/technology/ip_stratixiv/flash/hdllib.cfg b/libraries/technology/ip_stratixiv/flash/hdllib.cfg
index cc6328f702565d0903bae53859216067c7a0c3b4..47a0434734f95cdaf3bb9d688372171411c9b980 100644
--- a/libraries/technology/ip_stratixiv/flash/hdllib.cfg
+++ b/libraries/technology/ip_stratixiv/flash/hdllib.cfg
@@ -2,7 +2,6 @@ hdl_lib_name = ip_stratixiv_flash
hdl_library_clause_name = ip_stratixiv_flash_lib
hdl_lib_uses_synth = technology numonyx_m25p128
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_stratixiv
synth_files =
@@ -11,5 +10,11 @@ synth_files =
test_bench_files =
+
+[modelsim_project_file]
modelsim_copy_files =
$RADIOHDL/libraries/external/numonyx_m25p128/NU_M25P128_V10/sim/memory_file .
+
+
+[quartus_project_file]
+
diff --git a/libraries/technology/ip_stratixiv/mac_10g/hdllib.cfg b/libraries/technology/ip_stratixiv/mac_10g/hdllib.cfg
index a63f73b35d3f9b0809471394165db060937caa71..c548304587aff440c8bbcc978e1f8ec27483e23c 100644
--- a/libraries/technology/ip_stratixiv/mac_10g/hdllib.cfg
+++ b/libraries/technology/ip_stratixiv/mac_10g/hdllib.cfg
@@ -2,18 +2,21 @@ hdl_lib_name = ip_stratixiv_mac_10g
hdl_library_clause_name = ip_stratixiv_mac_10g_lib
hdl_lib_uses_synth = common
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_stratixiv
-modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_stratixiv/mac_10g/compile_ip.tcl
-
synth_files =
test_bench_files =
+
+[modelsim_project_file]
modelsim_copy_files =
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_stratixiv/mac_10g/compile_ip.tcl
+
+
+[quartus_project_file]
quartus_copy_files =
quartus_vhdl_files =
diff --git a/libraries/technology/ip_stratixiv/mult/hdllib.cfg b/libraries/technology/ip_stratixiv/mult/hdllib.cfg
index f86aebcee45ffb14c025a705f69e8ce8759ab6fb..09c1c605e91fca71905f26261a85c21154e96fe7 100644
--- a/libraries/technology/ip_stratixiv/mult/hdllib.cfg
+++ b/libraries/technology/ip_stratixiv/mult/hdllib.cfg
@@ -2,7 +2,6 @@ hdl_lib_name = ip_stratixiv_mult
hdl_library_clause_name = ip_stratixiv_mult_lib
hdl_lib_uses_synth = technology common
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_stratixiv
synth_files =
@@ -14,3 +13,10 @@ synth_files =
ip_stratixiv_mult_add4_rtl.vhd
test_bench_files =
+
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/ip_stratixiv_phy_xaui_0.vhd b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/ip_stratixiv_phy_xaui_0.vhd
index 4e561332dedee9ffd0ef1cf1d4f1ec6400aa7b73..9655c20d448738e939ee1bbef069437ce061d861 100644
--- a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/ip_stratixiv_phy_xaui_0.vhd
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/ip_stratixiv_phy_xaui_0.vhd
@@ -1,6 +1,6 @@
-- ip_stratixiv_phy_xaui_0.vhd
--- Generated using ACDS version 11.1sp2 259 at 2014.09.29.14:00:54
+-- Generated using ACDS version 11.1sp2 259 at 2016.03.29.08:44:51
library IEEE;
use IEEE.std_logic_1164.all;
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/mentor/msim_setup.tcl b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/mentor/msim_setup.tcl
index e19fa6f7e7fa37fc50ac7264c417da2639ddbc0f..60168352309689d35362392fbc0b76d29d125dab 100644
--- a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/mentor/msim_setup.tcl
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/mentor/msim_setup.tcl
@@ -1,5 +1,5 @@
-# (C) 2001-2014 Altera Corporation. All rights reserved.
+# (C) 2001-2016 Altera Corporation. All rights reserved.
# Your use of Altera Corporation's design tools, logic functions and
# other software and tools, and its AMPP partner logic functions, and
# any output files any of the foregoing (including device programming
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/ip_stratixiv_phy_xaui_soft.vhd b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/ip_stratixiv_phy_xaui_soft.vhd
index 2975d799b3b68a98ce7a88f1eb09c715928250ae..0a66ff3f1e984b49396ce3063832fd0004897c6c 100644
--- a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/ip_stratixiv_phy_xaui_soft.vhd
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/ip_stratixiv_phy_xaui_soft.vhd
@@ -1,6 +1,6 @@
-- ip_stratixiv_phy_xaui_soft.vhd
--- Generated using ACDS version 11.1sp2 259 at 2014.09.29.14:01:40
+-- Generated using ACDS version 11.1sp2 259 at 2016.03.29.08:45:31
library IEEE;
use IEEE.std_logic_1164.all;
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/mentor/msim_setup.tcl b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/mentor/msim_setup.tcl
index 4c03220d0d8ad10469ae5b21e348907a8558fdce..2d65d2485fcad863158ebf147c6776ef82384d54 100644
--- a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/mentor/msim_setup.tcl
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/mentor/msim_setup.tcl
@@ -1,5 +1,5 @@
-# (C) 2001-2014 Altera Corporation. All rights reserved.
+# (C) 2001-2016 Altera Corporation. All rights reserved.
# Your use of Altera Corporation's design tools, logic functions and
# other software and tools, and its AMPP partner logic functions, and
# any output files any of the foregoing (including device programming
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/hdllib.cfg b/libraries/technology/ip_stratixiv/phy_xaui/hdllib.cfg
index 197723815858426ae02368cb1173895ac94226d3..06cb12d45ed0de2a85911fe269d9b23379858345 100644
--- a/libraries/technology/ip_stratixiv/phy_xaui/hdllib.cfg
+++ b/libraries/technology/ip_stratixiv/phy_xaui/hdllib.cfg
@@ -2,13 +2,8 @@ hdl_lib_name = ip_stratixiv_phy_xaui
hdl_library_clause_name = ip_stratixiv_phy_xaui_lib
hdl_lib_uses_synth = common
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_stratixiv
-modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_stratixiv/phy_xaui/compile_ip.tcl
- $RADIOHDL/libraries/technology/ip_stratixiv/phy_xaui/compile_ip_soft.tcl
-
synth_files =
ip_stratixiv_phy_xaui_0.vhd
ip_stratixiv_phy_xaui_1.vhd
@@ -19,10 +14,18 @@ test_bench_files =
tb_ip_stratixiv_phy_xaui.vhd
tb_ip_stratixiv_phy_xaui_ppm.vhd
+
+[modelsim_project_file]
modelsim_copy_files =
wave_tb_ip_stratixiv_phy_xaui.do .
wave_tb_ip_stratixiv_phy_xaui_ppm.do .
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_stratixiv/phy_xaui/compile_ip.tcl
+ $RADIOHDL/libraries/technology/ip_stratixiv/phy_xaui/compile_ip_soft.tcl
+
+
+[quartus_project_file]
quartus_copy_files =
quartus_vhdl_files =
diff --git a/libraries/technology/ip_stratixiv/pll/hdllib.cfg b/libraries/technology/ip_stratixiv/pll/hdllib.cfg
index 7fda9fcc02f6466c4f7a4c76f8971d81f190cc43..a56d2d2e3b0779d23e7076f7b3adcaf6aee7b05c 100644
--- a/libraries/technology/ip_stratixiv/pll/hdllib.cfg
+++ b/libraries/technology/ip_stratixiv/pll/hdllib.cfg
@@ -2,7 +2,6 @@ hdl_lib_name = ip_stratixiv_pll
hdl_library_clause_name = ip_stratixiv_pll_lib
hdl_lib_uses_synth =
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_stratixiv
synth_files =
@@ -10,3 +9,10 @@ synth_files =
ip_stratixiv_pll_clk200_p6.vhd
test_bench_files =
+
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+
diff --git a/libraries/technology/ip_stratixiv/pll_clk25/hdllib.cfg b/libraries/technology/ip_stratixiv/pll_clk25/hdllib.cfg
index c6c2741712f2c2010e1b5ba561788c01bfe3dc1e..65a5c9fcf649b2f7804e9cb7a04afe2c014501b9 100644
--- a/libraries/technology/ip_stratixiv/pll_clk25/hdllib.cfg
+++ b/libraries/technology/ip_stratixiv/pll_clk25/hdllib.cfg
@@ -2,10 +2,16 @@ hdl_lib_name = ip_stratixiv_pll_clk25
hdl_library_clause_name = ip_stratixiv_pll_clk25_lib
hdl_lib_uses_synth =
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_stratixiv
synth_files =
ip_stratixiv_pll_clk25.vhd
test_bench_files =
+
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+
diff --git a/libraries/technology/ip_stratixiv/ram/hdllib.cfg b/libraries/technology/ip_stratixiv/ram/hdllib.cfg
index 0ef6a8342f3b37e1b63f611852831d372f68c9bc..b33799a56452d3e97acbdcc3505e0342493ec0ae 100644
--- a/libraries/technology/ip_stratixiv/ram/hdllib.cfg
+++ b/libraries/technology/ip_stratixiv/ram/hdllib.cfg
@@ -2,7 +2,6 @@ hdl_lib_name = ip_stratixiv_ram
hdl_library_clause_name = ip_stratixiv_ram_lib
hdl_lib_uses_synth = technology
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_stratixiv
synth_files =
@@ -13,3 +12,10 @@ synth_files =
ip_stratixiv_rom_r.vhd
test_bench_files =
+
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+
diff --git a/libraries/technology/ip_stratixiv/transceiver/hdllib.cfg b/libraries/technology/ip_stratixiv/transceiver/hdllib.cfg
index 26d0175c6eeb61f355048928a3fa4b97be583f96..ca35fe298b6f0a2dd1259963ff7c7cc318f0fe5c 100644
--- a/libraries/technology/ip_stratixiv/transceiver/hdllib.cfg
+++ b/libraries/technology/ip_stratixiv/transceiver/hdllib.cfg
@@ -2,7 +2,6 @@ hdl_lib_name = ip_stratixiv_transceiver
hdl_library_clause_name = ip_stratixiv_transceiver_lib
hdl_lib_uses_synth = technology
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_stratixiv
synth_files =
@@ -29,3 +28,10 @@ synth_files =
ip_stratixiv_hssi_rx_16b.vhd
test_bench_files =
+
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+
diff --git a/libraries/technology/ip_stratixiv/tse_sgmii_gx/hdllib.cfg b/libraries/technology/ip_stratixiv/tse_sgmii_gx/hdllib.cfg
index 155cf6e658d7a0e483f21b39dde6cffb4b81025e..b5969afd7c7ef98420e2aa40de820c31100d4201 100644
--- a/libraries/technology/ip_stratixiv/tse_sgmii_gx/hdllib.cfg
+++ b/libraries/technology/ip_stratixiv/tse_sgmii_gx/hdllib.cfg
@@ -2,7 +2,6 @@ hdl_lib_name = ip_stratixiv_tse_sgmii_gx
hdl_library_clause_name = ip_stratixiv_tse_sgmii_gx_lib
hdl_lib_uses_synth =
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_stratixiv
synth_files =
@@ -10,6 +9,11 @@ synth_files =
test_bench_files =
ip_stratixiv_tse_sgmii_gx.vho
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
quartus_vhdl_files =
ip_stratixiv_tse_sgmii_gx.vhd
diff --git a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/hdllib.cfg b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/hdllib.cfg
index 84b356b2d3744146b39d78116e656fd958fe9ea3..7c4dbe9d0b0bd8325cc5ac30e32e851736a6901d 100644
--- a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/hdllib.cfg
+++ b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/hdllib.cfg
@@ -2,7 +2,6 @@ hdl_lib_name = ip_stratixiv_tse_sgmii_lvds
hdl_library_clause_name = ip_stratixiv_tse_sgmii_lvds_lib
hdl_lib_uses_synth = common
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_stratixiv
synth_files =
@@ -11,6 +10,11 @@ test_bench_files =
ip_stratixiv_tse_sgmii_lvds.vho
tb_ip_stratixiv_tse_sgmii_lvds.vhd
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
quartus_vhdl_files =
ip_stratixiv_tse_sgmii_lvds.vhd
diff --git a/libraries/technology/ip_virtex4/hdllib.cfg b/libraries/technology/ip_virtex4/hdllib.cfg
index 9f0f32940f55a55cb459bf77a0cb8ae32168118d..63d38b131a1377a53668845c883d8916f26e4f55 100644
--- a/libraries/technology/ip_virtex4/hdllib.cfg
+++ b/libraries/technology/ip_virtex4/hdllib.cfg
@@ -2,9 +2,11 @@ hdl_lib_name = ip_virtex4
hdl_library_clause_name = ip_virtex4_lib
hdl_lib_uses_synth =
hdl_lib_uses_sim =
-
hdl_lib_technology = ip_virtex4
synth_files =
test_bench_files =
+
+
+[modelsim_project_file]
diff --git a/libraries/technology/mac_10g/hdllib.cfg b/libraries/technology/mac_10g/hdllib.cfg
index fee6509fd534ad95d1ba5b37464b2d136ca1303a..840ffab5b6e4c7a68e7b23ac3f47786ccd443316 100644
--- a/libraries/technology/mac_10g/hdllib.cfg
+++ b/libraries/technology/mac_10g/hdllib.cfg
@@ -2,7 +2,6 @@ hdl_lib_name = tech_mac_10g
hdl_library_clause_name = tech_mac_10g_lib
hdl_lib_uses_synth = technology ip_stratixiv_mac_10g ip_arria10_mac_10g ip_arria10_e3sge3_mac_10g common dp
hdl_lib_uses_sim =
-
hdl_lib_technology =
synth_files =
@@ -24,7 +23,12 @@ test_bench_files =
tb_tech_mac_10g.vhd
tb_tb_tech_mac_10g.vhd
+
+[modelsim_project_file]
modelsim_copy_files =
wave_tb_tech_mac_10g_stratixiv.do .
wave_tb_tech_mac_10g_arria10.do .
+
+[quartus_project_file]
+
diff --git a/libraries/technology/memory/hdllib.cfg b/libraries/technology/memory/hdllib.cfg
index 5795b280e8a92747ba4fee5345162ff33c01d52b..e1cdd1cdc425186d006d3af3a99f8a939cbbf7d1 100644
--- a/libraries/technology/memory/hdllib.cfg
+++ b/libraries/technology/memory/hdllib.cfg
@@ -2,7 +2,6 @@ hdl_lib_name = tech_memory
hdl_library_clause_name = tech_memory_lib
hdl_lib_uses_synth = technology ip_stratixiv_ram ip_arria10_ram ip_arria10_e3sge3_ram
hdl_lib_uses_sim =
-
hdl_lib_technology =
synth_files =
@@ -14,3 +13,10 @@ synth_files =
tech_memory_rom_r.vhd
test_bench_files =
+
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+
diff --git a/libraries/technology/mult/hdllib.cfg b/libraries/technology/mult/hdllib.cfg
index 6d8901db15006aec4471fe77173e448f8656c9c6..73bc46a0cc54582998215df2db95ccec5a2f9fa4 100644
--- a/libraries/technology/mult/hdllib.cfg
+++ b/libraries/technology/mult/hdllib.cfg
@@ -8,7 +8,6 @@ hdl_lib_uses_synth = common
ip_arria10_complex_mult_rtl
ip_arria10_e3sge3_mult_add4_rtl
hdl_lib_uses_sim =
-
hdl_lib_technology =
synth_files =
@@ -19,3 +18,10 @@ synth_files =
tech_mult.vhd
test_bench_files =
+
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+
diff --git a/libraries/technology/pll/hdllib.cfg b/libraries/technology/pll/hdllib.cfg
index b22b74085d00541279d734471b00165064bf069f..25b1d8f50aaa9828db53a001a58e401446d4d17b 100644
--- a/libraries/technology/pll/hdllib.cfg
+++ b/libraries/technology/pll/hdllib.cfg
@@ -13,7 +13,6 @@ hdl_lib_uses_synth = technology
ip_arria10_e3sge3_pll_clk125
common
hdl_lib_uses_sim =
-
hdl_lib_technology =
synth_files =
@@ -25,3 +24,10 @@ synth_files =
tech_pll_clk125.vhd
test_bench_files =
+
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+
diff --git a/libraries/technology/transceiver/hdllib.cfg b/libraries/technology/transceiver/hdllib.cfg
index 55f3e3dea7980e66d71a9b73f6e080a4d37c1162..2b84eb47a4a92675aaf0827e85c5c1be4c7d043d 100644
--- a/libraries/technology/transceiver/hdllib.cfg
+++ b/libraries/technology/transceiver/hdllib.cfg
@@ -2,7 +2,6 @@ hdl_lib_name = tech_transceiver
hdl_library_clause_name = tech_transceiver_lib
hdl_lib_uses_synth = technology ip_stratixiv_transceiver common dp
hdl_lib_uses_sim =
-
hdl_lib_technology =
synth_files =
@@ -22,3 +21,10 @@ synth_files =
test_bench_files =
tb_sim_transceiver_serdes.vhd
+
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+
diff --git a/libraries/technology/tse/hdllib.cfg b/libraries/technology/tse/hdllib.cfg
index 6f10a65cf0c14be5d70a1c6ff6de618c6dd3882f..79c9dad1527944d39cadaf4e0612db7ac951324d 100644
--- a/libraries/technology/tse/hdllib.cfg
+++ b/libraries/technology/tse/hdllib.cfg
@@ -1,12 +1,11 @@
hdl_lib_name = tech_tse
hdl_library_clause_name = tech_tse_lib
hdl_lib_uses_synth = technology
- ip_stratixiv_tse_sgmii_lvds ip_stratixiv_tse_sgmii_gx
- ip_arria10_tse_sgmii_lvds ip_arria10_tse_sgmii_gx
- ip_arria10_e3sge3_tse_sgmii_lvds ip_arria10_e3sge3_tse_sgmii_gx
- common dp
+ ip_stratixiv_tse_sgmii_lvds ip_stratixiv_tse_sgmii_gx
+ ip_arria10_tse_sgmii_lvds ip_arria10_tse_sgmii_gx
+ ip_arria10_e3sge3_tse_sgmii_lvds ip_arria10_e3sge3_tse_sgmii_gx
+ common dp
hdl_lib_uses_sim =
-
hdl_lib_technology =
synth_files =
@@ -22,3 +21,9 @@ test_bench_files =
tb_tech_tse_pkg.vhd
tb_tech_tse.vhd
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+
diff --git a/libraries/technology/xaui/hdllib.cfg b/libraries/technology/xaui/hdllib.cfg
index 2ae45b5fc68993e5c1b514855dcf973e6f916f8f..4e4877861d23e7999227d3151f86faa6c934c90e 100644
--- a/libraries/technology/xaui/hdllib.cfg
+++ b/libraries/technology/xaui/hdllib.cfg
@@ -1,13 +1,7 @@
hdl_lib_name = tech_xaui
hdl_library_clause_name = tech_xaui_lib
-hdl_lib_uses_synth = technology
- ip_stratixiv_transceiver
- ip_stratixiv_phy_xaui
- tech_transceiver
- common
- dp
+hdl_lib_uses_synth = technology ip_stratixiv_transceiver ip_stratixiv_phy_xaui tech_transceiver common dp
hdl_lib_uses_sim =
-
hdl_lib_technology =
synth_files =
@@ -18,3 +12,10 @@ synth_files =
tech_xaui.vhd
test_bench_files =
+
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+