Added [section headers].

applications/dig_receiver/designs/dig_receiver_bn/hdllib.cfg

@@ -2,16 +2,8 @@ hdl_lib_name = dig_receiver_bn
 hdl_library_clause_name = dig_receiver_bn_lib
 hdl_lib_uses_synth = common mm dp unb1_board diag digital_receiver dr_mesh test_generator
 hdl_lib_uses_sim = 
-
 hdl_lib_technology = ip_stratixiv
 
-synth_top_level_entity = dig_receiver_bn
-
-quartus_copy_files =
-    $RADIOHDL/applications/dig_receiver/designs/dig_receiver_bn/quartus/sopc_dig_receiver_bn.sopc .
-
-modelsim_copy_files = 
-
 synth_files =
     $HDL_BUILD_DIR/unb1/quartus/dig_receiver_bn/sopc_dig_receiver_bn.vhd
     $RADIOHDL/applications/dig_receiver/designs/dig_receiver_bn/src/vhdl/adc_lvds.vhd
@@ -21,6 +13,17 @@ synth_files =
 
 test_bench_files =
 
+
+[modelsim_project_file]
+modelsim_copy_files = 
+
+
+[quartus_project_file]
+synth_top_level_entity = dig_receiver_bn
+
+quartus_copy_files =
+    $RADIOHDL/applications/dig_receiver/designs/dig_receiver_bn/quartus/sopc_dig_receiver_bn.sopc .
+
 quartus_qsf_files =
     $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
 

applications/dig_receiver/designs/dig_receiver_fn/hdllib.cfg

@@ -2,16 +2,8 @@ hdl_lib_name = dig_receiver_fn
 hdl_library_clause_name = dig_receiver_fn_lib
 hdl_lib_uses_synth = common mm dp unb1_board diag digital_receiver dr_mesh tr_10GbE dr_udp_packetizer
 hdl_lib_uses_sim = 
-
 hdl_lib_technology = ip_stratixiv
 
-synth_top_level_entity = dig_receiver_fn
-
-quartus_copy_files =
-    $RADIOHDL/applications/dig_receiver/designs/dig_receiver_fn/quartus/sopc_dig_receiver_fn.sopc .
-
-modelsim_copy_files = 
-
 synth_files =
     $HDL_BUILD_DIR/unb1/quartus/dig_receiver_fn/sopc_dig_receiver_fn.vhd
     $RADIOHDL/applications/dig_receiver/designs/dig_receiver_fn/src/vhdl/dig_receiver_mm.vhd
@@ -20,6 +12,17 @@ synth_files =
 
 test_bench_files =
 
+
+[modelsim_project_file]
+modelsim_copy_files = 
+
+
+[quartus_project_file]
+synth_top_level_entity = dig_receiver_fn
+
+quartus_copy_files =
+    $RADIOHDL/applications/dig_receiver/designs/dig_receiver_fn/quartus/sopc_dig_receiver_fn.sopc .
+
 quartus_qsf_files =
     $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
 

applications/dig_receiver/libraries/common_OA/hdllib.cfg

@@ -2,12 +2,8 @@ hdl_lib_name = common_OA
 hdl_library_clause_name = common_OA_lib
 hdl_lib_uses_synth = technology common
 hdl_lib_uses_sim = 
-
 hdl_lib_technology = 
 
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
-
 synth_files =
     $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/common_OA/src/vhdl/common_ram_wsrs.vhd
     $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/common_OA/src/vhdl/common_pulse_delay.vhd
@@ -24,3 +20,9 @@ synth_files =
 
 test_bench_files = 
 
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+

applications/dig_receiver/libraries/dbbc/hdllib.cfg

@@ -2,11 +2,8 @@ hdl_lib_name = dbbc
 hdl_library_clause_name = dbbc_lib
 hdl_lib_uses_synth = common mm dp common_OA
 hdl_lib_uses_sim = 
-
 hdl_lib_technology = 
 
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
 
 synth_files =
     $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/dbbc/src/vhdl/dBBC_pkg.vhd
@@ -25,3 +22,9 @@ synth_files =
     
 test_bench_files = 
 
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+

applications/dig_receiver/libraries/digital_receiver/hdllib.cfg

@@ -2,12 +2,8 @@ hdl_lib_name = digital_receiver
 hdl_library_clause_name = digital_receiver_lib
 hdl_lib_uses_synth = common mm dp common_OA dbbc fft_module_n vdif_formatter
 hdl_lib_uses_sim = 
-
 hdl_lib_technology = 
 
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
-
 synth_files =
     $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/DigitalReceiver/src/vhdl/digrec_pkg.vhd
     $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/DigitalReceiver/src/vhdl/realign_data.vhd
@@ -44,3 +40,10 @@ synth_files =
    
 test_bench_files = 
 
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+
+

applications/dig_receiver/libraries/dr_mesh/hdllib.cfg

@@ -2,12 +2,8 @@ hdl_lib_name = dr_mesh
 hdl_library_clause_name = dr_mesh_lib
 hdl_lib_uses_synth = common mm dp diag tr_nonbonded
 hdl_lib_uses_sim = 
-
 hdl_lib_technology = 
 
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
-
 synth_files =
     $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/dr_mesh/src/vhdl/mesh_pkg.vhd
     $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/dr_mesh/src/vhdl/mesh_resample_47.vhd
@@ -27,3 +23,9 @@ synth_files =
 
 test_bench_files = 
 
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+

applications/dig_receiver/libraries/fft_module_n/hdllib.cfg

@@ -2,12 +2,8 @@ hdl_lib_name = fft_module_n
 hdl_library_clause_name = fft_module_n_lib
 hdl_lib_uses_synth = technology common common_OA
 hdl_lib_uses_sim = 
-
 hdl_lib_technology = 
 
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
-
 synth_files =
     $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/fft/src/vhdl/fft_pkg.vhd
     $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/fft/src/vhdl/multadd.vhd
@@ -50,3 +46,9 @@ test_bench_files =
     $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/fft/src/vhdl/sims/tb_fftmod4_dav.vhd
     $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/fft/src/vhdl/sims/tb_real_fft.vhd
 
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+

applications/dig_receiver/libraries/polyfilt/hdllib.cfg

@@ -2,12 +2,8 @@ hdl_lib_name = polyfilt
 hdl_library_clause_name = polyfilt_lib
 hdl_lib_uses_synth = technology common common_OA fft_module_n
 hdl_lib_uses_sim = 
-
 hdl_lib_technology = 
 
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
-
 synth_files =
   $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/polyfilt/src/vhdl/channelizer_pfb_4.vhd
   $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/polyfilt/src/vhdl/poly_filter_main.vhd
@@ -25,3 +21,9 @@ synth_files =
 test_bench_files =
   $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/polyfilt/src/vhdl/poly_filt_tb.vhd
 
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+

applications/dig_receiver/libraries/test_generator/hdllib.cfg

@@ -2,12 +2,8 @@ hdl_lib_name = test_generator
 hdl_library_clause_name = test_generator_lib
 hdl_lib_uses_synth = common mm dp diag axi4
 hdl_lib_uses_sim = 
-
 hdl_lib_technology = 
 
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
-
 synth_files =
     $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/test_generator/src/vhdl/cal_pulse.vhd
     $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/test_generator/src/vhdl/xorshift_RNG.vhd
@@ -20,3 +16,11 @@ synth_files =
     
 test_bench_files = 
     $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/test_generator/src/vhdl/tb_test_generator.vhd
+
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+
+

applications/dig_receiver/libraries/udp_packetizer/hdllib.cfg

@@ -2,12 +2,8 @@ hdl_lib_name = dr_udp_packetizer
 hdl_library_clause_name = dr_udp_packetizer_lib
 hdl_lib_uses_synth = common mm dp technology_lib tr_10GbE_lib tech_mac_10g tech_eth_10g tr_xaui
 hdl_lib_uses_sim = 
-
 hdl_lib_technology = 
 
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
-
 synth_files =
     $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/udp_packetizer/src/vhdl/udp_packetizer_pkg.vhd
     $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/udp_packetizer/src/vhdl/udp_packetizer_st.vhd
@@ -16,3 +12,9 @@ synth_files =
 
 test_bench_files = 
 
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+

applications/dig_receiver/libraries/vdif_formatter/hdllib.cfg

@@ -2,12 +2,8 @@ hdl_lib_name = vdif_formatter
 hdl_library_clause_name = vdif_formatter_lib
 hdl_lib_uses_synth = common mm dp common_OA 
 hdl_lib_uses_sim = 
-
 hdl_lib_technology = 
 
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
-
 synth_files =
     $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/formatter/src/vhdl/format_header.vhd
     $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/formatter/src/vhdl/formatter.vhd
@@ -19,3 +15,9 @@ synth_files =
 
 test_bench_files = 
 
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+

applications/rfidb/designs/rfidb/hdllib.cfg

@@ -2,20 +2,8 @@ hdl_lib_name = unb1_rfidb
 hdl_library_clause_name = unb1_rfidb_lib
 hdl_lib_uses_synth =  common dp unb1_board diag eth detector tech_tse
 hdl_lib_uses_sim = 
-
 hdl_lib_technology = ip_stratixiv
 
-synth_top_level_entity =
-
-quartus_copy_files =
-    quartus/qsys_unb1_rfidb.qsys .
-    $RADIOHDL/libraries/base/dp/designs/unb1_dp_offload/src/hex hex
-
-modelsim_copy_files =
-    $RADIOHDL/libraries/base/dp/designs/unb1_dp_offload/src/hex hex
-    tb/data data
-    modelsim .
-
 synth_files =
     src/vhdl/rfidb_constants_pkg.vhd
     src/vhdl/qsys_unb1_rfidb_pkg.vhd
@@ -25,6 +13,21 @@ synth_files =
 test_bench_files = 
     tb/vhdl/tb_unb1_rfidb.vhd
 
+
+[modelsim_project_file]
+modelsim_copy_files =
+    $RADIOHDL/libraries/base/dp/designs/unb1_dp_offload/src/hex hex
+    tb/data data
+    modelsim .
+
+
+[quartus_project_file]
+synth_top_level_entity =
+
+quartus_copy_files =
+    quartus/qsys_unb1_rfidb.qsys .
+    $RADIOHDL/libraries/base/dp/designs/unb1_dp_offload/src/hex hex
+
 quartus_qsf_files =
     $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
 

applications/rfidb/librairies/detector/hdllib.cfg

 hdl_lib_name = detector
 hdl_library_clause_name = detector_lib
 hdl_lib_uses_synth = common technology mm ip_arria10_fifo ip_stratixiv_fifo tech_fifo dp ip_stratixiv_ram ip_arria10_ram tech_memory
-
 hdl_lib_technology = 
 
 synth_files = 
@@ -14,7 +13,6 @@ synth_files =
     src/vhdl/detector.vhd
     src/vhdl/write_rfi_db.vhd
 
-
 test_bench_files = 
     tb/vhdl/tb_universal_shift_reg.vhd
     tb/vhdl/tb_robust_mean.vhd
@@ -23,5 +21,10 @@ test_bench_files =
     tb/vhdl/tb_detector.vhd
     tb/vhdl/tb_write_rfi_db.vhd
 
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
 quartus_qip_files =
     $RADIOHDL/applications/rfidb/designs/rfidb/quartus/alt_probe.qip

applications/stagiair/designs/stagiair_unb1_wave_gen/hdllib.cfg

@@ -2,7 +2,6 @@ hdl_lib_name = stagiair_unb1_wave_gen
 hdl_library_clause_name = stagiair_unb1_wave_gen_lib
 hdl_lib_uses_synth = common mm unb1_board wave_gen
 hdl_lib_uses_sim = 
-
 hdl_lib_technology = ip_stratixiv
 
 synth_files =
@@ -14,6 +13,11 @@ synth_files =
 test_bench_files = 
     tb/vhdl/tb_stagiair_unb1_wave_gen.vhd
 
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
 synth_top_level_entity =
 
 quartus_copy_files =

applications/stagiair/libraries/wave_gen/hdllib.cfg

@@ -2,7 +2,6 @@ hdl_lib_name = wave_gen
 hdl_library_clause_name = wave_gen_lib
 hdl_lib_uses_synth = common_mult common dp mm diag
 hdl_lib_uses_sim = 
-
 hdl_lib_technology = 
 
 synth_files =
@@ -14,3 +13,8 @@ test_bench_files =
     tb/vhdl/tb_sine_gen.vhd
     tb/vhdl/tb_wave_gen.vhd
 
+
+[modelsim_project_file]
+
+
+[quartus_project_file]

boards/uniboard1/designs/unb1_bn_capture/hdllib.cfg

@@ -3,11 +3,6 @@ hdl_library_clause_name = unb1_bn_capture_lib
 hdl_lib_uses_synth = common unb1_board dp eth tech_tse diag aduh 
 hdl_lib_technology = ip_stratixiv
 
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
-
-synth_top_level_entity =
-
 synth_files =
     $HDL_BUILD_DIR/unb1/quartus/unb1_bn_capture/sopc_unb1_bn_capture.vhd
     src/vhdl/unb1_bn_capture_pkg.vhd
@@ -19,13 +14,19 @@ test_bench_files =
     tb/vhdl/tb_unb1_bn_capture.vhd
     tb/vhdl/tb_node_unb1_bn_capture.vhd
 
-quartus_copy_files = quartus/sopc_unb1_bn_capture.sopc .
-                     $RADIOHDL/libraries/io/i2c/tb/data data
-                     $RADIOHDL/libraries/base/diag/src/data data
 
+[modelsim_project_file]
 modelsim_copy_files = $RADIOHDL/libraries/io/i2c/tb/data data   
                       $RADIOHDL/libraries/base/diag/src/data data
 
+
+[quartus_project_file]
+synth_top_level_entity =
+
+quartus_copy_files = quartus/sopc_unb1_bn_capture.sopc .
+                     $RADIOHDL/libraries/io/i2c/tb/data data
+                     $RADIOHDL/libraries/base/diag/src/data data
+
 quartus_qsf_files = 
     $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
     

boards/uniboard1/designs/unb1_bn_terminal_bg/hdllib.cfg

@@ -3,11 +3,6 @@ hdl_library_clause_name = unb1_bn_terminal_bg_lib
 hdl_lib_uses_synth = common unb1_board dp eth tech_tse diag bf  
 hdl_lib_technology = ip_stratixiv
 
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
-
-synth_top_level_entity =
-
 synth_files =
     $HDL_BUILD_DIR/unb1/quartus/unb1_bn_terminal_bg/sopc_unb1_bn_terminal_bg.vhd
     src/vhdl/node_unb1_bn_terminal_bg.vhd
@@ -17,8 +12,14 @@ test_bench_files =
     tb/vhdl/tb_node_unb1_bn_terminal_bg.vhd
     tb/vhdl/tb_tb_node_unb1_bn_terminal_bg.vhd    
 
+
+[modelsim_project_file]
 modelsim_copy_files = $RADIOHDL/libraries/base/diag/src/data data
 
+
+[quartus_project_file]
+synth_top_level_entity =
+
 quartus_copy_files = quartus/sopc_unb1_bn_terminal_bg.sopc .
                      $RADIOHDL/libraries/base/diag/src/data data 
 
@@ -32,7 +33,3 @@ quartus_qip_files = $HDL_BUILD_DIR/unb1/quartus/unb1_bn_terminal_bg/sopc_unb1_bn
 
 quartus_sdc_files =
     $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
-
-
-
-

boards/uniboard1/designs/unb1_ddr3/hdllib.cfg

@@ -16,9 +16,13 @@ synth_files =
 test_bench_files = 
     tb/vhdl/tb_unb1_ddr3.vhd
 
+
+[modelsim_project_file]
 modelsim_compile_ip_files =
     $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
     
+
+[quartus_project_file]
 synth_top_level_entity =
 
 quartus_copy_files =

boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/hdllib.cfg

@@ -3,7 +3,6 @@ hdl_library_clause_name = unb1_ddr3_reorder_dual_rank_lib
 hdl_lib_uses_synth = common technology mm i2c unb1_board dp eth tech_tse diag io_ddr reorder
 hdl_lib_uses_sim = 
 hdl_lib_technology = ip_stratixiv
-
 hdl_lib_excludes = ip_stratixiv_ddr3_uphy_4g_800_slave 
                    ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave 
                    ip_stratixiv_ddr3_uphy_4g_single_rank_800_master                   
@@ -20,15 +19,22 @@ test_bench_files =
     ../../tb/vhdl/tb_unb1_ddr3_reorder.vhd
     tb_unb1_ddr3_reorder_dual_rank.vhd
 
+
+[modelsim_project_file]
+modelsim_copy_files = 
+    ../../src/hex hex
+
+modelsim_compile_ip_files =
+    $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
+    
+
+[quartus_project_file]
 synth_top_level_entity =
 
 quartus_copy_files =
     ../../quartus/sopc_unb1_ddr3_reorder.sopc .
     ../../src/hex hex
 
-modelsim_copy_files = 
-    ../../src/hex hex
-
 quartus_qsf_files =
     $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
     
@@ -42,6 +48,3 @@ quartus_qip_files =
     $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master.qip
     $RADIOHDL/build/unb1/quartus/unb1_ddr3_reorder_dual_rank/sopc_unb1_ddr3_reorder.qip
     
-modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
-    

boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_single_rank/hdllib.cfg

@@ -19,15 +19,22 @@ test_bench_files =
     ../../tb/vhdl/tb_unb1_ddr3_reorder.vhd
     tb_unb1_ddr3_reorder_single_rank.vhd
 
+
+[modelsim_project_file]
+modelsim_copy_files = 
+    ../../src/hex hex
+
+modelsim_compile_ip_files =
+    $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
+    
+
+[quartus_project_file]
 synth_top_level_entity =
 
 quartus_copy_files =
     ../../quartus/sopc_unb1_ddr3_reorder.sopc .
     ../../src/hex hex
 
-modelsim_copy_files = 
-    ../../src/hex hex
-
 quartus_qsf_files =
     $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
     
@@ -41,6 +48,3 @@ quartus_qip_files =
     $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
     $RADIOHDL/build/unb1/quartus/unb1_ddr3_reorder_single_rank/sopc_unb1_ddr3_reorder.qip
     
-modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
-