Skip to content
Snippets Groups Projects
Commit b232c8c7 authored by Eric Kooistra's avatar Eric Kooistra
Browse files

Added [section headers].

parent 742a0824
No related branches found
No related tags found
No related merge requests found
Show whitespace changes
Inline Side-by-side
Showing
with 126 additions and 76 deletions
applications/compaan/designs/compaan_unb1_10g_app/hdllib.cfg
+ 7
− 2
View file @ b232c8c7
......@@ -3,8 +3,6 @@ hdl_library_clause_name = compaan_unb1_10g_app_lib
hdl_lib_uses_synth = common unb1_board dp eth tech_tse diag tr_10GbE compaan
hdl_lib_technology = ip_stratixiv
synth_top_level_entity =
synth_files =
src/vhdl/compaan_unb1_10g_pkg.vhd
src/vhdl/compaan_design.vhd
......@@ -16,6 +14,13 @@ synth_files =
test_bench_files =
tb/vhdl/tb_compaan_unb1_10g_app.vhd
[modelsim_project_file]
[quartus_project_file]
synth_top_level_entity =
quartus_copy_files = quartus/qsys_compaan_unb1_10g_app.qsys .
quartus_qsf_files =
......
applications/compaan/designs/compaan_unb1_10g_bg_db/hdllib.cfg
+ 7
− 2
View file @ b232c8c7
......@@ -3,8 +3,6 @@ hdl_library_clause_name = compaan_unb1_10g_bg_db_lib
hdl_lib_uses_synth = common unb1_board dp eth tech_tse diag tr_10GbE
hdl_lib_technology = ip_stratixiv
synth_top_level_entity =
synth_files =
src/vhdl/mmm_compaan_unb1_10g_bg_db.vhd
src/vhdl/compaan_unb1_10g_bg_db.vhd
......@@ -12,6 +10,13 @@ synth_files =
test_bench_files =
tb/vhdl/tb_compaan_unb1_10g_bg_db.vhd
[modelsim_project_file]
[quartus_project_file]
synth_top_level_entity =
quartus_copy_files = quartus/qsys_compaan_unb1_10g_bg_db.qsys .
quartus_qsf_files =
......
applications/compaan/designs/compaan_unb1_dp_offload/hdllib.cfg
+ 5
− 3
View file @ b232c8c7
......@@ -3,9 +3,6 @@ hdl_library_clause_name = compaan_unb1_dp_offload_lib
hdl_lib_uses_synth = common unb1_board dp eth tech_tse diag compaan
hdl_lib_technology = ip_stratixiv
build_dir_sim = $HDL_BUILD_DIR
build_dir_synth = $HDL_BUILD_DIR
synth_files =
$HDL_BUILD_DIR/quartus/compaan_unb1_dp_offload/sopc_compaan_unb1_dp_offload.vhd
src/vhdl/pkg_signals.vhd
......@@ -19,6 +16,11 @@ test_bench_files =
tb/vhdl/tb_compaan_unb1_dp_offload_bg_lb.vhd
tb/vhdl/tb_compaan_unb1_dp_offload_bg_co.vhd
[modelsim_project_file]
[quartus_project_file]
quartus_sdc_files =
$RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
applications/compaan/designs/compaan_unb1_dp_offload/revisions/compaan_unb1_dp_offload_bg/hdllib.cfg
+ 7
− 5
View file @ b232c8c7
......@@ -3,11 +3,6 @@ hdl_library_clause_name = compaan_unb1_dp_offload_bg_lib
hdl_lib_uses_synth = common unb1_board dp eth tech_tse diag compaan
hdl_lib_technology = ip_stratixiv
build_dir_sim = $HDL_BUILD_DIR
build_dir_synth = $HDL_BUILD_DIR
synth_top_level_entity =
synth_files =
$HDL_BUILD_DIR/unb1/quartus/compaan_unb1_dp_offload_bg/sopc_compaan_unb1_dp_offload.vhd
../../src/vhdl/pkg_signals.vhd
......@@ -22,6 +17,13 @@ test_bench_files =
../../tb/vhdl/tb_compaan_unb1_dp_offload_bg_lb.vhd
../../tb/vhdl/tb_compaan_unb1_dp_offload_bg_co.vhd
[modelsim_project_file]
[quartus_project_file]
synth_top_level_entity =
quartus_copy_files = ../../quartus/sopc_compaan_unb1_dp_offload.sopc .
quartus_qsf_files =
......
applications/compaan/designs/compaan_unb1_dp_offload/revisions/compaan_unb1_dp_offload_co/hdllib.cfg
+ 8
− 5
View file @ b232c8c7
......@@ -3,11 +3,6 @@ hdl_library_clause_name = compaan_unb1_dp_offload_co_lib
hdl_lib_uses_synth = common unb1_board dp eth tech_tse diag compaan
hdl_lib_technology = ip_stratixiv
build_dir_sim = $HDL_BUILD_DIR
build_dir_synth = $HDL_BUILD_DIR
synth_top_level_entity =
synth_files =
$HDL_BUILD_DIR/unb1/quartus/compaan_unb1_dp_offload_co/sopc_compaan_unb1_dp_offload.vhd
../../src/vhdl/pkg_signals.vhd
......@@ -22,6 +17,14 @@ test_bench_files =
../../tb/vhdl/tb_compaan_unb1_dp_offload_bg_lb.vhd
../../tb/vhdl/tb_compaan_unb1_dp_offload_bg_co.vhd
[modelsim_project_file]
[quartus_project_file]
synth_top_level_entity =
quartus_copy_files = ../../quartus/sopc_compaan_unb1_dp_offload.sopc .
quartus_qsf_files =
......
applications/compaan/designs/compaan_unb1_dp_offload/revisions/compaan_unb1_dp_offload_lb/hdllib.cfg
+ 7
− 5
View file @ b232c8c7
......@@ -3,11 +3,6 @@ hdl_library_clause_name = compaan_unb1_dp_offload_lb_lib
hdl_lib_uses_synth = common unb1_board dp eth tech_tse diag compaan
hdl_lib_technology = ip_stratixiv
build_dir_sim = $HDL_BUILD_DIR
build_dir_synth = $HDL_BUILD_DIR
synth_top_level_entity =
synth_files =
$HDL_BUILD_DIR/unb1/quartus/compaan_unb1_dp_offload_lb/sopc_compaan_unb1_dp_offload.vhd
../../src/vhdl/pkg_signals.vhd
......@@ -22,6 +17,13 @@ test_bench_files =
../../tb/vhdl/tb_compaan_unb1_dp_offload_bg_lb.vhd
../../tb/vhdl/tb_compaan_unb1_dp_offload_bg_co.vhd
[modelsim_project_file]
[quartus_project_file]
synth_top_level_entity =
quartus_copy_files = ../../quartus/sopc_compaan_unb1_dp_offload.sopc .
quartus_qsf_files =
......
applications/compaan/libraries/hdllib.cfg
+ 7
− 1
View file @ b232c8c7
hdl_lib_name = compaan
hdl_library_clause_name = compaan_lib
hdl_lib_uses_synth = common technology ip_arria10_fifo ip_stratixiv_fifo tech_fifo dp ip_stratixiv_ram ip_arria10_ram tech_memory
hdl_lib_technology = ip_stratixiv
synth_files =
......@@ -45,3 +44,10 @@ synth_files =
src/vhdl/ipcore.vhd
test_bench_files =
[modelsim_project_file]
[quartus_project_file]
applications/compaan/libraries/vhdl_altera/compaandesign_com/common/altera/hdllib.cfg
+ 6
− 4
View file @ b232c8c7
......@@ -3,13 +3,15 @@ hdl_library_clause_name = compaandesign_com_common_altera_1_lib
hdl_lib_uses_synth = common dp
hdl_lib_technology = ip_stratixiv
build_dir_sim = $HDL_BUILD_DIR
build_dir_synth = $HDL_BUILD_DIR
# Specify here all the files you want to be included in the library.
synth_files =
src/vhdl/fsl_v20.vhd
test_bench_files =
[modelsim_project_file]
modelsim_copy_files =
[quartus_project_file]
applications/compaan/libraries/vhdl_altera/compaandesign_com/common/common/hdllib.cfg
+ 6
− 4
View file @ b232c8c7
......@@ -3,13 +3,15 @@ hdl_library_clause_name = compaandesign_com_common_common_1_lib
hdl_lib_uses_synth =
hdl_lib_technology = ip_stratixiv
build_dir_sim = $HDL_BUILD_DIR
build_dir_synth = $HDL_BUILD_DIR
# Specify here all the files you want to be included in the library.
synth_files =
src/vhdl/hw_node_pkg.vhd
test_bench_files =
[modelsim_project_file]
modelsim_copy_files =
[quartus_project_file]
applications/compaan/libraries/vhdl_altera/compaandesign_com/common/const_connector/hdllib.cfg
+ 6
− 4
View file @ b232c8c7
......@@ -3,13 +3,15 @@ hdl_library_clause_name = compaandesign_com_common_const_connector_1_lib
hdl_lib_uses_synth =
hdl_lib_technology = ip_stratixiv
build_dir_sim = $HDL_BUILD_DIR
build_dir_synth = $HDL_BUILD_DIR
# Specify here all the files you want to be included in the library.
synth_files =
src/vhdl/const_connector.vhd
test_bench_files =
[modelsim_project_file]
modelsim_copy_files =
[quartus_project_file]
applications/compaan/libraries/vhdl_altera/compaandesign_com/common/extern_connector/hdllib.cfg
+ 6
− 4
View file @ b232c8c7
......@@ -3,13 +3,15 @@ hdl_library_clause_name = compaandesign_com_common_extern_connector_1_lib
hdl_lib_uses_synth =
hdl_lib_technology = ip_stratixiv
build_dir_sim = $HDL_BUILD_DIR
build_dir_synth = $HDL_BUILD_DIR
# Specify here all the files you want to be included in the library.
synth_files =
src/vhdl/extern_connector.vhd
test_bench_files =
[modelsim_project_file]
modelsim_copy_files =
[quartus_project_file]
applications/compaan/libraries/vhdl_altera/compaandesign_com/common/fifo/hdllib.cfg
+ 6
− 4
View file @ b232c8c7
......@@ -3,10 +3,6 @@ hdl_library_clause_name = compaandesign_com_common_fifo_1_lib
hdl_lib_uses_synth = compaandesign_com_common_altera_1
hdl_lib_technology = ip_stratixiv
build_dir_sim = $HDL_BUILD_DIR
build_dir_synth = $HDL_BUILD_DIR
# Specify here all the files you want to be included in the library.
synth_files =
src/vhdl/async_fifo_bram.vhd
src/vhdl/async_fifo.vhd
......@@ -18,4 +14,10 @@ synth_files =
test_bench_files =
[modelsim_project_file]
modelsim_copy_files =
[quartus_project_file]
applications/compaan/libraries/vhdl_altera/compaandesign_com/common/hwnode/hdllib.cfg
+ 6
− 4
View file @ b232c8c7
......@@ -3,10 +3,6 @@ hdl_library_clause_name = compaandesign_com_common_hwnode_1_lib
hdl_lib_uses_synth = compaandesign_com_common_common_1 compaandesign_com_common_altera_1
hdl_lib_technology = ip_stratixiv
build_dir_sim = $HDL_BUILD_DIR
build_dir_synth = $HDL_BUILD_DIR
# Specify here all the files you want to be included in the library.
synth_files =
src/vhdl/controller.vhd
src/vhdl/counter.vhd
......@@ -19,4 +15,10 @@ synth_files =
test_bench_files =
[modelsim_project_file]
modelsim_copy_files =
[quartus_project_file]
applications/compaan/libraries/vhdl_altera/compaandesign_com/common/wire_connector/hdllib.cfg
+ 6
− 4
View file @ b232c8c7
......@@ -3,13 +3,15 @@ hdl_library_clause_name = compaandesign_com_common_wire_connector_1_lib
hdl_lib_uses_synth =
hdl_lib_technology = ip_stratixiv
build_dir_sim = $HDL_BUILD_DIR
build_dir_synth = $HDL_BUILD_DIR
# Specify here all the files you want to be included in the library.
synth_files =
src/vhdl/wire_connector.vhd
test_bench_files =
[modelsim_project_file]
modelsim_copy_files =
[quartus_project_file]
applications/compaan/libraries/vhdl_altera/compaandesign_com/ipcore2rtl/functions/hdllib.cfg
+ 5
− 4
View file @ b232c8c7
......@@ -3,10 +3,6 @@ hdl_library_clause_name = compaandesign_com_ipcore2rtl_functions_1_lib
hdl_lib_uses_synth = compaandesign_com_common_hwnode_1 compaandesign_com_common_common_1
hdl_lib_technology = ip_stratixiv
build_dir_sim = $HDL_BUILD_DIR
build_dir_synth = $HDL_BUILD_DIR
# Specify here all the files you want to be included in the library.
synth_files =
src/vhdl/compaan_outlinedproc0.vhd
src/vhdl/compaan_outlinedproc0_pipeline.vhd
......@@ -17,4 +13,9 @@ synth_files =
test_bench_files =
[modelsim_project_file]
modelsim_copy_files =
[quartus_project_file]
applications/compaan/libraries/vhdl_altera/compaandesign_com/ipcore2rtl/hwn_nd_1/hdllib.cfg
+ 6
− 4
View file @ b232c8c7
......@@ -3,10 +3,6 @@ hdl_library_clause_name = compaandesign_com_ipcore2rtl_hwn_nd_1_1_lib
hdl_lib_uses_synth = compaandesign_com_ipcore2rtl_functions_1 compaandesign_com_common_hwnode_1 compaandesign_com_common_common_1
hdl_lib_technology = ip_stratixiv
build_dir_sim = $HDL_BUILD_DIR
build_dir_synth = $HDL_BUILD_DIR
# Specify here all the files you want to be included in the library.
synth_files =
src/vhdl/ipcore2rtl_hwn_nd_1_execution_unit.vhd
src/vhdl/ipcore2rtl_hwn_nd_1_eval_logic_rd.vhd
......@@ -15,4 +11,10 @@ synth_files =
test_bench_files =
[modelsim_project_file]
modelsim_copy_files =
[quartus_project_file]
applications/compaan/libraries/vhdl_altera/compaandesign_com/ipcore2rtl/hwn_nd_2/hdllib.cfg
+ 6
− 4
View file @ b232c8c7
......@@ -3,10 +3,6 @@ hdl_library_clause_name = compaandesign_com_ipcore2rtl_hwn_nd_2_1_lib
hdl_lib_uses_synth = compaandesign_com_ipcore2rtl_functions_1 compaandesign_com_common_hwnode_1 compaandesign_com_common_common_1
hdl_lib_technology = ip_stratixiv
build_dir_sim = $HDL_BUILD_DIR
build_dir_synth = $HDL_BUILD_DIR
# Specify here all the files you want to be included in the library.
synth_files =
src/vhdl/ipcore2rtl_hwn_nd_2_execution_unit.vhd
src/vhdl/ipcore2rtl_hwn_nd_2_eval_logic_rd.vhd
......@@ -15,4 +11,10 @@ synth_files =
test_bench_files =
[modelsim_project_file]
modelsim_copy_files =
[quartus_project_file]
applications/compaan/libraries/vhdl_altera/compaandesign_com/ipcore2rtl/hwn_nd_3/hdllib.cfg
+ 6
− 4
View file @ b232c8c7
......@@ -3,10 +3,6 @@ hdl_library_clause_name = compaandesign_com_ipcore2rtl_hwn_nd_3_1_lib
hdl_lib_uses_synth = compaandesign_com_ipcore2rtl_functions_1 compaandesign_com_common_hwnode_1 compaandesign_com_common_common_1
hdl_lib_technology = ip_stratixiv
build_dir_sim = $HDL_BUILD_DIR
build_dir_synth = $HDL_BUILD_DIR
# Specify here all the files you want to be included in the library.
synth_files =
src/vhdl/ipcore2rtl_hwn_nd_3_execution_unit.vhd
src/vhdl/ipcore2rtl_hwn_nd_3_eval_logic_rd.vhd
......@@ -15,4 +11,10 @@ synth_files =
test_bench_files =
[modelsim_project_file]
modelsim_copy_files =
[quartus_project_file]
applications/compaan/libraries/vhdl_altera/compaandesign_com/ipcore2rtl/register_rf/hdllib.cfg
+ 6
− 4
View file @ b232c8c7
......@@ -3,13 +3,15 @@ hdl_library_clause_name = compaandesign_com_ipcore2rtl_register_rf_1_lib
hdl_lib_uses_synth =
hdl_lib_technology = ip_stratixiv
build_dir_sim = $HDL_BUILD_DIR
build_dir_synth = $HDL_BUILD_DIR
# Specify here all the files you want to be included in the library.
synth_files =
src/vhdl/register_rf.vhd
test_bench_files =
[modelsim_project_file]
modelsim_copy_files =
[quartus_project_file]
applications/compaan/libraries/vhdl_altera/hdllib.cfg
+ 7
− 5
View file @ b232c8c7
hdl_lib_name = ipcore
hdl_library_clause_name = ipcore_lib
hdl_lib_uses_synth = compaandesign_com_ipcore2rtl_hwn_nd_3_1 compaandesign_com_ipcore2rtl_hwn_nd_1_1 compaandesign_com_ipcore2rtl_register_rf_1 compaandesign_com_ipcore2rtl_hwn_nd_2_1 compaandesign_com_common_altera_1
hdl_lib_technology = ip_stratixiv
build_dir_sim = $HDL_BUILD_DIR
build_dir_synth = $HDL_BUILD_DIR
# Specify here all the files you want to be included in the library.
synth_files =
src/vhdl/ipcore.vhd
src/vhdl/ipcore2rtl_ed_1_ip_wrapper.vhd
......@@ -19,3 +14,10 @@ synth_files =
test_bench_files =
src/vhdl/system_ext_TB.vhd
[modelsim_project_file]
[quartus_project_file]
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Please register or to comment