Merge branch 'master' into L2SDP-846

applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full_wg/disturb2_unb2b_sdp_station_full_wg.vhd

@@ -26,7 +26,7 @@
 --   Contains AIT input stage with WG, oversampled FSUB, XSUB, BF and RING, so without ADC JESD.
 
 
-LIBRARY IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_sdp_station_lib;
+LIBRARY IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_sdp_lib, wpfb_lib, lofar2_unb2b_sdp_station_lib;
 USE IEEE.STD_LOGIC_1164.ALL;
 USE IEEE.NUMERIC_STD.ALL;
 USE common_lib.common_pkg.ALL;
@@ -34,6 +34,9 @@ USE common_lib.common_mem_pkg.ALL;
 USE unb2b_board_lib.unb2b_board_pkg.ALL;
 USE diag_lib.diag_pkg.ALL;
 USE dp_lib.dp_stream_pkg.ALL;
+USE wpfb_lib.wpfb_pkg.ALL;
+USE lofar2_sdp_lib.sdp_pkg.ALL;
+
 
 ENTITY disturb2_unb2b_sdp_station_full_wg IS
   GENERIC (
@@ -44,7 +47,9 @@ ENTITY disturb2_unb2b_sdp_station_full_wg IS
     g_sim_node_nr      : NATURAL := 0;
     g_stamp_date       : NATURAL := 0;  -- Date (YYYYMMDD) -- set by QSF
     g_stamp_time       : NATURAL := 0;  -- Time (HHMMSS)   -- set by QSF
-    g_revision_id      : STRING := ""   -- revision ID     -- set by QSF
+    g_revision_id      : STRING  := "";  -- revision ID     -- set by QSF
+    g_wpfb             : t_wpfb  := c_sdp_wpfb_subbands;
+    g_wpfb_complex     : t_wpfb  := c_sdp_wpfb_complex_subbands
   );
   PORT (
     -- GENERAL
@@ -100,14 +105,16 @@ BEGIN
 
   u_revision : ENTITY lofar2_unb2b_sdp_station_lib.lofar2_unb2b_sdp_station
   GENERIC MAP (
-    g_design_name => g_design_name,
-    g_design_note => g_design_note,
-    g_sim         => g_sim,
-    g_sim_unb_nr  => g_sim_unb_nr,
-    g_sim_node_nr => g_sim_node_nr,
-    g_stamp_date  => g_stamp_date,
-    g_stamp_time  => g_stamp_time,
-    g_revision_id => g_revision_id
+    g_design_name  => g_design_name,
+    g_design_note  => g_design_note,
+    g_sim          => g_sim,
+    g_sim_unb_nr   => g_sim_unb_nr,
+    g_sim_node_nr  => g_sim_node_nr,
+    g_stamp_date   => g_stamp_date,
+    g_stamp_time   => g_stamp_time,
+    g_revision_id  => g_revision_id,
+    g_wpfb         => g_wpfb,
+    g_wpfb_complex => g_wpfb_complex
   )
   PORT MAP (
     -- GENERAL

applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full_wg/hdllib.cfg

@@ -4,12 +4,14 @@ hdl_lib_uses_synth = common mm technology unb2b_board lofar2_unb2b_sdp_station
 hdl_lib_uses_sim = eth 
 hdl_lib_technology = ip_arria10_e1sg
                      
- synth_files =
+synth_files =
     disturb2_unb2b_sdp_station_full_wg.vhd
 
 test_bench_files = 
+    tb_disturb2_unb2b_sdp_station_full_wg.vhd
 
 regression_test_vhdl =
+    tb_disturb2_unb2b_sdp_station_full_wg.vhd
 
 [modelsim_project_file]
 modelsim_copy_files =

applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full_wg/tb_disturb2_unb2b_sdp_station_full_wg.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright 2023
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+--     http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+--
+-- Author: R. van der Walle
+-- Purpose: Self-checking testbench for simulating disturb2_unb2b_sdp_station_wg using WG data.
+--
+-- Description:
+--   MM control actions:
+--
+--   1) Enable calc mode for WG via reg_diag_wg with:
+--      1.
+--        freq = 19.921875MHz (subband 102)
+--        ampl = 0.5 * 2**13
+--      2.
+--        freg = 19.43359375 MHz (subband 99.5)
+--        ampl = 0.5 * 2**13
+--   
+--   2) Read current BSN from reg_bsn_scheduler_wg and write reg_bsn_scheduler_wg 
+--      to trigger start of WG at BSN.
+--     
+--   3) Verify 10GbE output.
+--   
+--
+-- Usage:
+--   > as 7    # default
+--   > as 12   # for detailed debugging
+--   > run -a  
+-- Remark: TB based on tb_lofar2_unb2b_beamformer.vhd
+-------------------------------------------------------------------------------
+LIBRARY IEEE, common_lib, unb2b_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib, lofar2_sdp_lib, wpfb_lib, tech_pll_lib, tr_10GbE_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE IEEE.MATH_REAL.ALL;
+USE common_lib.common_pkg.ALL;
+USE unb2b_board_lib.unb2b_board_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL;
+USE common_lib.common_str_pkg.ALL;
+USE mm_lib.mm_file_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE mm_lib.mm_file_unb_pkg.ALL;
+USE diag_lib.diag_pkg.ALL;
+USE wpfb_lib.wpfb_pkg.ALL;
+USE lofar2_sdp_lib.sdp_pkg.ALL;
+USE tech_pll_lib.tech_pll_component_pkg.ALL;
+
+ENTITY tb_disturb2_unb2b_sdp_station_full_wg IS
+END tb_disturb2_unb2b_sdp_station_full_wg;
+
+ARCHITECTURE tb OF tb_disturb2_unb2b_sdp_station_full_wg IS
+
+  CONSTANT c_sim             : BOOLEAN := TRUE;
+  CONSTANT c_unb_nr          : NATURAL := 0; -- UniBoard 0
+  CONSTANT c_node_nr         : NATURAL := 0; 
+  CONSTANT c_id              : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
+  CONSTANT c_version         : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
+  CONSTANT c_fw_version      : t_unb2b_board_fw_version := (1, 0);
+
+  CONSTANT c_eth_clk_period      : TIME := 8 ns;  -- 125 MHz XO on UniBoard
+  CONSTANT c_ext_clk_period      : TIME := 5 ns;
+  CONSTANT c_bck_ref_clk_period  : TIME := 5 ns;
+  CONSTANT c_sa_clk_period       : TIME := tech_pll_clk_644_period; -- 644MHz
+  CONSTANT c_pps_period          : NATURAL := 1000;
+
+  CONSTANT c_tb_clk_period       : TIME := 100 ps; -- use fast tb_clk to speed up M&C
+  CONSTANT c_cable_delay         : TIME := 12 ns;
+
+  CONSTANT c_nof_block_per_sync  : NATURAL := 16; 
+  CONSTANT c_nof_clk_per_sync    : NATURAL := c_nof_block_per_sync*c_sdp_N_fft; 
+  CONSTANT c_wpfb_sim            : t_wpfb := func_wpfb_set_nof_block_per_sync(c_sdp_wpfb_subbands, c_nof_block_per_sync);
+  CONSTANT c_wpfb_complex_sim    : t_wpfb := func_wpfb_map_real_input_wpfb_parameters_to_complex_input(c_wpfb_sim);
+   
+  -- WG
+  CONSTANT c_full_scale_ampl      : REAL := REAL(2**(c_sdp_W_adc-1)-1);  -- = full scale of WG
+  CONSTANT c_bsn_start_wg         : NATURAL := 2;  -- start WG at this BSN to instead of some BSN, to avoid mismatches in exact expected data values
+  CONSTANT c_ampl_sp              : NATURAL := 2**(c_sdp_W_adc-1) / 2;  -- in number of lsb
+  CONSTANT c_wg_subband_freq_unit : REAL := c_diag_wg_freq_unit/REAL(c_sdp_N_fft);  -- subband freq = Fs/1024 = 200 MSps/1024 = 195312.5 Hz sinus
+  CONSTANT c_wg_freq_offset       : REAL := 0.0/11.0; -- in freq_unit
+  CONSTANT c_subband_sp_0         : REAL := 102.0;  -- Select subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz 
+  CONSTANT c_subband_sp_1         : REAL := 99.5;  -- Select subband at index 99.5 = 99.5/1024 * 200MHz = 19.43359375 MHz
+  CONSTANT c_wg_ampl_lsb          : REAL := c_diag_wg_ampl_unit / c_full_scale_ampl;  -- amplitude in number of LSbit resolution steps
+  CONSTANT c_exp_wg_power_sp      : REAL := REAL(c_ampl_sp**2)/2.0 * REAL(c_sdp_N_fft*c_nof_block_per_sync);
+
+  TYPE t_real_arr IS ARRAY (INTEGER RANGE <>) OF REAL; 
+  TyPE t_slv_64_subbands_arr IS ARRAY (INTEGER RANGE <>) OF t_slv_64_arr(0 TO c_sdp_S_sub_bf);
+
+  -- MM  
+  CONSTANT c_mm_file_reg_ppsh             : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "PIO_PPS";
+  CONSTANT c_mm_file_reg_bsn_source_v2    : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SOURCE_V2";
+  CONSTANT c_mm_file_reg_bsn_scheduler_wg : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SCHEDULER";
+  CONSTANT c_mm_file_reg_diag_wg          : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_WG";
+  CONSTANT c_mm_file_reg_dp_xonoff        : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_DP_XONOFF";
+
+  -- Tb
+  SIGNAL tb_end              : STD_LOGIC := '0';
+  SIGNAL sim_done            : STD_LOGIC := '0';
+  SIGNAL tb_clk              : STD_LOGIC := '0';  
+  SIGNAL rd_data             : STD_LOGIC_VECTOR(c_32-1 DOWNTO 0);
+
+  -- WG
+  SIGNAL dbg_c_exp_wg_power_sp   : REAL := c_exp_wg_power_sp;
+  SIGNAL current_bsn_wg          : STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0);
+
+  -- 10GbE
+  CONSTANT c_exp_beamlet_index    : NATURAL := NATURAL(c_subband_sp_0) * c_sdp_N_pol;
+  CONSTANT c_exp_beamlet_index_os : NATURAL := c_sdp_N_pol_bf * c_sdp_cep_nof_beamlets_per_block + NATURAL(ROUND(c_subband_sp_1)) * c_sdp_N_pol;
+  CONSTANT c_exp_beamlet_re : STD_LOGIC_VECTOR(7 DOWNTO 0) := x"7F"; --Derived from simulation
+  CONSTANT c_exp_beamlet_im : STD_LOGIC_VECTOR(7 DOWNTO 0) := x"81"; --Derived from simulation
+  
+  SIGNAL dbg_beamlet_index_offset : NATURAL := 0;
+
+  SIGNAL beamlet_arr2_re : t_slv_8_arr(c_sdp_R_os * c_sdp_N_pol_bf * c_sdp_cep_nof_beamlets_per_block-1 DOWNTO 0);
+  SIGNAL beamlet_arr2_im : t_slv_8_arr(c_sdp_R_os * c_sdp_N_pol_bf * c_sdp_cep_nof_beamlets_per_block-1 DOWNTO 0);
+
+  SIGNAL tr_10GbE_src_out       : t_dp_sosi;
+  SIGNAL tr_ref_clk_312         : STD_LOGIC := '0';
+  SIGNAL tr_ref_clk_156         : STD_LOGIC := '0';
+  SIGNAL tr_ref_rst_156         : STD_LOGIC := '0';
+
+  -- DUT
+  SIGNAL ext_clk             : STD_LOGIC := '0';
+  SIGNAL pps                 : STD_LOGIC := '0';
+  SIGNAL ext_pps             : STD_LOGIC := '0'; 
+  SIGNAL pps_rst             : STD_LOGIC := '1';
+
+  SIGNAL WDI                 : STD_LOGIC;
+  SIGNAL INTA                : STD_LOGIC;
+  SIGNAL INTB                : STD_LOGIC;
+
+  SIGNAL eth_clk             : STD_LOGIC := '0';
+  SIGNAL eth_txp             : STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 downto 0);
+  SIGNAL eth_rxp             : STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 downto 0);
+
+  SIGNAL sens_scl            : STD_LOGIC;
+  SIGNAL sens_sda            : STD_LOGIC;
+  SIGNAL pmbus_scl           : STD_LOGIC;
+  SIGNAL pmbus_sda           : STD_LOGIC;
+
+  SIGNAL SA_CLK              : STD_LOGIC := '1';
+  SIGNAL si_lpbk_0           : STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 DOWNTO 0);
+   
+BEGIN
+
+  ----------------------------------------------------------------------------
+  -- System setup
+  ----------------------------------------------------------------------------
+  ext_clk <= NOT ext_clk AFTER c_ext_clk_period/2;  -- External clock (200 MHz)
+  eth_clk <= NOT eth_clk AFTER c_eth_clk_period/2;  -- Ethernet ref clock (125 MHz)
+  SA_CLK <= NOT SA_CLK AFTER c_sa_clk_period/2; -- Serial Gigabit IO sa clock (644 MHz)
+  pps_rst <= '0' AFTER c_ext_clk_period*2;
+
+  INTA <= 'H';  -- pull up
+  INTB <= 'H';  -- pull up
+
+  sens_scl <= 'H';  -- pull up
+  sens_sda <= 'H';  -- pull up
+  pmbus_scl <= 'H';  -- pull up
+  pmbus_sda <= 'H';  -- pull up
+
+  ------------------------------------------------------------------------------
+  -- External PPS
+  ------------------------------------------------------------------------------  
+  proc_common_gen_pulse(5, c_pps_period, '1', pps_rst, ext_clk, pps);
+  ext_pps <= pps;
+
+  ------------------------------------------------------------------------------
+  -- DUT
+  ------------------------------------------------------------------------------
+  u_disturb2_unb2b_sdp_station_full_wg : ENTITY work.disturb2_unb2b_sdp_station_full_wg
+  GENERIC MAP (
+    g_design_name            => "disturb2_unb2b_sdp_station_full_wg",
+    g_design_note            => "SIM Disturb2 SDP station full design WG",
+    g_sim                    => c_sim,
+    g_sim_unb_nr             => c_unb_nr,
+    g_sim_node_nr            => c_node_nr,
+    g_wpfb                   => c_wpfb_sim,
+    g_wpfb_complex           => c_wpfb_complex_sim
+  )
+  PORT MAP (
+    -- GENERAL
+    CLK          => ext_clk,
+    PPS          => pps,
+    WDI          => WDI,
+    INTA         => INTA,
+    INTB         => INTB,
+
+    -- Others
+    VERSION      => c_version,
+    ID           => c_id,
+    TESTIO       => open,
+
+    -- I2C Interface to Sensors
+    SENS_SC      => sens_scl,
+    SENS_SD      => sens_sda,
+
+    PMBUS_SC     => pmbus_scl,
+    PMBUS_SD     => pmbus_sda,
+    PMBUS_ALERT  => open,
+
+    -- 1GbE Control Interface
+    ETH_CLK      => eth_clk,
+    ETH_SGIN     => eth_rxp,
+    ETH_SGOUT    => eth_txp,
+
+    -- Transceiver clocks
+    SA_CLK       => SA_CLK,
+    -- front transceivers
+    QSFP_1_RX    => si_lpbk_0, 
+    QSFP_1_TX    => si_lpbk_0, 
+
+    -- LEDs
+    QSFP_LED     => open
+  );
+
+    u_unb2_board_clk644_pll : ENTITY tech_pll_lib.tech_pll_xgmii_mac_clocks
+    PORT MAP (
+      refclk_644 => SA_CLK,
+      rst_in     => pps_rst,
+      clk_156    => tr_ref_clk_156,
+      clk_312    => tr_ref_clk_312,
+      rst_156    => tr_ref_rst_156,
+      rst_312    => OPEN
+    );
+    
+    u_tr_10GbE: ENTITY tr_10GbE_lib.tr_10GbE
+    GENERIC MAP (
+      g_sim           => TRUE,
+      g_sim_level     => 1,
+      g_nof_macs      => 1,
+      g_use_mdio      => FALSE
+    )
+    PORT MAP (
+      -- Transceiver PLL reference clock
+      tr_ref_clk_644      => SA_CLK,
+      tr_ref_clk_312      => tr_ref_clk_312,  -- 312.5      MHz for 10GBASE-R
+      tr_ref_clk_156      => tr_ref_clk_156,  -- 156.25     MHz for 10GBASE-R or for XAUI
+      tr_ref_rst_156      => tr_ref_rst_156,  --                for 10GBASE-R or for XAUI
+    
+      -- MM interface
+      mm_rst              => pps_rst,
+      mm_clk              => tb_clk,
+      
+      -- DP interface
+      dp_rst              => pps_rst,
+      dp_clk              => ext_clk,
+    
+      serial_rx_arr(0)    => si_lpbk_0(0),
+      
+      src_out_arr(0)      => tr_10GbE_src_out
+    );
+
+  ------------------------------------------------------------------------------
+  -- MM slave accesses via file IO
+  ------------------------------------------------------------------------------
+  tb_clk  <= NOT tb_clk AFTER c_tb_clk_period/2;    -- Testbench MM clock
+  
+  p_mm_stimuli : PROCESS
+    VARIABLE v_bsn                   : NATURAL;
+    VARIABLE v_beamlet_index_offset  : NATURAL;  
+  BEGIN
+    -- Wait for DUT power up after reset
+    WAIT FOR 1 us;
+    
+    proc_common_wait_until_hi_lo(ext_clk, ext_pps);
+
+    ----------------------------------------------------------------------------
+    -- Enable UDP offload (dp_xonoff) of beamset 0
+    ----------------------------------------------------------------------------
+    mmf_mm_bus_wr(c_mm_file_reg_dp_xonoff,0 , 1, tb_clk);
+    mmf_mm_bus_wr(c_mm_file_reg_dp_xonoff,2 , 1, tb_clk);
+
+    ----------------------------------------------------------------------------
+    -- Enable BS
+    ----------------------------------------------------------------------------
+    mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 3,                   0, tb_clk);
+    mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 2,                   1, tb_clk);  -- Init BSN = 0
+    mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 1,  c_nof_clk_per_sync, tb_clk);  -- nof_block_per_sync
+    mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 0,        16#00000003#, tb_clk);  -- Enable BS at PPS
+    
+    ----------------------------------------------------------------------------
+    -- Enable WG
+    ----------------------------------------------------------------------------
+    --   0 : mode[7:0]           --> off=0, calc=1, repeat=2, single=3)
+    --       nof_samples[31:16]  --> <= c_ram_wg_size=1024
+    --   1 : phase[15:0]
+    --   2 : freq[30:0]
+    --   3 : ampl[16:0]
+    mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 0, 1024*2**16 + 1, tb_clk);  -- nof_samples, mode calc
+    mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 1, INTEGER(  0.0 * c_diag_wg_phase_unit), tb_clk);  -- phase offset in degrees
+    mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 2, INTEGER((c_subband_sp_0+c_wg_freq_offset) * c_wg_subband_freq_unit), tb_clk);  -- freq
+    mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 3, INTEGER(REAL(c_ampl_sp) * c_wg_ampl_lsb), tb_clk);  -- ampl
+    mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 8, 1024*2**16 + 1, tb_clk);  -- nof_samples, mode calc
+    mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 9, INTEGER(  0.0 * c_diag_wg_phase_unit), tb_clk);  -- phase offset in degrees
+    mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 10, INTEGER((c_subband_sp_1+c_wg_freq_offset) * c_wg_subband_freq_unit), tb_clk);  -- freq
+    mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 11, INTEGER(REAL(c_ampl_sp) * c_wg_ampl_lsb), tb_clk);  -- ampl
+
+    -- Read current BSN
+    mmf_mm_bus_rd(c_mm_file_reg_bsn_scheduler_wg, 0, current_bsn_wg(31 DOWNTO  0), tb_clk);
+    mmf_mm_bus_rd(c_mm_file_reg_bsn_scheduler_wg, 1, current_bsn_wg(63 DOWNTO 32), tb_clk);
+    proc_common_wait_some_cycles(tb_clk, 1);
+    
+    -- Write scheduler BSN to trigger start of WG at next block
+    v_bsn := TO_UINT(current_bsn_wg) + 2;
+    ASSERT v_bsn <= c_bsn_start_wg REPORT "Too late to start WG: " & int_to_str(v_bsn) & " > " & int_to_str(c_bsn_start_wg) SEVERITY ERROR;
+    v_bsn := c_bsn_start_wg;
+    mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 0, v_bsn, tb_clk);  -- first write low then high part
+    mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 1,     0, tb_clk);  -- assume v_bsn < 2**31-1
+    
+    -- Wait for enough WG data and start of sync interval
+    mmf_mm_wait_until_value(c_mm_file_reg_bsn_scheduler_wg, 0,                   -- read BSN low
+                            "UNSIGNED", rd_data, ">=", c_nof_block_per_sync*2,   -- this is the wait until condition
+                            c_sdp_T_sub, tb_clk);
+
+    ---------------------------------------------------------------------------
+    -- Read 10GbE Stream
+    ---------------------------------------------------------------------------
+    FOR BS IN 0 TO 2 LOOP -- Read 3 blocks to make sure we get 1 from each beamset. It can happen that two blocks (but not three) from the same beamset are received back to back.
+      proc_common_wait_until_high(ext_clk, tr_10GbE_src_out.sop);
+      FOR I IN 0 TO 8 LOOP -- Packet header is 9.25 words wide, which can be discarded
+        IF I = 7 THEN
+          v_beamlet_index_offset :=  c_sdp_N_pol_bf * TO_UINT(tr_10GbE_src_out.data(39 DOWNTO 24)); -- Read beamlet index
+          dbg_beamlet_index_offset <= v_beamlet_index_offset;
+        END IF;
+        proc_common_wait_until_high(ext_clk, tr_10GbE_src_out.valid);
+        proc_common_wait_some_cycles(ext_clk, 1);
+      END LOOP;
+  
+      -- First word contains 3 beamlets + 1 header part
+      beamlet_arr2_re(v_beamlet_index_offset + 0) <= tr_10GbE_src_out.data(7 DOWNTO 0);
+      beamlet_arr2_im(v_beamlet_index_offset + 0) <= tr_10GbE_src_out.data(15 DOWNTO 8);
+      beamlet_arr2_re(v_beamlet_index_offset + 1) <= tr_10GbE_src_out.data(23 DOWNTO 16);
+      beamlet_arr2_im(v_beamlet_index_offset + 1) <= tr_10GbE_src_out.data(31 DOWNTO 24);
+      beamlet_arr2_re(v_beamlet_index_offset + 2) <= tr_10GbE_src_out.data(39 DOWNTO 32);
+      beamlet_arr2_im(v_beamlet_index_offset + 2) <= tr_10GbE_src_out.data(47 DOWNTO 40);
+      proc_common_wait_until_high(ext_clk, tr_10GbE_src_out.valid);
+      proc_common_wait_some_cycles(ext_clk, 1);
+      FOR I IN 1 TO (c_sdp_N_pol_bf * c_sdp_cep_nof_beamlets_per_block/4)-1 LOOP
+        beamlet_arr2_re(v_beamlet_index_offset + I*4 -1) <= tr_10GbE_src_out.data(7 DOWNTO 0);
+        beamlet_arr2_im(v_beamlet_index_offset + I*4 -1) <= tr_10GbE_src_out.data(15 DOWNTO 8);
+        beamlet_arr2_re(v_beamlet_index_offset + I*4 +0) <= tr_10GbE_src_out.data(23 DOWNTO 16);
+        beamlet_arr2_im(v_beamlet_index_offset + I*4 +0) <= tr_10GbE_src_out.data(31 DOWNTO 24);
+        beamlet_arr2_re(v_beamlet_index_offset + I*4 +1) <= tr_10GbE_src_out.data(39 DOWNTO 32);
+        beamlet_arr2_im(v_beamlet_index_offset + I*4 +1) <= tr_10GbE_src_out.data(47 DOWNTO 40);
+        beamlet_arr2_re(v_beamlet_index_offset + I*4 +2) <= tr_10GbE_src_out.data(55 DOWNTO 48);
+        beamlet_arr2_im(v_beamlet_index_offset + I*4 +2) <= tr_10GbE_src_out.data(63 DOWNTO 56);
+        proc_common_wait_until_high(ext_clk, tr_10GbE_src_out.valid);
+        proc_common_wait_some_cycles(ext_clk, 1);
+      END LOOP;
+
+      beamlet_arr2_re(v_beamlet_index_offset + c_sdp_N_pol_bf * c_sdp_cep_nof_beamlets_per_block-1) <= tr_10GbE_src_out.data(55 DOWNTO 48);
+      beamlet_arr2_im(v_beamlet_index_offset + c_sdp_N_pol_bf * c_sdp_cep_nof_beamlets_per_block-1) <= tr_10GbE_src_out.data(63 DOWNTO 56);
+    END LOOP;
+
+    ---------------------------------------------------------------------------
+    -- Verify 10GbE UDP offload
+    --------------------------------------------------------------------------- 
+    ASSERT beamlet_arr2_re(c_exp_beamlet_index) = c_exp_beamlet_re REPORT "Wrong 10GbE output (re) on beamset 0" SEVERITY ERROR;
+    ASSERT beamlet_arr2_im(c_exp_beamlet_index) = c_exp_beamlet_im REPORT "Wrong 10GbE output (im) on beamset 0" SEVERITY ERROR;
+    ASSERT beamlet_arr2_re(c_exp_beamlet_index_os) = c_exp_beamlet_re REPORT "Wrong 10GbE output (re) on beamset 1 (shifted subbands)" SEVERITY ERROR;
+    ASSERT beamlet_arr2_im(c_exp_beamlet_index_os) = c_exp_beamlet_im REPORT "Wrong 10GbE output (im) on beamset 1 (shifted subbands)" SEVERITY ERROR;
+
+    ---------------------------------------------------------------------------
+    -- End Simulation 
+    ---------------------------------------------------------------------------   
+    sim_done <= '1';
+    proc_common_wait_some_cycles(ext_clk, 100);
+    proc_common_stop_simulation(TRUE, ext_clk, sim_done, tb_end);
+    WAIT;
+  END PROCESS;
+END tb;

applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd

@@ -56,6 +56,7 @@ ENTITY lofar2_unb2b_sdp_station IS
     g_factory_image          : BOOLEAN := FALSE;
     g_protect_addr_range     : BOOLEAN := FALSE;
     g_wpfb                   : t_wpfb  := c_sdp_wpfb_subbands;
+    g_wpfb_complex           : t_wpfb  := c_sdp_wpfb_complex_subbands;
     g_bsn_nof_clk_per_sync   : NATURAL := c_sdp_N_clk_per_sync;  -- Default 200M, overide for short simulation
     g_scope_selected_subband : NATURAL := 0
   );
@@ -807,6 +808,7 @@ BEGIN
   GENERIC MAP (
     g_sim                    => g_sim,
     g_wpfb                   => g_wpfb,
+    g_wpfb_complex           => g_wpfb_complex,
     g_bsn_nof_clk_per_sync   => g_bsn_nof_clk_per_sync,
     g_scope_selected_subband => g_scope_selected_subband,
     g_no_jesd                => c_revision_select.no_jesd, 

doc/erko_howto_tools.txt

@@ -21,6 +21,7 @@
 * Linux
 * ICT diensten
 * Python
+* Numpy, matplotlib.pyplot
 * Jupyter
 * Graphana
 * Zenodo DOI
@@ -170,10 +171,19 @@ run_rbf unb2b lofar2_unb2b_sdp_station_full_wg
 *******************************************************************************
 * scp from regtest
 *******************************************************************************
+mkdir hdl_build_results/20230108
+scp -rp regtest@dop349:/home/regtest/quartus_build_images_cron.log hdl_build_results/20230108/
+scp -rp regtest@dop349:/home/regtest/git/hdl/build/unb2c/quartus/lofar2_unb2c_sdp_station_full hdl_build_results/20230108/
+scp -rp regtest@dop349:/home/regtest/git/hdl/build/unb2b/quartus/lofar2_unb2b_sdp_station_full_wg hdl_build_results/20230108/
+scp -rp regtest@dop349:/home/regtest/git/hdl/build/unb2c/quartus/disturb2_unb2b_sdp_station_full hdl_build_results/20230108/
+scp -rp regtest@dop349:/home/regtest/git/hdl/build/unb2c/quartus/disturb2_unb2b_sdp_station_full_wg hdl_build_results/20230108/
 
-scp -rp regtest@dop349:/home/regtest/quartus_build_images_cron.log 20221218/
-scp -rp regtest@dop349:/home/regtest/git/hdl/build/unb2c/quartus/lofar2_unb2c_sdp_station_full 20221218/
+du -h -d 2
+df -h /home
 
+Synthesis neemt onegeveer 4GB voor Disturb image en 3GB voor SDP image, dus
+ongeveer 14GB / weekend. De regtest machine heeft nog 500GB vrij, dus we
+kunnen nog ongeveer 35x opslaan, voordat we moeten deleten.
 
 *******************************************************************************
 * Flash and reboot unb2
@@ -1108,6 +1118,27 @@ numpy tutorial:
 https://lwn.net/SubscriberLink/847039/3016fa7278000b77/
 
 
+*******************************************************************************
+* Numpy, matplotlib.pyplot
+*******************************************************************************
+
+a = 20
+plt.figure(figsize=(16, 6))
+plt.subplot(1, 2, 1)
+plt.plot(si_ampls[0:a], si_SSTs_dB[0:a])
+plt.title(f"SST as function of input sine amplitude [0:{a}>")
+plt.xlabel("si_ampl, ni_sigma [q]")
+plt.ylabel("SST [dB]")
+plt.grid()
+
+plt.subplot(1, 2, 2)
+plt.plot(si_ampls[a:], si_SSTs_dB[a:])
+plt.title(f"SST as function of input sine amplitude [{a}:{FS}>")
+plt.xlabel("si_ampl, ni_sigma [q]")
+plt.ylabel("SST [dB]")
+plt.grid()
+
+
 *******************************************************************************
 * Jupyter
 *******************************************************************************