Added technology generic

applications/arts/designs/arts_unb1_sc1/src/generated/arts_unb1_sc1_bg_single_pol.vhd

@@ -45,6 +45,8 @@ LIBRARY bf_lib; --bf_unit
     USE bf_lib.bf_pkg.ALL;
 LIBRARY unb1_board_lib; --ctrl_unb1_board
     USE unb1_board_lib.unb1_board_pkg.ALL;
+LIBRARY technology_lib; --tech
+    USE technology_lib.technology_pkg.ALL;
 
 ENTITY arts_unb1_sc1_bg_single_pol IS
   GENERIC (
@@ -74,7 +76,8 @@ END arts_unb1_sc1_bg_single_pol;
 
 ARCHITECTURE str OF arts_unb1_sc1_bg_single_pol IS
 
-  CONSTANT NOF_TELESCOPES :  NATURAL  := 12;
+  CONSTANT NOF_TELESCOPES :  NATURAL := 16;
+  CONSTANT c_technology   :  INTEGER := c_tech_stratixiv;
 
   -------------------------------------------------------------------------------
   -- mms_diag_block_gen
@@ -184,6 +187,7 @@ BEGIN
   -------------------------------------------------------------------------------
   u_mms_diag_block_gen : ENTITY diag_lib.mms_diag_block_gen
   GENERIC MAP (
+    g_technology         => c_technology,
     g_nof_streams        => c_mms_diag_block_gen_nof_streams,
     g_buf_dat_w          => c_mms_diag_block_gen_data_w,
     g_buf_addr_w         => ceil_log2(TO_UINT(c_mms_diag_block_gen_bg_rst.samples_per_packet)),
@@ -195,7 +199,7 @@ BEGIN
     mm_clk           => mm_clk,
 
     dp_rst           => dp_rst,
-    dp_clk           => dp_clk,
+    dp_clk           => CLK,
 
     out_sosi_arr     => mms_diag_block_gen_src_out_arr,
     out_siso_arr     => mms_diag_block_gen_src_in_arr
@@ -206,13 +210,14 @@ BEGIN
   -------------------------------------------------------------------------------
   u_bf_unit : ENTITY bf_lib.bf_unit
   GENERIC MAP (
+    g_technology           => c_technology,
     g_bf                   => c_bf_unit_bf
 --    g_bf_weights_file_name => c_bf_unit_bf_weights_file_name
 --    g_ss_wide_file_prefix  => c_bf_unit_ss_wide_file_prefix
   )
   PORT MAP (
     dp_rst              => dp_rst,
-    dp_clk              => dp_clk,
+    dp_clk              => CLK,
     mm_rst              => mm_rst,
     mm_clk              => mm_clk,
   
@@ -225,8 +230,8 @@ BEGIN
     reg_st_sst_mosi     => bf_unit_reg_st_sst_mosi,
     reg_st_sst_miso     => bf_unit_reg_st_sst_miso,
                            
-    in_sosi_arr         => bf_unit_snk_in_arr,  
-    in_siso_arr         => bf_unit_snk_out_arr, 
+    in_sosi_arr         => mms_diag_block_gen_src_out_arr,  
+    in_siso_arr         => mms_diag_block_gen_src_in_arr, 
     out_raw_sosi        => bf_unit_raw_src_out,
     out_bst_sosi        => bf_unit_bst_src_out,
     out_qua_sosi        => bf_unit_qua_src_out
@@ -236,14 +241,17 @@ BEGIN
   -- arts_unb1_sc1_offload
   -------------------------------------------------------------------------------
   u_arts_unb1_sc1_offload : ENTITY work.arts_unb1_sc1_offload
+  GENERIC MAP (
+    g_technology                => c_technology
+   )
   PORT MAP (
     mm_rst  => mm_rst,
     mm_clk  => mm_clk,
     
     dp_rst  => dp_rst,
-    dp_clk  => dp_clk,
+    dp_clk  => CLK,
 
-    snk_in  => arts_unb1_sc1_offload_snk_in,
+    snk_in  => bf_unit_raw_src_out,
     snk_out => arts_unb1_sc1_offload_snk_out,
 
     src_out => arts_unb1_sc1_offload_src_out,
@@ -257,12 +265,13 @@ BEGIN
   -------------------------------------------------------------------------------
   u_ctrl_unb1_board : ENTITY unb1_board_lib.ctrl_unb1_board
   GENERIC MAP (
+    g_technology     => c_technology,
     g_sim            => g_sim,
     g_design_name    => c_ctrl_unb1_board_design_name,
     g_stamp_date     => c_ctrl_unb1_board_stamp_date,
     g_stamp_time     => c_ctrl_unb1_board_stamp_time, 
     g_stamp_svn      => c_ctrl_unb1_board_stamp_svn,
-    g_dp_clk_use_pll => TRUE, -- Use internal PLL to generate dp_clk
+    g_dp_clk_use_pll => FALSE, -- Use internal PLL to generate dp_clk
     g_xo_clk_use_pll => TRUE  -- Use internal PLL to generate mm_clk
   )
   PORT MAP (
@@ -279,7 +288,7 @@ BEGIN
     dp_rst                   => dp_rst,
     dp_clk                   => dp_clk,
     dp_rst_in                => dp_rst,  -- Feed dp_clk back in
-    dp_clk_in                => dp_clk,  -- Feed dp_rst back in
+    dp_clk_in                => CLK,  -- Feed dp_rst back in
 
     cal_rec_clk              => cal_rec_clk,