Changed unb1_reorder DDR3 selection to single rank master

applications/unb1_reorder/hdllib.cfg

@@ -3,11 +3,11 @@ hdl_library_clause_name = unb1_reorder_lib
 hdl_lib_uses_synth = common technology mm i2c unb1_board dp eth tech_tse diag io_ddr reorder
 hdl_lib_uses_sim = 
 hdl_lib_technology = ip_stratixiv
-hdl_lib_excludes = ip_stratixiv_ddr3_uphy_4g_800_slave
+hdl_lib_excludes = ip_stratixiv_ddr3_uphy_4g_800_master ip_stratixiv_ddr3_uphy_4g_800_slave ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave
 
 
 synth_files =
-    $HDL_BUILD_DIR/quartus/unb1_reorder/sopc_unb1_reorder.vhd
+    $HDL_BUILD_DIR/unb1/quartus/unb1_reorder/sopc_unb1_reorder.vhd
     src/vhdl/node_unb1_reorder.vhd
     src/vhdl/mmm_unb1_reorder.vhd
     src/vhdl/unb1_reorder.vhd
@@ -37,9 +37,9 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master.qip
-    $RADIOHDL/build/quartus/unb1_reorder/sopc_unb1_reorder.qip
+    $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
+    $RADIOHDL/build/unb1/quartus/unb1_reorder/sopc_unb1_reorder.qip
     
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
+    $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl