corrected ELSIF order

libraries/base/common/src/vhdl/common_counter.vhd

@@ -91,12 +91,12 @@ BEGIN
     nxt_count <= reg_count;
     IF cnt_clr='1' THEN
       nxt_count <= (OTHERS => '0');
+    ELSIF cnt_ld='1' THEN
+      nxt_count <= load;
     ELSIF reg_count=cnt_max THEN
       IF NOT g_clip THEN
         nxt_count <= (OTHERS => '0');
       END IF;
-    ELSIF cnt_ld='1' THEN
-      nxt_count <= load;
     ELSIF cnt_en='1' THEN
       nxt_count <= INCR_UVEC(reg_count, g_step_size);
     END IF;