processed review comments

libraries/base/dp/src/vhdl/dp_block_validate_err.vhd

@@ -39,6 +39,9 @@
 --     The ratio of max / min is used to determine a fifo size for the outgoing
 --     sosi.valid signals. To minimize logic the g_min_block_size can be set to
 --     the expected minimum block size.
+--   . g_fifo_size can be set to g_max_block_size if there is no backpressure.
+--     If there is back pressure on the src_in, the fifo_fill_eop can be used to 
+--     to account for this backpressure by using an g_fifo_size > g_max_block_size.
 -------------------------------------------------------------------------------
 -- REGMAP
 -------------------------------------------------------------------------------
@@ -65,11 +68,11 @@ USE common_lib.common_mem_pkg.ALL;
 ENTITY dp_block_validate_err IS
   GENERIC (
     g_cnt_w              : NATURAL  := c_word_w; -- max is c_word_w due to mm word width
-    g_max_block_size     : POSITIVE := 250;
-    g_min_block_size     : POSITIVE := 1;
+    g_max_block_size     : POSITIVE := 250; -- largest possible incoming block size.
+    g_min_block_size     : POSITIVE := 1;   -- smallest possible incoming block size.
     g_nof_err_counts     : NATURAL  := 8;
     -- fifo generics
-    g_fifo_size          : POSITIVE := 256;
+    g_fifo_size          : POSITIVE := 256; -- fifo size to buffer incoming blocks, should be >= g_max_block_size 
     g_data_w             : NATURAL  := 16;
     g_bsn_w              : NATURAL  := 1;
     g_empty_w            : NATURAL  := 1;

libraries/base/dp/src/vhdl/dp_fifo_fill_eop.vhd

@@ -208,6 +208,9 @@ BEGIN
   END GENERATE;
 
   -- Set rd_eop_cnt outside generate statements to avoid Modelsim warning "Nonresolved signal 'rd_eop_cnt' may have multiple sources".
+  -- This is only the case with INTEGER (sub) types as it does not have a resolve function te decide the value in case of multiple sources
+  -- through GENERATE statements. STD_LOGIC / STD_LOGIC VECTORS do have such a resolve function. Modelsim cannot resolve that the two GENERATE
+  -- statements where g_use_dual_clock = FALSE / TRUE will never be active simultaneously as a GENERATE statement cannot have an ELSE statement.
   rd_eop_cnt <= TO_UINT(reg_rd_eop_cnt) WHEN g_use_dual_clock ELSE wr_eop_cnt;
 
   p_eop_cnt: PROCESS(wr_clk, wr_rst)

libraries/base/dp/tb/vhdl/tb_dp_fifo_fill_eop.vhd

@@ -56,7 +56,8 @@ ENTITY tb_dp_fifo_fill_eop IS
     g_dut_fifo_size       : NATURAL := 128;
     g_dut_fifo_fill       : NATURAL := 100;               -- selectable >= 0 for dp_fifo_fill
     g_dut_use_rd_fill_32b : BOOLEAN := FALSE;
-    g_dut_use_gap         : BOOLEAN := TRUE   
+    g_dut_use_gap         : BOOLEAN := TRUE;   
+    g_dut_use_random_ctrl : BOOLEAN := TRUE   
   );
 END tb_dp_fifo_fill_eop;
 
@@ -100,7 +101,7 @@ ARCHITECTURE tb OF tb_dp_fifo_fill_eop IS
   
   SIGNAL cnt_dat        : STD_LOGIC_VECTOR(c_dp_data_w-1 DOWNTO 0);
   SIGNAL cnt_val        : STD_LOGIC;
-  SIGNAL cnt_en         : STD_LOGIC;
+  SIGNAL cnt_en         : STD_LOGIC := '1'; -- default always active input control.
   
   SIGNAL tx_data        : t_dp_data_arr(0 TO c_tx_latency + c_tx_void)    := (OTHERS=>(OTHERS=>'0'));
   SIGNAL tx_val         : STD_LOGIC_VECTOR(0 TO c_tx_latency + c_tx_void) := (OTHERS=>'0');
@@ -123,7 +124,7 @@ ARCHITECTURE tb OF tb_dp_fifo_fill_eop IS
   SIGNAL out_siso       : t_dp_siso;
   SIGNAL out_sosi       : t_dp_sosi;
   
-  SIGNAL out_ready      : STD_LOGIC;
+  SIGNAL out_ready      : STD_LOGIC := '1'; -- default always active output flow control.
   SIGNAL prev_out_ready : STD_LOGIC_VECTOR(0 TO c_rx_latency);
   SIGNAL out_data       : STD_LOGIC_VECTOR(c_dp_data_w-1 DOWNTO 0);
   SIGNAL out_bsn        : STD_LOGIC_VECTOR(c_dp_data_w-1 DOWNTO 0) := (OTHERS=>'0');
@@ -156,7 +157,7 @@ BEGIN
   proc_dp_sync_interval(clk, sync);
   
   -- Input data
-  cnt_val <= in_ready AND cnt_en AND NOT gap_en;
+  cnt_val <= in_ready AND cnt_en AND NOT gap_en WHEN g_dut_use_random_ctrl ELSE in_ready AND NOT gap_en;
 
 
   proc_dp_cnt_dat(rst, clk, cnt_val, cnt_dat);
@@ -173,8 +174,10 @@ BEGIN
   in_channel <= INCR_UVEC(in_data, c_channel_offset);
 
   -- Stimuli control
-  proc_dp_count_en(rst, clk, sync, lfsr1, state, verify_done, tb_done, cnt_en);
-  proc_dp_out_ready(rst, clk, sync, lfsr2, out_ready);
+    proc_dp_count_en(rst, clk, sync, lfsr1, state, verify_done, tb_done, cnt_en);
+  gen_random_ctrl : IF g_dut_use_random_ctrl GENERATE
+    proc_dp_out_ready(rst, clk, sync, lfsr2, out_ready);
+  END GENERATE;
   
   -- Output verify
   proc_dp_verify_en(c_verify_en_wait, rst, clk, sync, verify_en);

libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_fill_eop.vhd

@@ -45,13 +45,18 @@ END tb_tb_dp_fifo_fill_eop;
 ARCHITECTURE tb OF tb_tb_dp_fifo_fill_eop IS
   SIGNAL tb_end : STD_LOGIC := '0';  -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
 BEGIN
-  -- Try FIFO settings : GENERIC MAP (g_dut_use_dual_clock, g_dut_use_bsn, g_dut_use_empty, g_dut_use_channel, g_dut_use_sync, g_dut_fifo_rl, g_dut_fifo_size, g_dut_fifo_fill, g_dut_use_rd_fill_32b, g_dut_use_gap)
-  u_dut_sc_1          : ENTITY work.tb_dp_fifo_fill_eop GENERIC MAP (g_dut_use_dual_clock => FALSE, g_dut_fifo_rl => 1); 
-  u_dut_dc_1          : ENTITY work.tb_dp_fifo_fill_eop GENERIC MAP (g_dut_use_dual_clock => TRUE,  g_dut_fifo_rl => 1);
-  u_dut_sc_0          : ENTITY work.tb_dp_fifo_fill_eop GENERIC MAP (g_dut_use_dual_clock => FALSE, g_dut_fifo_rl => 0); 
-  u_dut_dc_0          : ENTITY work.tb_dp_fifo_fill_eop GENERIC MAP (g_dut_use_dual_clock => TRUE,  g_dut_fifo_rl => 0);
-  u_dut_sc_1_no_gap   : ENTITY work.tb_dp_fifo_fill_eop GENERIC MAP (g_dut_use_dual_clock => FALSE, g_dut_fifo_rl => 1, g_dut_use_gap => FALSE); 
-  u_dut_dc_1_no_gap   : ENTITY work.tb_dp_fifo_fill_eop GENERIC MAP (g_dut_use_dual_clock => TRUE,  g_dut_fifo_rl => 1, g_dut_use_gap => FALSE);
-  u_dut_sc_0_no_gap   : ENTITY work.tb_dp_fifo_fill_eop GENERIC MAP (g_dut_use_dual_clock => FALSE, g_dut_fifo_rl => 0, g_dut_use_gap => FALSE); 
-  u_dut_dc_0_no_gap   : ENTITY work.tb_dp_fifo_fill_eop GENERIC MAP (g_dut_use_dual_clock => TRUE,  g_dut_fifo_rl => 0, g_dut_use_gap => FALSE);  
+  -- Try FIFO settings : GENERIC MAP (g_dut_use_dual_clock, g_dut_use_bsn, g_dut_use_empty, g_dut_use_channel, g_dut_use_sync, g_dut_fifo_rl, g_dut_fifo_size, g_dut_fifo_fill, g_dut_use_rd_fill_32b, g_dut_use_gap, g_dut_use_random_ctrl)
+  
+  u_dut_sc_1             : ENTITY work.tb_dp_fifo_fill_eop GENERIC MAP (g_dut_use_dual_clock => FALSE, g_dut_fifo_rl => 1, g_dut_use_random_ctrl => FALSE); 
+  u_dut_sc_1_no_gap      : ENTITY work.tb_dp_fifo_fill_eop GENERIC MAP (g_dut_use_dual_clock => FALSE, g_dut_fifo_rl => 1, g_dut_use_random_ctrl => FALSE, g_dut_use_gap => FALSE); 
+  u_dut_dc_1_no_gap      : ENTITY work.tb_dp_fifo_fill_eop GENERIC MAP (g_dut_use_dual_clock => TRUE,  g_dut_fifo_rl => 1, g_dut_use_random_ctrl => FALSE, g_dut_use_gap => FALSE); 
+  u_dut_dc_0_no_gap      : ENTITY work.tb_dp_fifo_fill_eop GENERIC MAP (g_dut_use_dual_clock => TRUE,  g_dut_fifo_rl => 0, g_dut_use_random_ctrl => FALSE, g_dut_use_gap => FALSE); 
+  u_dut_sc_1_rand        : ENTITY work.tb_dp_fifo_fill_eop GENERIC MAP (g_dut_use_dual_clock => FALSE, g_dut_fifo_rl => 1, g_dut_use_random_ctrl => TRUE); 
+  u_dut_dc_1_rand        : ENTITY work.tb_dp_fifo_fill_eop GENERIC MAP (g_dut_use_dual_clock => TRUE,  g_dut_fifo_rl => 1, g_dut_use_random_ctrl => TRUE);
+  u_dut_sc_0_rand        : ENTITY work.tb_dp_fifo_fill_eop GENERIC MAP (g_dut_use_dual_clock => FALSE, g_dut_fifo_rl => 0, g_dut_use_random_ctrl => TRUE); 
+  u_dut_dc_0_rand        : ENTITY work.tb_dp_fifo_fill_eop GENERIC MAP (g_dut_use_dual_clock => TRUE,  g_dut_fifo_rl => 0, g_dut_use_random_ctrl => TRUE);
+  u_dut_sc_1_rand_no_gap : ENTITY work.tb_dp_fifo_fill_eop GENERIC MAP (g_dut_use_dual_clock => FALSE, g_dut_fifo_rl => 1, g_dut_use_random_ctrl => TRUE, g_dut_use_gap => FALSE); 
+  u_dut_dc_1_rand_no_gap : ENTITY work.tb_dp_fifo_fill_eop GENERIC MAP (g_dut_use_dual_clock => TRUE,  g_dut_fifo_rl => 1, g_dut_use_random_ctrl => TRUE, g_dut_use_gap => FALSE);
+  u_dut_sc_0_rand_no_gap : ENTITY work.tb_dp_fifo_fill_eop GENERIC MAP (g_dut_use_dual_clock => FALSE, g_dut_fifo_rl => 0, g_dut_use_random_ctrl => TRUE, g_dut_use_gap => FALSE); 
+  u_dut_dc_0_rand_no_gap : ENTITY work.tb_dp_fifo_fill_eop GENERIC MAP (g_dut_use_dual_clock => TRUE,  g_dut_fifo_rl => 0, g_dut_use_random_ctrl => TRUE, g_dut_use_gap => FALSE);  
 END tb;