Support applying SI per signal input.

applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.fpga.yaml

@@ -199,6 +199,8 @@ peripherals:
   #############################################################################
   
   - peripheral_name: si/si
+    parameter_overrides:
+      - { name: g_nof_streams, value: c_S_pn }
     mm_port_names:
       - REG_SI
       

applications/lofar2/designs/lofar2_unb2c_sdp_station/lofar2_unb2c_sdp_station.fpga.yaml

@@ -199,6 +199,8 @@ peripherals:
   #############################################################################
   
   - peripheral_name: si/si
+    parameter_overrides:
+      - { name: g_nof_streams, value: c_S_pn }
     mm_port_names:
       - REG_SI
       

libraries/dsp/si/si.peripheral.yaml

@@ -8,6 +8,9 @@ hdl_library_description: "Spectral Inversion (SI)"
 peripherals:
   - peripheral_name: si    # pi_si.py
     peripheral_description: "Spectral Inversion control."
+    parameters:
+      # Parameters of si_arr.vhd
+      - { name: g_nof_streams, value: 1 }
     mm_ports:
       # MM port for si_arr.vhd
       - mm_port_name: REG_SI
@@ -15,6 +18,9 @@ peripherals:
         mm_port_description: "In the even Nyquist zones the sampled spectrum gets flipped in frequency. This flip can be compensated for by enabling spectral inversion (SI)."
         fields:
           - - field_name: enable
-              field_description: "When 0 then pass on the array of input signals, when 1 then enable spectral inversion for all the input signals."
+              field_description: |
+                "Set spectral inversion per input signal in [g_nof_streams-1:0].
+                 When enable[i] = 0 then pass on input signal i, when enable[i] = 1
+                 then enable spectral inversion for the input signal i."
               address_offset: 0x0
-              mm_width: 1
+              mm_width: g_nof_streams

libraries/dsp/si/src/vhdl/si_arr.vhd

@@ -56,9 +56,20 @@ END si_arr;
 
 ARCHITECTURE str OF si_arr IS
 
-  CONSTANT c_si_mem_reg : t_c_mem := (c_mem_reg_rd_latency, 1, 1, 1, '0');
+  --TYPE t_c_mem IS RECORD
+  --  latency   : NATURAL;    -- read latency
+  --  adr_w     : NATURAL;
+  --  dat_w     : NATURAL;
+  --  nof_dat   : NATURAL;    -- optional, nof dat words <= 2**adr_w
+  --  init_sl   : STD_LOGIC;  -- optional, init all dat words to std_logic '0', '1' or 'X'
+  --  --init_file : STRING;     -- "UNUSED", unconstrained length can not be in record
+  --END RECORD;
 
-  SIGNAL reg_si_en : STD_LOGIC_VECTOR(c_si_mem_reg.dat_w*c_si_mem_reg.nof_dat-1 DOWNTO 0);
+  -- Use one MM word to fit the si_en bits, so this suits g_nof_streams
+  -- <= c_word_w = 32.
+  CONSTANT c_si_mem_reg : t_c_mem := (c_mem_reg_rd_latency, 1, g_nof_streams, 1, '0');
+
+  SIGNAL reg_si_en : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
 
 BEGIN
 
@@ -88,7 +99,7 @@ BEGIN
     PORT MAP (
       in_sosi   => in_sosi_arr(I), 
       out_sosi  => out_sosi_arr(I), 
-      si_en     => reg_si_en(0), 
+      si_en     => reg_si_en(I),
       clk       => dp_clk,
       rst       => dp_rst
     );