Merge branch 'master' into L2SDP-962

applications/lofar1/RSP/readme_lofar1.txt

@@ -38,8 +38,8 @@ Contents
 References:
 [1] LOFAR1 RSP firmware SVN repository https://svn.astron.nl/Station/trunk/RSP/
 [2] LOFAR1 pft2 reference files https://svn.astron.nl/Station/trunk/RSP/rsp/tb/tc/5.%20Datapath/5.2%20PFT/
-[3] LOFAR1 firmware ported to LOFAR2.0 GIT repository https://git.astron.nl/desp/hdl/-/tree/master/applications/lofar1
-[4] APERTIF DSP firmware (rTwoSDF, filter, fft, wpfb) in LOFAR2.0 GIT repository https://git.astron.nl/desp/hdl/-/tree/master/libraries/dsp
+[3] LOFAR1 firmware ported to LOFAR2.0 GIT repository https://git.astron.nl/rtsd/hdl/-/tree/master/applications/lofar1
+[4] APERTIF DSP firmware (rTwoSDF, filter, fft, wpfb) in LOFAR2.0 GIT repository https://git.astron.nl/rtsd/hdl/-/tree/master/libraries/dsp
 [5] APERTIF PFB MATLAB code in APERTIF firmware SVN repository https://svn.astron.nl/UniBoard_FP7/RadioHDL/trunk/applications/apertif/matlab/apertif_matlab_readme.txt
 
 

applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station.sdc

@@ -97,8 +97,58 @@ set_clock_groups -asynchronous -group [get_clocks {*xcvr_native_a10_0|g_xcvr_nat
 #-group [get_clocks {inst2|xcvr_4ch_native_phy_inst|xcvr_native_a10_0|g_xcvr_native_insts[?]|rx_pma_clk}] \
 #-group [get_clocks {inst2|xcvr_pll_inst|xcvr_fpll_a10_0|tx_bonding_clocks[0]}]
 
+# JESD
+
+# The link_clk has clk contstraint of 100 MHz, but this seems not sufficient to
+# guarantee proper cross clock domain data transfer between the link_clk and
+# the 200 MHz frame_clk. Therefore use set_clock_uncertainty to enforce
+# constraints on link_clk and frame_clk that are somewhat more than Fmax = 200
+# MHz. To get a reasonable Fmax use Fmax reported for designs where the JESD
+# did not show bit errors or sample shifts.
+#
+# For unb2c e.g. Fmax = 218 MHz for link_clk and Fmax = 244 MHz for frame_clk
+# were achieved, so similar as for unb2b. Thererfore choose to use same Fmax
+# values as for unb2b,
+#
+# In Timing Anayser -> Tasks Report Setup Summary -> Start -> Report timing for
+# link_clk yields timing diagram. Paste set_clock_uncertainty constraint in
+# cli -> Report: Regenerate, to update timing results.
+#
+# link_clk 100 MHz:
+#      _________           ____
+#     |         |         |
+#     ^         v         ^
+#  ___|         |_________|
+#     0         5        10 ns
+#             <-----------*  = 5.727 ns for both rise-rise and rise-fall
+#     <------> = 10 - 5.727 = 4.263 ns --> 234 MHz
+#
+# frame_clk 200 MHz:
+#      ____      ____
+#     |    |    |
+#     ^    v    ^
+#  ___|    |____|
+#     0   2.5   5 ns
+#             <-*  = 0.496 ns for both rise-rise and rise-fall
+#     <------> = 5 - 0.496 = 4.504 ns --> 222 MHz
+#
+# Idem use same set_clock_uncertainty for fall-fall and fall_rise. Although
+# maybe only the rise-rise constraint for link_clk is already sufficient.
+
+# Increase clock uncertainty to force link_clk to have Fmax > 234MHz
+set_clock_uncertainty -rise_from [get_clocks {*|iopll_0|link_clk}] -rise_to [get_clocks {*|iopll_0|link_clk}]  5.727
+set_clock_uncertainty -rise_from [get_clocks {*|iopll_0|link_clk}] -fall_to [get_clocks {*|iopll_0|link_clk}]  5.727
+set_clock_uncertainty -fall_from [get_clocks {*|iopll_0|link_clk}] -rise_to [get_clocks {*|iopll_0|link_clk}]  5.727
+set_clock_uncertainty -fall_from [get_clocks {*|iopll_0|link_clk}] -fall_to [get_clocks {*|iopll_0|link_clk}]  5.727
+
+# Increase clock uncertainty to force frame_clk to have Fmax > 222MHz
+set_clock_uncertainty -rise_from [get_clocks {*|iopll_0|frame_clk}] -rise_to [get_clocks {*|iopll_0|frame_clk}]  0.496
+set_clock_uncertainty -rise_from [get_clocks {*|iopll_0|frame_clk}] -fall_to [get_clocks {*|iopll_0|frame_clk}]  0.496
+set_clock_uncertainty -fall_from [get_clocks {*|iopll_0|frame_clk}] -rise_to [get_clocks {*|iopll_0|frame_clk}]  0.496
+set_clock_uncertainty -fall_from [get_clocks {*|iopll_0|frame_clk}] -fall_to [get_clocks {*|iopll_0|frame_clk}]  0.496
+
 # false paths added for the jesd interface as these clocks are independent.
-set_false_path -from [get_clocks {*xcvr_fpll_a10_0|outclk2}] -to [get_clocks {*iopll_0|link_clk}]
-set_false_path -from [get_clocks {*iopll_0|link_clk}] -to [get_clocks {*xcvr_fpll_a10_0|outclk2}]
-set_false_path -from [get_clocks {*xcvr_fpll_a10_0|outclk2}] -to [get_clocks {*iopll_0|frame_clk}]
-set_false_path -from [get_clocks {*iopll_0|frame_clk}] -to [get_clocks {*xcvr_fpll_a10_0|outclk2}]
+#set_false_path -from [get_clocks {*xcvr_fpll_a10_0|outclk2}] -to [get_clocks {*iopll_0|link_clk}]
+#set_false_path -from [get_clocks {*iopll_0|link_clk}] -to [get_clocks {*xcvr_fpll_a10_0|outclk2}]
+#set_false_path -from [get_clocks {*xcvr_fpll_a10_0|outclk2}] -to [get_clocks {*iopll_0|frame_clk}]
+#set_false_path -from [get_clocks {*iopll_0|frame_clk}] -to [get_clocks {*xcvr_fpll_a10_0|outclk2}]

applications/lofar2/doc/prestudy/station2_sdp_firmware_design.txt

@@ -241,9 +241,9 @@ WP 5 SDP plan:  --> https://support.astron.nl/confluence/display/STAT/WP-5+SDP
 - UniBoard2c planning : L2SDP-42
 
 Other:
-  . tools/oneclick/doc/desp_firmware_dag_erko.txt
-  . tools/oneclick/doc/desp_firmware_overview.txt
-  . desp_howtools_erko.txt
+  . tools/oneclick/doc/rtsd_firmware_dag_erko.txt
+  . tools/oneclick/doc/rtsd_firmware_overview.txt
+  . rtsd_howtools_erko.txt
   
 
 *******************************************************************************

applications/lofar2/doc/prestudy/station2_sdp_firmware_planning.txt

@@ -764,7 +764,7 @@ Jira EK: L3 SDP DD Monitoring and Control
            . low TRL of GP
            . tight SDP planning
          - unclear or too little benifit of GP compared to UCP
-         - not used for SDP or DESP future, if we have a SOC then direct
+         - not used for SDP or RTSD future, if we have a SOC then direct
            OPC-UA via TCP/IP
            
 Jira PD: demonstrate unb2b_arp_ping on UniBoard2, to show that the VHDL works
@@ -847,4 +847,4 @@ d) Reviewers
 - subband filterbank
 - subband correlator on one node
 - beamformer output to CEP
-- ring (Cédric Dumez-Viou ?)
+- ring (C�dric Dumez-Viou ?)

applications/lofar2/doc/prestudy/station2_sdp_transient_buffer.txt

@@ -20,7 +20,7 @@ References:
 
 [1] LIFT requirements: https://plm.astron.nl/polarion/#/project/LOFAR2System/wiki/Overview%20pages/LIFT%20Reference
     https://plm.astron.nl/polarion/#/project/LOFAR2System/workitem?id=LOFAR2-11847
-    https://git.astron.nl/desp/hdl/-/blob/L2SDP-857/applications/lofar2/doc/prestudy/lift_sdp_transient_buffer.txt
+    https://git.astron.nl/rtsd/hdl/-/blob/L2SDP-857/applications/lofar2/doc/prestudy/lift_sdp_transient_buffer.txt
 
 [2] https://support.astron.nl/confluence/display/L2M/2022-10-24+LIFT+meeting+notes
     https://support.astron.nl/confluence/display/L2M/2023-02-08+LIFT+meeting+notes

applications/lofar2/doc/prestudy/station2_to_do_erko.txt

@@ -82,7 +82,7 @@ Vijf principes:
 - Learn how gmi_minimal HDL code works to prepare for porting to unb2b_minimal_gmi
 - Update RadioHDL docs
 - Write RadioHDL article
-- Write HDL RL=0 article - desp_hdl_design_article.txt
+- Write HDL RL=0 article - rtsd_hdl_design_article.txt
 - XST : SNR = 1 per visibility for 10000 samples, brigthtest sourcre log 19.5 --> 4.5 dB --> T_int = 1 s is ok.
 - BSP registers:
   . duration of operations : counts time since last power cycle (passive heartbeat)

applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd

@@ -256,10 +256,10 @@ package sdp_pkg is
 
   -- The statistics offload uses the same 1GbE port as the NiosII for M&C. The 1GbE addresses defined in SW and here in FW.
   -- See NiosII code:
-  --   https://git.astron.nl/desp/hdl/-/blob/master/libraries/unb_osy/unbos_eth.h
-  --   https://git.astron.nl/desp/hdl/-/blob/master/libraries/unb_osy/unbos_eth.c
+  --   https://git.astron.nl/rtsd/hdl/-/blob/master/libraries/unb_osy/unbos_eth.h
+  --   https://git.astron.nl/rtsd/hdl/-/blob/master/libraries/unb_osy/unbos_eth.c
   -- and g_base_ip = x"0A63" in:
-  --   https://git.astron.nl/desp/hdl/-/blob/master/boards/uniboard2b/libraries/unb2b_board/src/vhdl/ctrl_unb2b_board.vhd
+  --   https://git.astron.nl/rtsd/hdl/-/blob/master/boards/uniboard2b/libraries/unb2b_board/src/vhdl/ctrl_unb2b_board.vhd
 
   -- Can use same offload time for all statistics, because 1GbE mux will combine them
   -- see https://support.astron.nl/confluence/display/L2M/L3+SDP+Testing+Notebook%3A+Statistics+offload

applications/lofar2/model/readme_lofar2_model.txt

@@ -10,12 +10,12 @@ Contents:
 
 References:
 
-[1] https://git.astron.nl/desp/hdl/-/blob/master/applications/lofar1/FilterTaskForce.zip
+[1] https://git.astron.nl/rtsd/hdl/-/blob/master/applications/lofar1/FilterTaskForce.zip
     found by Andre Gunst from LOFAR1,for overview see readme_FilterTaskForce.txt
 [2] from Andre Gunst
-[3] https://git.astron.nl/desp/hdl/-/blob/master/apertif_matlab/README.md
+[3] https://git.astron.nl/rtsd/hdl/-/blob/master/apertif_matlab/README.md
 
-[4] https://git.astron.nl/desp/hdl/-/blob/master/libraries/dsp/verify_pfb/tb_tb_verify_pfb_wg.vhd
+[4] https://git.astron.nl/rtsd/hdl/-/blob/master/libraries/dsp/verify_pfb/tb_tb_verify_pfb_wg.vhd
 
 
 

doc/erko_firmware_dag.txt

 Author: Eric Kooistra, jan 2018
-Title: Status of FPGA firmware devlopment at DESP
+Title: Status of FPGA firmware devlopment at RTSD
 
 Purpose:
-- Explain how we currently develop FPGA firmware at DESP
+- Explain how we currently develop FPGA firmware at RTSD
 
 1) Develop FPGA hardware boards
   - Review board design document and schematic, so that the board will not contain major bugs and
@@ -287,7 +287,7 @@ Purpose:
   - Write paper on RL = 0 coding style with state reg and pipeline reg clearly separated. The design should also work
     without pipeline. Possibly the pipelining should be added automatically and only where needed.
   
-13) DESP pillars
+13) RTSD pillars
   - All data storage
   
   

doc/erko_firmware_overview.txt

 Author: Eric Kooistra, jan 2018
-Title: Key aspects of FPGA firmware devlopment at DESP
+Title: Key aspects of FPGA firmware devlopment at RTSD
 
 Purpose:
-- Provide a list of key aspects of FPGA firmware devlopment at DESP
+- Provide a list of key aspects of FPGA firmware devlopment at RTSD
 - Identify libraries or toolscript that we could isolate and make public via e.g. OpenCores or GitHub
 - Identify topics that we need to focus on in the future
 
@@ -146,7 +146,7 @@ Purpose:
   - NWO digital special interest group
   - student assignments
   
-11) DESP pillars
+11) RTSD pillars
   - All data storage
   
   

doc/erko_hdl_design_article.txt

@@ -4,8 +4,8 @@ Reset : asynchronous or synchronous ?
 $HDL_WORK/applications/lofar2/doc/prestudy/
 
 Ref:
- $RADIOHDL/tools/oneclick/doc/desp_firmware_dag_erko.txt
- $RADIOHDL/tools/oneclick/doc/desp_firmware_overview.txt
+ $RADIOHDL/tools/oneclick/doc/rtsd_firmware_dag_erko.txt
+ $RADIOHDL/tools/oneclick/doc/rtsd_firmware_overview.txt
 
  https://support.astron.nl/confluence/display/SBe/VHDL+design+patterns+for+RTL+coding
 

doc/erko_howto_tools.txt

@@ -444,7 +444,7 @@ export SVN=${HOME}/svnroot/UniBoard_FP7
 Error : Unavailable library ip_arria10_e1sg_altera_jesd204_180 at 'hdl_lib_uses_sim' key is not disclosed at 'hdl_lib_disclose_library_clause_names' key in library ['ip_arria10_fractional_pll_clk200', 'ip_arria10_fractional_pll_clk125', 'ip_arria10_e3sge3_fractional_pll_clk200', 'ip_arria10_e3sge3_fractional_pll_clk125', 'ip_arria10_e1sg_fractional_pll_clk200', 'ip_arria10_e1sg_fractional_pll_clk125', 'ip_arria10_e2sg_fractional_pll_clk200', 'ip_arria10_e2sg_fractional_pll_clk125']
 
 Temporary fix commented line 4,5 in:
-https://git.astron.nl/desp/hdl/-/blob/L2SDP-36/libraries/technology/ip_arria10_e1sg/jesd204b/hdllib.cfg
+https://git.astron.nl/rtsd/hdl/-/blob/L2SDP-36/libraries/technology/ip_arria10_e1sg/jesd204b/hdllib.cfg
 
 
 *******************************************************************************
@@ -504,8 +504,8 @@ touch .gitignore       # create .gitignore if it does not already exist
 cd ~/git
 git init  # start new repo at this dir, creates .git/
 git clone # get and start with existing repo
-git clone git@git.astron.nl:desp/args.git
-git clone git@git.astron.nl:desp/sampy.git
+git clone git@git.astron.nl:rtsd/args.git
+git clone git@git.astron.nl:rtsd/sampy.git
 
 git status # what is in stage area and what is modified
 git status -uno  # skip unversioned files
@@ -729,10 +729,10 @@ then:
 1) gitlab
    Zorg er voor dat je de GIT repositories hebt op dop386 (10.87.0.186)
    10  git clone https://git.astron.nl/lofar2.0/sdptr
-   12  git clone https://git.astron.nl/desp/hdl
-   13  git clone https://git.astron.nl/desp/radiohdl
-   14  git clone https://git.astron.nl/desp/args
-   15  git clone https://git.astron.nl/desp/upe_gear
+   12  git clone https://git.astron.nl/rtsd/hdl
+   13  git clone https://git.astron.nl/rtsd/radiohdl
+   14  git clone https://git.astron.nl/rtsd/args
+   15  git clone https://git.astron.nl/rtsd/upe_gear
    37  initsdp
 
    scp ~/.gitconfig kooistra@dop386:/home/kooistra    # for default git user name and user email
@@ -853,7 +853,7 @@ then:
 * Markdown
 *******************************************************************************
 
-https://git.astron.nl/desp/args/-/blob/master/Markdown/readme_markdown.txt
+https://git.astron.nl/rtsd/args/-/blob/master/Markdown/readme_markdown.txt
 
 Official guide: https://daringfireball.net/projects/markdown/syntax
 

doc/erko_teaser_talks.txt

@@ -369,4 +369,4 @@ entity dp_requantize is
 
 
 * References:
-  [] Signal statistics, https://git.astron.nl/desp/hdl/-/blob/master/applications/lofar2/model/signal_statistics.ipynb
+  [] Signal statistics, https://git.astron.nl/rtsd/hdl/-/blob/master/applications/lofar2/model/signal_statistics.ipynb

doc/sdp_useful_commands_erko.txt

@@ -202,7 +202,7 @@ Signal input indices:
 
 sdp_rw.py --host 10.99.0.250 --port 4842 -r firmware_version
 
-    https://git.astron.nl/desp/hdl/-/merge_requests/241 met statistics offload fix was op 15 april 2022
+    https://git.astron.nl/rtsd/hdl/-/merge_requests/241 met statistics offload fix was op 15 april 2022
     sdp-arts: 2022-04-13T08.41.35_209979741_lofar2_unb2b_sdp_station_full_wg
     dts-outside: 2022-04-12T10.56.45_b8464ee23_lofar2_unb2c_sdp_station_full
     dts-lcu: 2022-04-29T10.19.39_2c3958e1f_lofar2_unb2c_sdp_station_full

init_hdl.sh

@@ -95,10 +95,10 @@ for altera_dir in ${ALTERA_DIR}/*; do
 done
 
 # source also radiohdl, args and vhdl_style tools
-. ../radiohdl/init_radiohdl.sh
-if [[ -d "${HDL_WORK}/../args" ]]; then
-    . ../args/init_args.sh
+. ${GIT}/radiohdl/init_radiohdl.sh
+if [[ -d "${GIT}/args" ]]; then
+    . ${GIT}/args/init_args.sh
 fi
-if [[ -d "${HDL_WORK}/../vhdlstyle" ]]; then
-    . ../vhdlstyle/init_vhdl_style.sh
+if [[ -d "${GIT}/vhdlstyle" ]]; then
+    . ${GIT}/vhdlstyle/init_vhdl_style.sh
 fi

libraries/base/axi4/src/vhdl/axi4_lite_pkg.vhd

@@ -24,7 +24,7 @@
 --   Package containing usefull definitions for working with AXI4-Lite
 -- Description:
 --   Ported from:
---   https://git.astron.nl/desp/gemini/-/blob/master/libraries/base/axi4/src/vhdl/axi4_lite_pkg.vhd
+--   https://git.astron.nl/rtsd/gemini/-/blob/master/libraries/base/axi4/src/vhdl/axi4_lite_pkg.vhd
 -------------------------------------------------------------------------------
 
 library IEEE, common_lib;

libraries/base/axi4/src/vhdl/axi4_stream_pkg.vhd

@@ -20,7 +20,7 @@
 -- . Reinier van der Walle (edits only, see Original)
 -- Purpose: General AXI stream record defintion
 -- Original:
--- https://git.astron.nl/desp/gemini/-/blob/master/libraries/base/axi4/src/vhdl/axi4_stream_pkg.vhd
+-- https://git.astron.nl/rtsd/gemini/-/blob/master/libraries/base/axi4/src/vhdl/axi4_stream_pkg.vhd
 -- Remarks:
 -- * Choose smallest maximum SOSI slv lengths that fit all use cases, because unconstrained record
 --   fields slv is not allowed.

libraries/base/diag/tb/vhdl/tb_diag_pkg.vhd

@@ -505,7 +505,7 @@ package body tb_diag_pkg is
   -- PROCEDURE proc_diag_measure_cw_ampl_and_phase()
   -- Purpose: Measure ADC/WG amplitude and phase using local sin and cos
   -- Description:
-  -- * similar as done by add_clock_cw_statistics() in https://git.astron.nl/desp/upe_gear/-/blob/master/base/ADC_functions.py
+  -- * similar as done by add_clock_cw_statistics() in https://git.astron.nl/rtsd/upe_gear/-/blob/master/base/ADC_functions.py
   -- * Measure amplitude and phase of WG
   --   . assume integer subband number, so there are integer subband number of sine periods per c_Nsamples input samples.
   --     Hence DC = 0 over each block of c_Nsamples input samples, so no need to measure DC.

libraries/dsp/doc/pfb.txt

@@ -3,9 +3,9 @@
 2) Fixed point numbers: https://support.astron.nl/confluence/display/L2M/L3+SDP+Decision%3A+Definition+of+fixed+point+numbers
 3) Rounding: https://support.astron.nl/confluence/display/L2M/L4+SDPFW+Decision%3A+Number+representation%2C+resizing+and+rounding
 
-4) LOFAR station Polyphase Filterbank (PFB) model in Matlab: https://git.astron.nl/desp/apertif_matlab/-/blob/master/matlab/ The apertif_matlab_readme.txt gives a brief desciption of all files in this repository. The one_pfb.m runs the model.
+4) LOFAR station Polyphase Filterbank (PFB) model in Matlab: https://git.astron.nl/rtsd/apertif_matlab/-/blob/master/matlab/ The apertif_matlab_readme.txt gives a brief desciption of all files in this repository. The one_pfb.m runs the model.
 
-5) PFB implementation in Apertif and in LOFAR2 station firmware: https://git.astron.nl/desp/hdl/-/blob/master/libraries/dsp/fft/doc/ASTRON_SP_054_filterbank_spec_part2.pdf
+5) PFB implementation in Apertif and in LOFAR2 station firmware: https://git.astron.nl/rtsd/hdl/-/blob/master/libraries/dsp/fft/doc/ASTRON_SP_054_filterbank_spec_part2.pdf
 
 Het FIR filter als geheel is symmetrisch, maar per phase is het niet symmetrisch.
 

libraries/dsp/st/doc/st_histogram_status.txt

@@ -15,7 +15,7 @@ new Jira story):
   (see 5c)
 
 Below, for reference, EK copied the left over comments and answers from the
-GitLab merge ( https://git.astron.nl/desp/hdl/-/merge_requests/101 ) of the
+GitLab merge ( https://git.astron.nl/rtsd/hdl/-/merge_requests/101 ) of the
 st_histogram VHDL in L2SDP-151 into L2SDP-143 and then into the master.