Added dp_fifo_fill_core.vhd as basis for dp_fifo_fill_sc.vhd and dp_fifo_fill_dc.vhd.

libraries/base/dp/hdllib.cfg

@@ -30,6 +30,8 @@ synth_files =
     $UNB/Firmware/modules/dp/src/vhdl/dp_fifo_info.vhd
     $UNB/Firmware/modules/dp/src/vhdl/dp_fifo_sc.vhd
     $UNB/Firmware/modules/dp/src/vhdl/dp_fifo_fill.vhd
+    src/vhdl/dp_fifo_fill_core.vhd
+    src/vhdl/dp_fifo_fill_sc.vhd
     $UNB/Firmware/modules/dp/src/vhdl/dp_fifo_dc.vhd
     $UNB/Firmware/modules/dp/src/vhdl/dp_fifo_dc_mixed_widths.vhd
     $UNB/Firmware/modules/dp/src/vhdl/dp_fifo_to_mm.vhd

libraries/base/dp/src/vhdl/dp_fifo_fill_core.vhd

+--------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+--------------------------------------------------------------------------------
+
+-- Purpose:
+--   The FIFO starts outputting data when the output is ready and it has been
+--   filled with more than g_fifo_fill words. Given a fixed frame length, this
+--   is useful when the in_val is throttled while the out_val should not be
+--   inactive valid between out_sop to out_eop. This is necessary for frame
+--   transport over a PHY link without separate data valid signal.
+-- Description:
+--   The FIFO is filled sufficiently for each input frame, as defined by the
+--   sop and then read until the eop.
+-- Remarks:
+-- . Reuse from LOFAR rad_frame_scheduler.vhd and rad_frame_scheduler(rtl).vhd
+-- . For g_fifo_fill=0 this dp_fifo_fill_core defaults to dp_fifo_core.
+-- . The architecture offers two implementations via g_fifo_rl. Use 0 for show
+--   ahead FIFO or 1 for normal FIFO. At the output of dp_fifo_fill_core the
+--   RL=1 independent of g_fifo_rl, the g_fifo_rl only applies to the internal
+--   FIFO. The show ahead FIFO uses the dp_latency_adapter to get to RL 0
+--   internally. The normal FIFO is prefered, because it uses less logic. It
+--   keeps the RL internally also at 1.
+-- . Note that the structure of p_state is idendical in both architectures
+--   for both g_fifo_rl=0 or 1. Hence the implementation of g_fifo_rl=1 with
+--   dp_input_hold is an example of how to use dp_input_hold to get the same
+--   behaviour as if the input had g_fifo_rl=0 as with the show ahead FIFO.
+-- . To view the similarity of the p_state process for both g_fifo_rl e.g.
+--   open the file in two editors or do repeatedly find (F3) on a text
+--   section like 'WHEN s_fill  =>' that only occurs one in each p_state.
+-- . The next_src_out = pend_src_out when src_in.ready='1'. However it is more
+--   clear to only use pend_src_out and explicitely write the condition on
+--   src_in.ready in the code, because then the structure of p_state is the
+--   same for both g_fifo_rl=0 or 1. Furthermore using pend_src_out and 
+--   src_in.ready is often more clear to comprehend then using next_src_out
+--   directly.
+
+LIBRARY IEEE,common_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+USE work.dp_stream_pkg.ALL;
+
+ENTITY dp_fifo_fill_core IS
+  GENERIC (
+    g_use_dual_clock : BOOELAN := FALSE;
+    g_data_w         : NATURAL := 16;
+    g_bsn_w          : NATURAL := 1;
+    g_empty_w        : NATURAL := 1;
+    g_channel_w      : NATURAL := 1;
+    g_error_w        : NATURAL := 1;
+    g_use_bsn        : BOOLEAN := FALSE;
+    g_use_empty      : BOOLEAN := FALSE;
+    g_use_channel    : BOOLEAN := FALSE;
+    g_use_error      : BOOLEAN := FALSE;
+    g_use_sync       : BOOLEAN := FALSE;
+    g_use_complex    : BOOLEAN := FALSE;  -- TRUE feeds the concatenated complex fields (im & re) through the FIFO instead of the data field.
+    g_fifo_fill      : NATURAL := 0;
+    g_fifo_size      : NATURAL := 256;    -- (32+2) * 256 = 1 M9K, g_data_w+2 for sop and eop
+    g_fifo_af_margin : NATURAL := 4;      -- Nof words below max (full) at which fifo is considered almost full
+    g_fifo_rl        : NATURAL := 1       -- use RL=0 for internal show ahead FIFO, default use RL=1 for internal normal FIFO
+  );
+  PORT (
+    wr_rst      : IN  STD_LOGIC;
+    wr_clk      : IN  STD_LOGIC;
+    rd_rst      : IN  STD_LOGIC;
+    rd_clk      : IN  STD_LOGIC;
+    -- Monitor FIFO filling
+    wr_ful      : OUT STD_LOGIC;  -- corresponds to the carry bit of wr_usedw when FIFO is full
+    wr_usedw    : OUT STD_LOGIC_VECTOR(ceil_log2(largest(g_fifo_size, g_fifo_fill + g_fifo_af_margin + 2))-1 DOWNTO 0);  -- = ceil_log2(c_fifo_size)-1 DOWNTO 0
+    rd_usedw    : OUT STD_LOGIC_VECTOR(ceil_log2(largest(g_fifo_size, g_fifo_fill + g_fifo_af_margin + 2))-1 DOWNTO 0);  -- = ceil_log2(c_fifo_size)-1 DOWNTO 0
+    rd_emp      : OUT STD_LOGIC;
+    -- ST sink
+    snk_out     : OUT t_dp_siso;
+    snk_in      : IN  t_dp_sosi;
+    -- ST source
+    src_in      : IN  t_dp_siso;
+    src_out     : OUT t_dp_sosi
+  );
+END dp_fifo_fill_core;
+
+
+ARCHITECTURE rtl OF dp_fifo_fill_core IS
+
+  CONSTANT c_fifo_rl          : NATURAL := sel_a_b(g_fifo_fill=0, 1, g_fifo_rl);
+  CONSTANT c_fifo_fill_margin : NATURAL := g_fifo_af_margin + 2;  -- add +2 extra margin, with tb_dp_fifo_fill it follows that +1 is also enough to avoid almost full when fifo is operating near g_fifo_fill level
+  CONSTANT c_fifo_size        : NATURAL := largest(g_fifo_size, g_fifo_fill + c_fifo_fill_margin);
+  CONSTANT c_fifo_size_w      : NATURAL := ceil_log2(c_fifo_size);
+  
+  -- The FIFO filling relies on framed data, so contrary to dp_fifo_sc the sop and eop need to be used.
+  CONSTANT c_use_ctrl  : BOOLEAN := TRUE;
+  
+  TYPE state_type IS (s_idle, s_fill, s_output, s_xoff);
+  
+  SIGNAL state       : state_type;
+  SIGNAL nxt_state   : state_type;
+  
+  SIGNAL xon_reg     : STD_LOGIC;
+  SIGNAL nxt_xon_reg : STD_LOGIC;
+  
+  SIGNAL rd_siso     : t_dp_siso;
+  SIGNAL rd_sosi     : t_dp_sosi := c_dp_sosi_rst;  -- initialize default values for unused sosi fields;
+  
+  SIGNAL wr_fifo_usedw  : STD_LOGIC_VECTOR(c_fifo_size_w-1 DOWNTO 0);  -- = wr_usedw'RANGE
+  SIGNAL rd_fifo_usedw  : STD_LOGIC_VECTOR(c_fifo_size_w-1 DOWNTO 0);  -- = rd_usedw'RANGE
+  
+  SIGNAL i_src_out   : t_dp_sosi;
+  SIGNAL nxt_src_out : t_dp_sosi;
+  
+  -- Signals for g_fifo_rl=1
+  SIGNAL hold_src_in  : t_dp_siso;
+  SIGNAL pend_src_out : t_dp_sosi;
+  
+BEGIN
+
+  -- Output monitor FIFO filling
+  wr_usedw <= wr_fifo_usedw;
+  rd_usedw <= rd_fifo_usedw;
+
+  gen_dp_fifo_sc : IF g_use_dual_clock=FALSE GENERATE
+    wr_fifo_usedw <= rd_fifo_usedw;
+    
+    u_dp_fifo_sc : ENTITY work.dp_fifo_sc
+    GENERIC MAP (
+      g_data_w         => g_data_w,
+      g_bsn_w          => g_bsn_w,
+      g_empty_w        => g_empty_w,
+      g_channel_w      => g_channel_w,
+      g_error_w        => g_error_w,
+      g_use_bsn        => g_use_bsn,
+      g_use_empty      => g_use_empty,
+      g_use_channel    => g_use_channel,
+      g_use_error      => g_use_error,
+      g_use_sync       => g_use_sync,
+      g_use_ctrl       => c_use_ctrl,
+      g_use_complex    => g_use_complex,
+      g_fifo_size      => c_fifo_size,
+      g_fifo_af_margin => g_fifo_af_margin,
+      g_fifo_rl        => c_fifo_rl
+    )
+    PORT MAP (
+      rst         => rd_rst,
+      clk         => rd_clk,
+      -- Monitor FIFO filling
+      wr_ful      => wr_ful,
+      usedw       => rd_fifo_usedw,
+      rd_emp      => rd_emp,
+      -- ST sink
+      snk_out     => snk_out,
+      snk_in      => snk_in,
+      -- ST source
+      src_in      => rd_siso,  -- for RL = 0 rd_siso.ready acts as read acknowledge, for RL = 1 rd_siso.ready acts as read request
+      src_out     => rd_sosi
+    );
+  END GENERATE;
+  
+  gen_dp_fifo_sc : IF g_use_dual_clock=TRUE GENERATE
+    u_dp_fifo_dc : ENTITY work.dp_fifo_dc
+    GENERIC MAP (
+      g_data_w         => g_data_w,
+      g_bsn_w          => g_bsn_w,
+      g_empty_w        => g_empty_w,
+      g_channel_w      => g_channel_w,
+      g_error_w        => g_error_w,
+      g_use_bsn        => g_use_bsn,
+      g_use_empty      => g_use_empty,
+      g_use_channel    => g_use_channel,
+      g_use_error      => g_use_error,
+      g_use_sync       => g_use_sync,
+      g_use_ctrl       => c_use_ctrl,
+      --g_use_complex    => g_use_complex,
+      g_fifo_size      => c_fifo_size,
+      g_fifo_af_margin => g_fifo_af_margin,
+      g_fifo_rl        => c_fifo_rl
+    )
+    PORT MAP (
+      wr_rst      => wr_rst,
+      wr_clk      => wr_clk,
+      rd_rst      => rd_rst,
+      rd_clk      => rd_clk,
+      -- Monitor FIFO filling
+      wr_ful      => wr_ful,
+      wr_usedw    => wr_fifo_usedw,
+      rd_usedw    => rd_fifo_usedw,
+      rd_emp      => rd_emp,
+      -- ST sink
+      snk_out     => snk_out,
+      snk_in      => snk_in,
+      -- ST source
+      src_in      => rd_siso,  -- for RL = 0 rd_siso.ready acts as read acknowledge, -- for RL = 1 rd_siso.ready acts as read request
+      src_out     => rd_sosi
+    );
+  END GENERATE;
+    
+  no_fill : IF g_fifo_fill=0 GENERATE
+    rd_siso <= src_in;   -- SISO
+    src_out <= rd_sosi;  -- SOSI
+  END GENERATE;  -- no_fill
+  
+  gen_fill : IF g_fifo_fill>0 GENERATE
+  
+    src_out <= i_src_out;
+    
+    p_rd_clk: PROCESS(rd_clk, rd_rst)
+    BEGIN
+      IF rd_rst='1' THEN
+        xon_reg   <= '0';
+        state     <= s_idle;
+        i_src_out <= c_dp_sosi_rst;
+      ELSIF rising_edge(rd_clk) THEN
+        xon_reg   <= nxt_xon_reg;
+        state     <= nxt_state;
+        i_src_out <= nxt_src_out;
+      END IF;
+    END PROCESS;
+    
+    nxt_xon_reg <= src_in.xon;  -- register xon to easy timing closure
+      
+    gen_rl_0 : IF g_fifo_rl=0 GENERATE
+      p_state : PROCESS(state, rd_sosi, src_in, xon_reg, rd_fifo_usedw)
+      BEGIN
+        nxt_state <= state;
+        
+        rd_siso <= src_in;  -- default acknowledge (RL=1) this input when output is ready
+        
+        -- The output register stage increase RL=0 to 1, so it matches RL = 1 for src_in.ready
+        nxt_src_out       <= rd_sosi;
+        nxt_src_out.valid <= '0';   -- default no output
+        nxt_src_out.sop   <= '0';
+        nxt_src_out.eop   <= '0';
+        nxt_src_out.sync  <= '0';
+        
+        CASE state IS
+          WHEN s_idle =>
+            IF xon_reg='0' THEN
+              nxt_state <= s_xoff;
+            ELSE
+              -- read the FIFO until the sop is pending at the output, so discard any valid data between eop and sop
+              IF rd_sosi.sop='0' THEN
+                rd_siso <= c_dp_siso_rdy;   -- acknowledge (RL=0) this input independent of output ready
+              ELSE
+                rd_siso <= c_dp_siso_hold;  -- stop the input, hold the rd_sosi.sop at FIFO output (RL=0)
+                nxt_state <= s_fill;
+              END IF;
+            END IF;
+          WHEN s_fill =>
+            IF xon_reg='0' THEN
+              nxt_state <= s_xoff;
+            ELSE
+              -- stop reading until the FIFO has been filled sufficiently
+              IF UNSIGNED(rd_fifo_usedw)<g_fifo_fill THEN
+                rd_siso <= c_dp_siso_hold;  -- stop the input, hold the pend_src_out.sop
+              ELSE
+                -- if the output is ready, then start outputting the frame
+                IF src_in.ready='1' THEN
+                  nxt_src_out <= rd_sosi;  -- output sop that is still at FIFO output (RL=0)
+                  nxt_state <= s_output;
+                END IF;
+              END IF;
+            END IF;
+          WHEN s_output =>
+            -- if the output is ready continue outputting the frame, ignore xon_reg during this frame
+            IF src_in.ready='1' THEN
+              nxt_src_out <= rd_sosi;  -- output valid
+              IF rd_sosi.eop='1' THEN
+                nxt_state <= s_idle;   -- output eop, so stop reading the FIFO
+              END IF;
+            END IF;
+          WHEN OTHERS => -- s_xoff
+            -- Flush the fill FIFO when xon='0'
+            rd_siso <= c_dp_siso_flush;
+            IF xon_reg='1' THEN
+              nxt_state <= s_idle;
+            END IF;
+        END CASE;
+        
+        -- Pass on frame level flow control
+        rd_siso.xon <= src_in.xon;
+      END PROCESS;
+    END GENERATE;  -- gen_rl_0
+    
+    gen_rl_1 : IF g_fifo_rl=1 GENERATE
+      -- Use dp_hold_input to get equivalent implementation with default RL=1 FIFO.
+      
+      -- Hold the sink input for source output
+      u_snk : ENTITY work.dp_hold_input
+      PORT MAP (
+        rst          => rd_rst,
+        clk          => rd_clk,
+        -- ST sink
+        snk_out      => rd_siso,       -- SISO ready
+        snk_in       => rd_sosi,       -- SOSI
+        -- ST source
+        src_in       => hold_src_in,   -- SISO ready
+        next_src_out => OPEN,          -- SOSI
+        pend_src_out => pend_src_out,
+        src_out_reg  => i_src_out
+      );
+      
+      p_state : PROCESS(state, src_in, xon_reg, pend_src_out, rd_fifo_usedw)
+      BEGIN
+        nxt_state <= state;
+        
+        hold_src_in <= src_in;  -- default request (RL=1) new input when output is ready
+        
+        -- The output register stage matches RL = 1 for src_in.ready
+        nxt_src_out       <= pend_src_out;
+        nxt_src_out.valid <= '0';          -- default no output
+        nxt_src_out.sop   <= '0';
+        nxt_src_out.eop   <= '0';
+        nxt_src_out.sync  <= '0';
+        
+        CASE state IS
+          WHEN s_idle =>
+            IF xon_reg='0' THEN
+              nxt_state <= s_xoff;
+            ELSE
+              -- read the FIFO until the sop is pending at the output, so discard any valid data between eop and sop
+              IF pend_src_out.sop='0' THEN
+                hold_src_in <= c_dp_siso_rdy;   -- request (RL=1) new input independent of output ready
+              ELSE
+                hold_src_in <= c_dp_siso_hold;  -- stop the input, hold the pend_src_out.sop in dp_hold_input
+                nxt_state <= s_fill;
+              END IF;
+            END IF;
+          WHEN s_fill =>
+            IF xon_reg='0' THEN
+              nxt_state <= s_xoff;
+            ELSE
+              -- stop reading until the FIFO has been filled sufficiently
+              IF UNSIGNED(rd_fifo_usedw)<g_fifo_fill THEN
+                hold_src_in <= c_dp_siso_hold;  -- stop the input, hold the pend_src_out.sop
+              ELSE
+                -- if the output is ready, then start outputting the input frame
+                IF src_in.ready='1' THEN
+                  nxt_src_out <= pend_src_out;  -- output sop that is still pending in dp_hold_input
+                  nxt_state <= s_output;
+                END IF;
+              END IF;
+            END IF;
+          WHEN s_output =>
+            -- if the output is ready continue outputting the input frame, ignore xon_reg during this frame
+            IF src_in.ready='1' THEN
+              nxt_src_out <= pend_src_out;  -- output valid
+              IF pend_src_out.eop='1' THEN
+                nxt_state <= s_idle;        -- output eop, so stop reading the FIFO
+              END IF;
+            END IF;
+          WHEN OTHERS => -- s_xon
+            -- Flush the fill FIFO when xon='0'
+            hold_src_in <= c_dp_siso_flush;
+            IF xon_reg='1' THEN
+              nxt_state <= s_idle;
+            END IF;
+        END CASE;
+        
+        -- Pass on frame level flow control
+        hold_src_in.xon <= src_in.xon;
+      END PROCESS;
+    END GENERATE;  -- gen_rl_1
+    
+  END GENERATE;  -- gen_fill
+END rtl;

libraries/base/dp/src/vhdl/dp_fifo_fill_sc.vhd

+--------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+--------------------------------------------------------------------------------
+
+-- Purpose: The FIFO output is available until the next eop only after it has
+--          been filled with more than g_fifo_fill words.
+-- Description: See dp_fifo_fill_core.vhd.
+
+LIBRARY IEEE,common_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+USE work.dp_stream_pkg.ALL;
+
+ENTITY dp_fifo_fill_sc IS
+  GENERIC (
+    g_data_w         : NATURAL := 16;
+    g_bsn_w          : NATURAL := 1;
+    g_empty_w        : NATURAL := 1;
+    g_channel_w      : NATURAL := 1;
+    g_error_w        : NATURAL := 1;
+    g_use_bsn        : BOOLEAN := FALSE;
+    g_use_empty      : BOOLEAN := FALSE;
+    g_use_channel    : BOOLEAN := FALSE;
+    g_use_error      : BOOLEAN := FALSE;
+    g_use_sync       : BOOLEAN := FALSE;
+    g_use_complex    : BOOLEAN := FALSE;  -- TRUE feeds the concatenated complex fields (im & re) through the FIFO instead of the data field.
+    g_fifo_fill      : NATURAL := 0;
+    g_fifo_size      : NATURAL := 256;    -- (32+2) * 256 = 1 M9K, g_data_w+2 for sop and eop
+    g_fifo_af_margin : NATURAL := 4;      -- Nof words below max (full) at which fifo is considered almost full
+    g_fifo_rl        : NATURAL := 1       -- use RL=0 for internal show ahead FIFO, default use RL=1 for internal normal FIFO
+  );
+  PORT (
+    rst         : IN  STD_LOGIC;
+    clk         : IN  STD_LOGIC;
+    
+    -- Monitor FIFO filling
+    wr_ful      : OUT STD_LOGIC;
+    usedw       : OUT STD_LOGIC_VECTOR(ceil_log2(largest(g_fifo_size, g_fifo_fill + g_fifo_af_margin + 2))-1 DOWNTO 0);  -- = ceil_log2(c_fifo_size)-1 DOWNTO 0
+    rd_emp      : OUT STD_LOGIC;
+    
+    -- ST sink
+    snk_out     : OUT t_dp_siso;
+    snk_in      : IN  t_dp_sosi;
+    -- ST source
+    src_in      : IN  t_dp_siso;
+    src_out     : OUT t_dp_sosi
+  );
+END dp_fifo_fill_sc;
+
+
+ARCHITECTURE str OF dp_fifo_fill_sc IS
+BEGIN
+
+  u_dp_fifo_fill_core : ENTITY work.dp_fifo_fill_core
+  GENERIC MAP (
+    g_use_dual_clock => FALSE,
+    g_data_w         => g_data_w,
+    g_bsn_w          => g_bsn_w,
+    g_empty_w        => g_empty_w,
+    g_channel_w      => g_channel_w,
+    g_error_w        => g_error_w,
+    g_use_bsn        => g_use_bsn,
+    g_use_empty      => g_use_empty,
+    g_use_channel    => g_use_channel,
+    g_use_error      => g_use_error,
+    g_use_sync       => g_use_sync,
+    g_use_complex    => g_use_complex,
+    g_fifo_fill      => g_fifo_fill,
+    g_fifo_size      => g_fifo_size,
+    g_fifo_af_margin => g_fifo_af_margin,
+    g_fifo_rl        => g_fifo_rl       
+  )
+  PORT MAP (
+    wr_rst      => rst,
+    wr_clk      => clk,
+    rd_rst      => rst,
+    rd_clk      => clk,
+    -- Monitor FIFO filling
+    wr_ful      => wr_ful,
+    wr_usedw    => OPEN,
+    rd_usedw    => usedw,
+    rd_emp      => rd_emp,
+    -- ST sink
+    snk_out     => snk_out,
+    snk_in      => snk_in,
+    -- ST source
+    src_in      => src_in,
+    src_out     => src_out
+  );
+
+END str;