Clarify io_ddr wr FIFO depth and rd FIFO depth.

applications/lofar2/libraries/sdp/src/vhdl/node_sdp_transient_buffer.vhd

@@ -140,9 +140,9 @@ architecture str of node_sdp_transient_buffer is
   constant c_rs_nof_clk_per_sync  : natural := sel_a_b(g_sim, g_sim_sdp_tbuf.N_clk_per_sync, c_sdp_N_clk_per_sync);
   constant c_bs_block_size        : natural := sel_a_b(g_sim, g_sim_sdp_tbuf.bs_block_size, c_sdp_N_fft);
   constant c_rs_block_size        : natural := sel_a_b(g_sim, g_sim_sdp_tbuf.rs_block_size, c_sdp_tbuf_rs_block_size);
-  constant c_page_data_size       : natural := func_sdp_tbuf_calculate_page_data_size(c_rs_block_size);
-  constant c_page_meta_size       : natural := func_sdp_tbuf_calculate_page_meta_size(c_rs_block_size);
-  constant c_page_size            : natural := c_page_data_size + c_page_meta_size;
+  constant c_page_data_size       : natural := func_sdp_tbuf_calculate_page_data_size(c_rs_block_size);  -- 667
+  constant c_page_meta_size       : natural := func_sdp_tbuf_calculate_page_meta_size(c_rs_block_size);  -- 1
+  constant c_page_size            : natural := c_page_data_size + c_page_meta_size;  -- 668
 
   -- DDR4 controller
   -- . select DDR4 memory for HW or for simulation
@@ -162,11 +162,18 @@ architecture str of node_sdp_transient_buffer is
   --   . wr_fifo_af_xon >=0, Nof words below max (full) at which fifo is considered almost full for snk_out.xon
   --   Fit at least one page in FIFO including wr_fifo_af_margin and add DDR4 refresh time, instead of using largest(
   --   c_page_size, c_ddr4_wr_refresh_len), for some more margin.
-  constant c_ddr4_wr_fifo_af_margin : natural := 8 + 1;  -- = c_wr_fifo_af_margin from io_ddr
-  constant c_ddr4_rd_fifo_af_margin : natural := 8 + 3 * c_ddr4_MB_I.maxburstsize;  -- = c_rd_fifo_af_margin from io_ddr
-  constant c_ddr4_wr_refresh_len    : natural := c_tech_ddr_refresh_ns * c_sdp_f_adc_MHz / 10**3;
+  constant c_ddr4_wr_fifo_af_margin : natural := 8 + 1;  -- = 9 = c_wr_fifo_af_margin from io_ddr
+  constant c_ddr4_rd_fifo_af_margin : natural := 8 + 3 * c_ddr4_MB_I.maxburstsize;  -- = 200 = c_rd_fifo_af_margin
+                                                                                    -- from io_ddr
+  constant c_ddr4_wr_refresh_len    : natural := c_tech_ddr_refresh_ns * c_sdp_f_adc_MHz / 10**3;  -- = 70
+  -- The c_ddr4_wr_fifo_depth = 747 and c_ddr4_rd_fifo_depth = 868 yiels a FIFO depth (= size) of 1024 words of width
+  -- c_ddr4_word_w = 512b. The M20k can fit 20b x 1024, so both wr FIFO and rd FIFO need 512b / 20b = 26 M20k blocks.
+  -- In simulation the wr FIFO only fills a few words < 10 and the rd FIFO < 512, so somewhat less than c_page_size
+  -- number of words. Hence it may be possible to save a factor two in M20k block RAM usage by using
+  -- c_ddr4_wr_fifo_depth = 512 and c_ddr4_rd_fifo_depth = 512 instead of 1024.
   constant c_ddr4_wr_fifo_depth     : natural := c_ddr4_wr_fifo_af_margin + c_page_size + c_ddr4_wr_refresh_len;
-  constant c_ddr4_rd_fifo_depth     : natural := c_ddr4_rd_fifo_af_margin + c_page_size;
+                                                                                          -- = 747
+  constant c_ddr4_rd_fifo_depth     : natural := c_ddr4_rd_fifo_af_margin + c_page_size;  -- = 868
   --   Use wr_fifo_af_xon and u_dp_xonoff_writer to drop packets to avoid io_ddr/wr_fifo overflow.
   constant c_ddr4_wr_fifo_af_xon    : natural := c_page_size;