- Changed behavior of out_val by adding an out_val_ena signal

- 

libraries/dsp/filter/src/vhdl/fil_ppf_ctrl.vhd

@@ -63,21 +63,24 @@ architecture rtl of fil_ppf_ctrl is
   constant c_ctrl_latency       : natural := 1;                               -- due to taps_out_vec register
   constant c_mult_latency       : natural := g_fil_ppf_pipeline.mult_input + g_fil_ppf_pipeline.mult_product + g_fil_ppf_pipeline.mult_output;
   constant c_adder_latency      : natural := ceil_log2(g_fil_ppf.nof_taps) * g_fil_ppf_pipeline.adder_stage;
-
   constant c_filter_zdly        : natural := g_fil_ppf.nof_bands * (2**g_fil_ppf.nof_chan); 
+
   constant c_tot_latency        : natural := g_fil_ppf_pipeline.mem_delay + c_ctrl_latency + c_mult_latency + 
-                                             c_adder_latency + c_filter_zdly + g_fil_ppf_pipeline.requant_remove_lsb + 
+                                             c_adder_latency + g_fil_ppf_pipeline.requant_remove_lsb + 
                                              g_fil_ppf_pipeline.requant_remove_msb;
+                                             
   constant c_single_taps_vec_w  : natural := g_fil_ppf.in_dat_w*g_fil_ppf.nof_taps;                                             
   constant c_taps_vec_w         : natural := c_single_taps_vec_w*g_fil_ppf.nof_streams;
   
   type reg_type is record
     in_dat_arr   : t_in_dat_delay;                             -- Input register for the data
+    init_dly_cnt : integer range 0 to c_filter_zdly;           -- Counter used to overcome the settling time of the filter. 
     val_dly      : std_logic_vector(c_tot_latency-1 downto 0); -- Delay register for the valid signal 
     rd_addr      : std_logic_vector(c_addr_w-1 downto 0);      -- The read address
     wr_addr      : std_logic_vector(c_addr_w-1 downto 0);      -- The write address
     wr_en        : std_logic;                                  -- Write enable signal for the taps memory
     taps_out_vec : std_logic_vector(c_taps_vec_w-1 downto 0);  -- Output register containing the next taps data
+    out_val_ena  : std_logic;                                  -- Output enable 
   end record;
   
   signal r, rin : reg_type; 
@@ -99,6 +102,12 @@ begin
     
     if(r.val_dly(0) = '1') then                                 -- Wait for incoming data
       v.rd_addr := INCR_UVEC(r.rd_addr, 1);
+      if(r.init_dly_cnt < c_filter_zdly) then
+        v.init_dly_cnt := r.init_dly_cnt + 1;
+        v.out_val_ena := '0';
+      else 
+        v.out_val_ena := '1';
+      end if;
     end if;                                     
     
     if(r.val_dly(g_fil_ppf_pipeline.mem_delay+1) = '1') then 
@@ -114,12 +123,14 @@ begin
     end if; 
       
     if(rst = '1') then
+      v.init_dly_cnt := 0;
       v.in_dat_arr   := (others => (others => '0'));
       v.val_dly      := (others => '0');
       v.rd_addr      := (others => '0');
       v.wr_addr      := (others => '0');
       v.wr_en        := '0';  
       v.taps_out_vec := (others => '0');
+      v.out_val_ena  := '0';
     end if;
     
     rin <= v;  
@@ -137,6 +148,6 @@ begin
   taps_wraddr  <= r.wr_addr;
   taps_wren    <= r.wr_en;
   taps_out_vec <= r.taps_out_vec; 
-  out_val      <= r.val_dly(c_tot_latency-1);
+  out_val      <= r.val_dly(c_tot_latency-1) AND r.out_val_ena;
   
 end rtl;