add _e3sge3 option (for unb2a) to technology wrapper

libraries/technology/memory/tech_memory_ram_cr_cw.vhd

@@ -28,6 +28,7 @@ USE technology_lib.technology_select_pkg.ALL;
 -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
 LIBRARY ip_stratixiv_ram_lib;
 LIBRARY ip_arria10_ram_lib;
+LIBRARY ip_arria10_e3sge3_ram_lib;
 
 ENTITY tech_memory_ram_cr_cw IS
   GENERIC (
@@ -67,4 +68,10 @@ BEGIN
     PORT MAP (data, rdaddress, rdclock, wraddress, wrclock, wren, q);
   END GENERATE;
   
+  gen_ip_arria10_e3sge3 : IF g_technology=c_tech_arria10_e3sge3 GENERATE
+    u0 : ip_arria10_e3sge3_ram_cr_cw
+    GENERIC MAP (FALSE, g_adr_w, g_dat_w, g_nof_words, g_rd_latency, g_init_file)
+    PORT MAP (data, rdaddress, rdclock, wraddress, wrclock, wren, q);
+  END GENERATE;
+  
 END ARCHITECTURE;

libraries/technology/memory/tech_memory_ram_crw_crw.vhd

@@ -28,6 +28,7 @@ USE technology_lib.technology_select_pkg.ALL;
 -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
 LIBRARY ip_stratixiv_ram_lib;
 LIBRARY ip_arria10_ram_lib;
+LIBRARY ip_arria10_e3sge3_ram_lib;
 
 ENTITY tech_memory_ram_crw_crw IS
   GENERIC (
@@ -74,4 +75,10 @@ BEGIN
     PORT MAP (address_a, address_b, clock_a, clock_b, data_a, data_b, wren_a, wren_b, q_a, q_b);
   END GENERATE;
   
+  gen_ip_arria10_e3sge3 : IF g_technology=c_tech_arria10_e3sge3 GENERATE
+    u0 : ip_arria10_e3sge3_ram_crw_crw
+    GENERIC MAP (FALSE, g_adr_w, g_dat_w, g_nof_words, g_rd_latency, g_init_file)
+    PORT MAP (address_a, address_b, clock_a, clock_b, data_a, data_b, wren_a, wren_b, q_a, q_b);
+  END GENERATE;
+  
 END ARCHITECTURE;

libraries/technology/memory/tech_memory_ram_crwk_crw.vhd

@@ -28,6 +28,7 @@ USE technology_lib.technology_select_pkg.ALL;
 -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
 LIBRARY ip_stratixiv_ram_lib;
 LIBRARY ip_arria10_ram_lib;
+LIBRARY ip_arria10_e3sge3_ram_lib;
 
 ENTITY tech_memory_ram_crwk_crw IS  -- support different port data widths and corresponding address ranges
   GENERIC (
@@ -76,4 +77,10 @@ BEGIN
     PORT MAP (address_a, address_b, clock_a, clock_b, data_a, data_b, wren_a, wren_b, q_a, q_b);
   END GENERATE;
   
+  gen_ip_arria10_e3sge3 : IF g_technology=c_tech_arria10_e3sge3 GENERATE
+    u0 : ip_arria10_e3sge3_ram_crwk_crw
+    GENERIC MAP (g_adr_a_w, g_dat_a_w, g_adr_b_w, g_dat_b_w, g_nof_words_a, g_nof_words_b, g_rd_latency, g_init_file)
+    PORT MAP (address_a, address_b, clock_a, clock_b, data_a, data_b, wren_a, wren_b, q_a, q_b);
+  END GENERATE;
+  
 END ARCHITECTURE;

libraries/technology/memory/tech_memory_ram_r_w.vhd

@@ -28,6 +28,7 @@ USE technology_lib.technology_select_pkg.ALL;
 -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
 LIBRARY ip_stratixiv_ram_lib;
 LIBRARY ip_arria10_ram_lib;
+LIBRARY ip_arria10_e3sge3_ram_lib;
 
 ENTITY tech_memory_ram_r_w IS
   GENERIC (
@@ -64,4 +65,10 @@ BEGIN
     PORT MAP (clock, data, rdaddress, wraddress, wren, q);
   END GENERATE;
   
+  gen_ip_arria10_e3sge3 : IF g_technology=c_tech_arria10_e3sge3 GENERATE
+    u0 : ip_arria10_e3sge3_ram_r_w
+    GENERIC MAP (FALSE, g_adr_w, g_dat_w, g_nof_words, 1, g_init_file)
+    PORT MAP (clock, data, rdaddress, wraddress, wren, q);
+  END GENERATE;
+  
 END ARCHITECTURE;

libraries/technology/memory/tech_memory_rom_r.vhd

@@ -28,6 +28,7 @@ USE technology_lib.technology_select_pkg.ALL;
 -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
 LIBRARY ip_stratixiv_ram_lib;
 LIBRARY ip_arria10_ram_lib;
+LIBRARY ip_arria10_e3sge3_ram_lib;
 
 ENTITY tech_memory_rom_r IS
   GENERIC (
@@ -68,4 +69,18 @@ BEGIN
     );
   END GENERATE;
   
+  gen_ip_arria10_e3sge3 : IF g_technology=c_tech_arria10_e3sge3 GENERATE
+    -- use ip_arria10_e3sge3_ram_r_w as ROM
+    u0 : ip_arria10_e3sge3_ram_r_w
+    GENERIC MAP (FALSE, g_adr_w, g_dat_w, g_nof_words, 1, g_init_file)
+    PORT MAP (
+      clk         => clock,
+      --data        => ,
+      rdaddress   => address,
+      --wraddress   => ,
+      --wren        => ,
+      q           => q
+    );
+  END GENERATE;
+  
 END ARCHITECTURE;