Support output BSN source nof_clk_per_sync.

applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd

@@ -103,8 +103,9 @@ ENTITY node_sdp_adc_input_and_timing IS
 
     -- Streaming data output
     out_sosi_arr                   : OUT t_dp_sosi_arr(c_sdp_S_pn-1 DOWNTO 0);        
-    dp_bsn_source_restart          : OUT STD_LOGIC;
-    dp_bsn_source_new_interval     : OUT STD_LOGIC
+    dp_bsn_source_restart          : OUT STD_LOGIC;  -- for dp_sync_recover in WPFB
+    dp_bsn_source_new_interval     : OUT STD_LOGIC;  -- for SST and BST statistics offload, XST uses new_interval based on xst_processing_enable
+    dp_bsn_source_nof_clk_per_sync : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0)  -- for RSN source in transient buffer
   );
 END node_sdp_adc_input_and_timing;
 
@@ -131,6 +132,7 @@ ARCHITECTURE str OF node_sdp_adc_input_and_timing IS
 
   SIGNAL rx_bsn_source_restart      : STD_LOGIC;
   SIGNAL rx_bsn_source_new_interval : STD_LOGIC;
+  SIGNAL rx_bsn_source_nof_clk_per_sync : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
   SIGNAL rx_aux                     : STD_LOGIC_VECTOR(c_bs_aux_w-1 DOWNTO 0);
   SIGNAL dp_aux                     : STD_LOGIC_VECTOR(c_bs_aux_w-1 DOWNTO 0);
 
@@ -288,7 +290,8 @@ BEGIN
     bs_sosi           => bs_sosi,
 
     bs_restart        => rx_bsn_source_restart,
-    bs_new_interval   => rx_bsn_source_new_interval
+    bs_new_interval   => rx_bsn_source_new_interval,
+    bs_nof_clk_per_sync => rx_bsn_source_nof_clk_per_sync
   );
 
   u_bsn_trigger_wg : ENTITY dp_lib.mms_dp_bsn_scheduler
@@ -533,6 +536,19 @@ BEGIN
       out_aux          => dp_aux
     );
 
+  -- MM write of rx_bsn_source_nof_clk_per_sync occurs with sufficient margin before it
+  -- is used. Still use common_reg_cross_domain nonetheless to get from mm_clk to rx_clk
+  -- in mms_dp_bsn_monitor, and from rx_clk to dp_clk here. No need to go via
+  -- u_dp_fifo_dc_arr, use common_reg_cross_domain instead to save logic and/or RAM.
+  u_dp_nof_block_per_sync : ENTITY common_lib.common_reg_cross_domain
+  PORT MAP (
+    in_rst      => rx_rst,
+    in_clk      => rx_clk,
+    in_dat      => rx_bsn_source_nof_clk_per_sync,
+    out_rst     => dp_rst,
+    out_clk     => dp_clk,
+    out_dat     => dp_bsn_source_nof_clk_per_sync
+  );
 
   -----------------------------------------------------------------------------
   -- JESD Control register

libraries/base/dp/src/vhdl/mms_dp_bsn_source_v2.vhd

@@ -53,7 +53,8 @@ ENTITY mms_dp_bsn_source_v2 IS
     bs_sosi           : OUT t_dp_sosi;
 
     bs_restart        : OUT STD_LOGIC;  -- pulse to indicate if the bsn_source has restarted
-    bs_new_interval   : OUT STD_LOGIC   -- level to indicate first sync interval if the bsn_source has restarted
+    bs_new_interval   : OUT STD_LOGIC;  -- level to indicate first sync interval if the bsn_source has restarted
+    bs_nof_clk_per_sync : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0)
   );
 END mms_dp_bsn_source_v2;
 
@@ -75,6 +76,7 @@ ARCHITECTURE str OF mms_dp_bsn_source_v2 IS
 BEGIN
 
   bs_sosi <= i_bs_sosi;
+  bs_nof_clk_per_sync <= nof_clk_per_sync;
 
   u_mm_reg : ENTITY work.dp_bsn_source_reg_v2
   GENERIC MAP (