Skip to content
Snippets Groups Projects
Commit acd29819 authored by Eric Kooistra's avatar Eric Kooistra
Browse files

Add short block len tb.

parent 43bc9819
No related branches found
No related tags found
1 merge request!288Resolve L2SDP-836
Pipeline #38567 passed
Stage: simulation
Stage: synthesis
Show whitespace changes
Inline Side-by-side
libraries/io/eth/tb/vhdl/tb_tb_eth_tester.vhd
+ 39
− 15
View file @ acd29819
......@@ -40,7 +40,7 @@ END tb_tb_eth_tester;
ARCHITECTURE tb OF tb_tb_eth_tester IS
-- Multi tb
CONSTANT c_tb_w : NATURAL := 60; -- sufficiently long to fit all tb instances
CONSTANT c_tb_w : NATURAL := 100; -- sufficiently long to fit all tb instances
CONSTANT c_tb_end_vec : STD_LOGIC_VECTOR(c_tb_w-1 DOWNTO 0) := (OTHERS=>'1');
SIGNAL tb_end_vec : STD_LOGIC_VECTOR(c_tb_w-1 DOWNTO 0) := c_tb_end_vec; -- best view as hex in Wave Window
......@@ -66,6 +66,7 @@ ARCHITECTURE tb OF tb_tb_eth_tester IS
-- Choose c_gap_len somewhat larger to have packet link rate < 1 Gbps
CONSTANT c_gap_len : NATURAL := c_gap_len_min * 2; -- for g_nof_streams = 1
CONSTANT c_long_gap : NATURAL := c_gap_len_min * 10;
CONSTANT c_short_gap : NATURAL := 10; -- to cause BG xon/xoff flow control
CONSTANT c_zero_gap : NATURAL := 0; -- to verify BG ready flow control
......@@ -110,9 +111,9 @@ BEGIN
-- g_bg_ctrl_others : t_diag_block_gen_integer := ('1', '1', 30, 8, 10, 0, 30, 0) -- for other streams
-- Tb instance prefix:
-- . st = streaming Tx-Rx interface
-- . sim = sim_tse Tx-Rx interface
-- . tech = tech_tse Tx-Rx interface
-- . u_st : uses streaming Tx-Rx interface
-- . u_sim : uses sim_tse Tx-Rx interface
-- . u_tech : uses tech_tse Tx-Rx interface
-----------------------------------------------------------------------------
-- Single stream
......@@ -122,13 +123,13 @@ BEGIN
u_sim_tse : ENTITY work.tb_eth_tester GENERIC MAP (1, c_nof_sync, 1, TRUE, 1, c_bg_ctrl_one, c_bg_ctrl_rst) PORT MAP (tb_end_vec(1));
u_tech_tse : ENTITY work.tb_eth_tester GENERIC MAP (2, c_nof_sync, 1, TRUE, 0, c_bg_ctrl_one, c_bg_ctrl_rst) PORT MAP (tb_end_vec(2));
-- Try nof blocks_per_sync = 1
-- Try large block size and nof blocks_per_sync = 1
u_st_jumbo1 : ENTITY work.tb_eth_tester GENERIC MAP (10, c_nof_sync, 1, FALSE, 1,
('1', '1', c_block_len_jumbo, 1, c_zero_gap, 0, c_high, 0),
c_bg_ctrl_rst)
PORT MAP (tb_end_vec(10));
-- Try large block size
-- Try large block sizes
u_st_jumbo2 : ENTITY work.tb_eth_tester GENERIC MAP (11, c_nof_sync, 1, FALSE, 1,
('1', '1', c_block_len_jumbo, 2, c_zero_gap, 0, c_high, 0),
c_bg_ctrl_rst)
......@@ -139,6 +140,29 @@ BEGIN
c_bg_ctrl_rst)
PORT MAP (tb_end_vec(12));
u_tech_tse_jumbo : ENTITY work.tb_eth_tester GENERIC MAP (13, c_nof_sync, 1, TRUE, 0,
('1', '1', c_block_len_jumbo, 2, c_zero_gap, 0, c_high, 0),
c_bg_ctrl_rst)
PORT MAP (tb_end_vec(13));
-- Try small block sizes
-- . BG supports samples_per_packet >= 2, BG treats samples_per_packet = 1 as 2
-- . ETH MAC pads samples_per_packet <= 6 to 6, to have minimum packet length of 64 octets,
-- because hdr = 14 + 20 + 8 + 12 and crc = 4 have 58 octets.
u_st_len2 : ENTITY work.tb_eth_tester GENERIC MAP (20, c_nof_sync, 1, FALSE, 1,
('1', '1', 2, 8, c_gap_len, 0, c_high, 0),
c_bg_ctrl_rst)
PORT MAP (tb_end_vec(20));
u_sim_tse_len2 : ENTITY work.tb_eth_tester GENERIC MAP (21, c_nof_sync, 1, TRUE, 1,
('1', '1', 2, 8, c_gap_len, 0, c_high, 0),
c_bg_ctrl_rst)
PORT MAP (tb_end_vec(21));
u_tech_tse_len6 : ENTITY work.tb_eth_tester GENERIC MAP (22, c_nof_sync, 1, TRUE, 0,
('1', '1', 6, 8, c_gap_len, 0, c_high, 0),
c_bg_ctrl_rst)
PORT MAP (tb_end_vec(22));
-- Try different BG block lengths to verify sosi.empty nof octets in last word
u_st_bg_len_0 : ENTITY work.tb_eth_tester GENERIC MAP (30, c_nof_sync, 1, FALSE, 1, c_bg_ctrl_len_0, c_bg_ctrl_rst) PORT MAP (tb_end_vec(30));
u_st_bg_len_1 : ENTITY work.tb_eth_tester GENERIC MAP (31, c_nof_sync, 1, FALSE, 1, c_bg_ctrl_len_1, c_bg_ctrl_rst) PORT MAP (tb_end_vec(31));
......@@ -167,23 +191,23 @@ BEGIN
-- Multiple streams
-----------------------------------------------------------------------------
u_st_multiple_streams : ENTITY work.tb_eth_tester
GENERIC MAP (50, c_nof_sync, c_nof_streams, FALSE, 1,
GENERIC MAP (80, c_nof_sync, c_nof_streams, FALSE, 1,
c_bg_ctrl_multiple_first,
c_bg_ctrl_multiple_others)
PORT MAP (tb_end_vec(50));
PORT MAP (tb_end_vec(80));
-- Use tse to verify dp_mux and dp_demux in ETH module [1]
u_sim_tse_multiple_streams : ENTITY work.tb_eth_tester
GENERIC MAP (51, c_nof_sync, c_nof_streams, TRUE, 1,
GENERIC MAP (81, c_nof_sync, c_nof_streams, TRUE, 1,
c_bg_ctrl_multiple_first,
c_bg_ctrl_multiple_others)
PORT MAP (tb_end_vec(51));
PORT MAP (tb_end_vec(81));
u_sim_tse_multiple_bg_flow_control : ENTITY work.tb_eth_tester
GENERIC MAP (52, c_nof_sync_many, c_nof_streams, TRUE, 1,
GENERIC MAP (82, c_nof_sync_many, c_nof_streams, TRUE, 1,
('1', '1', c_block_len, 8, c_short_gap, 0, c_high, 0),
('1', '1', c_others_len, 8, c_short_gap, 0, c_high, 0))
PORT MAP (tb_end_vec(52));
PORT MAP (tb_end_vec(82));
tb_end <= '1' WHEN tb_end_vec = c_tb_end_vec ELSE '0';
......
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Please register or to comment